[PATCH i-g-t 2/3] tests/intel/xe_exec_store: Enforce per-instruction copy limit for MEM_COPY

[nishit.sharma@intel.com]

From: Nishit Sharma <nishit.sharma@intel.com>

In this test the copy limit for MEM_COPY instruction is enforced to max
data for linear mode.

Signed-off-by: Nishit Sharma <nishit.sharma@intel.com>
---
 tests/intel/xe_exec_store.c | 38 +++++++++++++++++++++++++------------
 1 file changed, 26 insertions(+), 12 deletions(-)

diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
index 989d9e6b9..5930f16e5 100644
--- a/tests/intel/xe_exec_store.c
+++ b/tests/intel/xe_exec_store.c
@@ -28,6 +28,7 @@
 
 #define STORE 0
 #define COND_BATCH 1
+#define MAX_DATA_WRITE ((size_t)(262143)) //Maximum data MEM_COPY operate for linear mode
 
 struct data {
 	uint32_t batch[16];
@@ -437,13 +438,17 @@ static void mem_transection_ordering(int fd, size_t bo_size, bool fence)
 	int count = 3; // src, bounce, dest, batch
 	int i, b = 0;
 	uint64_t offset[count];
+	uint64_t dst_offset;
+	uint64_t src_offset;
 	uint32_t exec_queues, vm, syncobjs;
 	uint32_t bo[count], *bo_map[count];
 	uint64_t ahnd;
 	uint32_t *batch_map;
 	int src_idx = 0, dst_idx = 1;
+	size_t bytes_written, size;
 
-	bo_size = xe_bb_size(fd, bo_size);
+	bo_size = ALIGN(bo_size, xe_get_default_alignment(fd));
+	bytes_written = bo_size;
 	vm = xe_vm_create(fd, 0, 0);
 	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
 	exec_queues = xe_exec_queue_create(fd, vm, &inst, 0);
@@ -467,16 +472,25 @@ static void mem_transection_ordering(int fd, size_t bo_size, bool fence)
 	for (i = 0; i < bo_size; i++)
 		((uint8_t *)bo_map[src_idx])[i] = i % bo_size;
 
-	batch_map[b++] = MEM_COPY_CMD;
-	batch_map[b++] = bo_size - 1;// src # of bytes
-	batch_map[b++] = 0; //src height
-	batch_map[b++] = -1; // src pitch
-	batch_map[b++] = -1; // dist pitch
-	batch_map[b++] = offset[src_idx];
-	batch_map[b++] = offset[src_idx]  >> 32;
-	batch_map[b++] = offset[dst_idx];
-	batch_map[b++] = offset[dst_idx]  >> 32;
-	batch_map[b++] = intel_get_uc_mocs_index(fd) << 25 | intel_get_uc_mocs_index(fd);
+	dst_offset = offset[dst_idx];
+	src_offset = offset[src_idx];
+	while (bo_size) {
+		size = min(MAX_DATA_WRITE, bo_size);
+		batch_map[b++] = MEM_COPY_CMD;
+		batch_map[b++] = size - 1;// src # of bytes
+		batch_map[b++] = 0; //src height
+		batch_map[b++] = -1; // src pitch
+		batch_map[b++] = -1; // dist pitch
+		batch_map[b++] = src_offset;
+		batch_map[b++] = src_offset  >> 32;
+		batch_map[b++] = dst_offset;
+		batch_map[b++] = dst_offset  >> 32;
+		batch_map[b++] = intel_get_uc_mocs_index(fd) << 25 | intel_get_uc_mocs_index(fd);
+
+		src_offset += size;
+		dst_offset += size;
+		bo_size -= size;
+	}
 	if (fence)
 		batch_map[b++] = MI_MEM_FENCE | MI_WRITE_FENCE;
 
@@ -489,7 +503,7 @@ static void mem_transection_ordering(int fd, size_t bo_size, bool fence)
 	igt_assert(syncobj_wait(fd, &syncobjs, 1, INT64_MAX, 0, NULL));
 
 	if (fence) {
-		igt_assert(memcmp(bo_map[src_idx], bo_map[dst_idx], bo_size) == 0);
+		igt_assert(memcmp(bo_map[src_idx], bo_map[dst_idx], bytes_written) == 0);
 	} else {
 		bool detected_out_of_order = false;
 
-- 
2.34.1