[PATCH i-g-t 0/2] Add memory write ordering verification

[nishit.sharma@intel.com]

From: Nishit Sharma <nishit.sharma@intel.com>

The patch series introduce a new gynamic subtest which verifies memory
relax ordering using copy and write operations across different memory
regions and buffer sizes (1M, 2M, 8M). For each memory region, the test
checks both copy and write transaction ordering to ensure correct memory
behavior on Intel GPUs.

ver2:
- Incorporated review comments (Priyanka)
- Created single patch using two commits
- Nits incorporated

Nishit Sharma (2):
  tests/intel/xe_exec_store: Validate PCIe6 relax ordering
  tests/intel/xe_exec_store: Extend test coverage to all memory regions

 tests/intel/xe_exec_store.c | 230 ++++++++++++++++++++++++++++++------
 1 file changed, 197 insertions(+), 33 deletions(-)

-- 
2.34.1