[PATCH i-g-t 0/4] Enable and Add new tests for DC3CO

[PATCH i-g-t 0/4] Enable and Add new tests for DC3CO

[Jeevan B]

Enable DC3CO tests for PSR/PR for display versions >= 35, add a new
test for DC3CO to validate frame drops, and test DC3CO with LOBF.

Jeevan B (4):
  tests/intel/kms_pm_dc: Replace require with proper assertion
  tests/intel/kms_pm_dc: Enable DC3CO test for PSR2/PR modes
  tests/kms_vrr: Add new test for DC3CO validation with LOBF
  tests/intel/kms_pm_dc: Add new test for dc3co framedrop validation

 tests/intel/kms_pm_dc.c | 120 ++++++++++++++++++++++++++++++++++++----
 tests/kms_vrr.c         |  30 ++++++++++
 2 files changed, 139 insertions(+), 11 deletions(-)

-- 
2.43.0

[PATCH i-g-t 1/4] tests/intel/kms_pm_dc: Replace require with proper assertion

[Jeevan B]

The DC3CO video playback simulation test was incorrectly using require at
the end to check if DC3CO state was entered. This causes the test to be
marked as SKIP instead of FAIL when DC3CO doesn't work properly, hiding
real issues. So changing the call from require to assert.

Fixes: b89efa8048e58 ("tests/i915/i915_pm_dc: Check dc3co count to skip the test")
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/intel/kms_pm_dc.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 39e94f36b..507b6168d 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -312,8 +312,7 @@ static void check_dc3co_with_videoplayback_like_load(data_t *data)
 		usleep(delay);
 	}
 
-	igt_require_f(igt_dc_state_wait_entry(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO,
-					      dc3co_prev_cnt), "dc3co-vpb-simulation not enabled\n");
+	check_dc_counter(data, IGT_INTEL_CHECK_DC3CO, dc3co_prev_cnt);
 }
 
 static void setup_dc3co(data_t *data)
-- 
2.43.0

[PATCH i-g-t 2/4] tests/intel/kms_pm_dc: Enable DC3CO test for PSR2/PR modes

[Jeevan B]

Enable DC3CO with PSR2/PR mode on TGL and for platforms with
display version greater than 35.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/intel/kms_pm_dc.c | 34 +++++++++++++++++++++++++---------
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 507b6168d..10450474a 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -315,19 +315,19 @@ static void check_dc3co_with_videoplayback_like_load(data_t *data)
 	check_dc_counter(data, IGT_INTEL_CHECK_DC3CO, dc3co_prev_cnt);
 }
 
-static void setup_dc3co(data_t *data)
+static void setup_dc3co(data_t *data, enum psr_mode mode)
 {
-	data->op_psr_mode = PSR_MODE_2;
+	data->op_psr_mode = mode;
 	psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, NULL);
 	igt_require_f(psr_wait_entry(data->debugfs_fd, data->op_psr_mode, NULL),
-		      "PSR2 is not enabled\n");
+		      "PSR2/PR is not enabled\n");
 }
 
-static void test_dc3co_vpb_simulation(data_t *data)
+static void test_dc3co_vpb_simulation(data_t *data, enum psr_mode mode)
 {
 	igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
 	setup_output(data);
-	setup_dc3co(data);
+	setup_dc3co(data, mode);
 	setup_videoplayback(data);
 	check_dc3co_with_videoplayback_like_load(data);
 	cleanup_dc3co_fbs(data);
@@ -638,10 +638,26 @@ int igt_main()
 
 	igt_describe("In this test we make sure that system enters DC3CO "
 		     "when PSR2 is active and system is in SLEEP state");
-	igt_subtest("dc3co-vpb-simulation") {
-		igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
-					     PSR_MODE_2, NULL));
-		test_dc3co_vpb_simulation(&data);
+	igt_subtest_with_dynamic("dc3co-vpb-simulation") {
+		int modes[] = {PSR_MODE_2, PR_MODE};
+		const char *append_subtest_name[2] = {
+			"psr2-",
+			"pr-",
+		};
+
+		for (int i = 0; i < ARRAY_SIZE(modes); i++) {
+			igt_dynamic_f("%s-dc3co-basic", append_subtest_name[i]) {
+				igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+							     modes[i], NULL));
+
+				if (modes[i] == PSR_MODE_2)
+					igt_require(IS_TIGERLAKE(data.devid) ||
+						    intel_display_ver(data.devid) >= 35);
+				else if (modes[i] == PR_MODE)
+					igt_require(intel_display_ver(data.devid) >= 35);
+				test_dc3co_vpb_simulation(&data, modes[i]);
+			}
+		}
 	}
 
 	igt_describe("This test validates display engine entry to DC5 state "
-- 
2.43.0

[PATCH i-g-t 3/4] tests/kms_vrr: Add new test for DC3CO validation with LOBF

[Jeevan B]

Add lobf-dc3co subtest to validate DC3CO entry during link-off
between frames.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_vrr.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c
index 569000fee..1f2b4ada8 100644
--- a/tests/kms_vrr.c
+++ b/tests/kms_vrr.c
@@ -29,6 +29,7 @@
  */
 
 #include "igt.h"
+#include "igt_pm.h"
 #include "igt_psr.h"
 #include "i915/intel_drrs.h"
 #include "sw_sync.h"
@@ -942,6 +943,25 @@ test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
 	igt_assert_f(lobf_enabled, "LOBF not enabled\n");
 }
 
+static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc,
+			    igt_output_t *output, uint32_t flags)
+{
+	unsigned long dc3co_count_before, dc3co_count_after;
+
+	dc3co_count_before = igt_read_dc_counter(data->debugfs_fd,
+						 IGT_INTEL_CHECK_DC3CO);
+
+	test_lobf(data, crtc, output, flags);
+
+	dc3co_count_after = igt_read_dc_counter(data->debugfs_fd,
+						IGT_INTEL_CHECK_DC3CO);
+
+	igt_assert_f(dc3co_count_after > dc3co_count_before,
+		     "DC3CO should be entered during link-off periods. "
+		     "Before: %lu, After: %lu\n",
+		     dc3co_count_before, dc3co_count_after);
+}
+
 static void
 test_cmrr(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
 	  uint32_t flags)
@@ -1237,6 +1257,16 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data)
 
 			run_vrr_test(&data, test_lobf, TEST_LINK_OFF);
 		}
+
+		igt_describe("Test to validate DC3CO entry during link-off between active "
+			     "frames in non-PSR operation non-PSR operation.");
+		igt_subtest_with_dynamic("lobf-dc3co") {
+			igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35);
+
+			igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+
+			run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF | IGT_INTEL_CHECK_DC3CO);
+		}
 	}
 
 	igt_fixture() {
-- 
2.43.0

[PATCH i-g-t 4/4] tests/intel/kms_pm_dc: Add new test for dc3co framedrop validation

[Jeevan B]

Add a new subtest to validate that no frame drops occur during
DC3CO entry, ensuring that no frame drops are detected and DC3CO
is successfully triggered during the test.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/intel/kms_pm_dc.c | 83 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 10450474a..b0e35dca1 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -51,6 +51,10 @@
  * Description: Make sure that system enters DC3CO when PSR2 is active and system
  *              is in SLEEP state
  *
+ * SUBTEST: dc3co-framedrop-check
+ * Description: Verify that DC3CO entry does not cause frame drops and successfully
+ * 		enters the power state
+ *
  * SUBTEST: dc5-dpms
  * Description: Validate display engine entry to DC5 state while all connectors's
  *              DPMS property set to OFF
@@ -315,6 +319,50 @@ static void check_dc3co_with_videoplayback_like_load(data_t *data)
 	check_dc_counter(data, IGT_INTEL_CHECK_DC3CO, dc3co_prev_cnt);
 }
 
+static void check_framedrop(data_t *data)
+{
+	igt_plane_t *primary;
+	uint32_t dc3co_prev_cnt, dc3co_cnt;
+	int delay, frame_count, max_count = 100, ret;
+	bool dc3co_flag = false;
+	drmVBlank wait;
+
+	primary = igt_output_get_plane_type(data->output,
+					    DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	dc3co_prev_cnt = igt_read_dc_counter(data->debugfs_fd,
+					     IGT_INTEL_CHECK_DC3CO);
+
+	/* Calculate delay to generate idle frame in usec*/
+	delay = 1.5 * ((1000 * 1000) / data->mode->vrefresh);
+
+	for (int i = 0; i < max_count; i++) {
+		if (i % 2 == 0)
+			igt_plane_set_fb(primary, &data->fb_rgb);
+		else
+			igt_plane_set_fb(primary, &data->fb_rgr);
+
+		igt_display_commit(&data->display);
+		frame_count++;
+
+		memset(&wait, 0, sizeof(wait));
+		wait.request.type = DRM_VBLANK_RELATIVE;
+		wait.request.sequence = 1;
+
+		ret = drmWaitVBlank(data->drm_fd, &wait);
+		igt_assert_eq(ret, 0);
+		dc3co_cnt = igt_read_dc_counter(data->debugfs_fd,
+						IGT_INTEL_CHECK_DC3CO);
+		if (dc3co_cnt > dc3co_prev_cnt)
+			dc3co_flag = true;
+
+		usleep(delay);
+	}
+
+	igt_assert_f(dc3co_flag, "DC3CO entry failed.\n");
+	igt_assert_f(frame_count == max_count, "Framedrop seen during vpb scenario.\n");
+}
+
 static void setup_dc3co(data_t *data, enum psr_mode mode)
 {
 	data->op_psr_mode = mode;
@@ -333,6 +381,16 @@ static void test_dc3co_vpb_simulation(data_t *data, enum psr_mode mode)
 	cleanup_dc3co_fbs(data);
 }
 
+static void test_framedrop_dc3co(data_t *data, enum psr_mode mode)
+{
+	igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+	setup_output(data);
+	setup_dc3co(data, mode);
+	setup_videoplayback(data);
+	check_framedrop(data);
+	cleanup_dc3co_fbs(data);
+}
+
 static void test_dc5_retention_flops(data_t *data, int dc_flag)
 {
 	uint32_t dc_counter_before_psr;
@@ -660,6 +718,31 @@ int igt_main()
 		}
 	}
 
+	igt_describe("Verify that DC3CO entry does not cause frame drops "
+		     "and successfully enters the power state");
+	igt_subtest_with_dynamic("dc3co-framedrop-check") {
+		int modes[] = {PSR_MODE_2, PR_MODE};
+		const char *append_subtest_name[2] = {
+			"psr2-",
+			"pr-",
+		};
+
+		for (int i = 0; i < ARRAY_SIZE(modes); i++) {
+			igt_dynamic_f("%s-dc3co-framedrop", append_subtest_name[i]) {
+				igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+							     modes[i], NULL));
+
+				if (modes[i] == PSR_MODE_2)
+					igt_require(IS_TIGERLAKE(data.devid) ||
+						    intel_display_ver(data.devid) >= 35);
+				else if (modes[i] == PR_MODE)
+					igt_require(intel_display_ver(data.devid) >= 35);
+
+				test_framedrop_dc3co(&data, modes[i]);
+			}
+		}
+	}
+
 	igt_describe("This test validates display engine entry to DC5 state "
 		     "while PSR is active");
 	igt_subtest("dc5-psr") {
-- 
2.43.0

[PATCH i-g-t 3/4] tests/kms_vrr: Add new test for DC3CO validation with LOBF

[Jeevan B]

Add lobf-dc3co subtest to validate DC3CO entry during link-off
between frames.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
 tests/kms_vrr.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c
index 569000fee..f8b830cc0 100644
--- a/tests/kms_vrr.c
+++ b/tests/kms_vrr.c
@@ -29,6 +29,7 @@
  */
 
 #include "igt.h"
+#include "igt_pm.h"
 #include "igt_psr.h"
 #include "i915/intel_drrs.h"
 #include "sw_sync.h"
@@ -80,6 +81,9 @@
  *
  * SUBTEST: negative-basic
  * Description: Make sure that VRR should not be enabled on the Non-VRR panel.
+ *
+ * SUBTEST: lobf-dc3co
+ * Description: Test DC3CO entry during LOBF.
  */
 
 #define NSECS_PER_SEC (1000000000ull)
@@ -942,6 +946,25 @@ test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
 	igt_assert_f(lobf_enabled, "LOBF not enabled\n");
 }
 
+static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc,
+			    igt_output_t *output, uint32_t flags)
+{
+	unsigned long dc3co_count_before, dc3co_count_after;
+
+	dc3co_count_before = igt_read_dc_counter(data->debugfs_fd,
+						 IGT_INTEL_CHECK_DC3CO);
+
+	test_lobf(data, crtc, output, flags);
+
+	dc3co_count_after = igt_read_dc_counter(data->debugfs_fd,
+						IGT_INTEL_CHECK_DC3CO);
+
+	igt_assert_f(dc3co_count_after > dc3co_count_before,
+		     "DC3CO should be entered during link-off periods. "
+		     "Before: %lu, After: %lu\n",
+		     dc3co_count_before, dc3co_count_after);
+}
+
 static void
 test_cmrr(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
 	  uint32_t flags)
@@ -1237,6 +1260,16 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data)
 
 			run_vrr_test(&data, test_lobf, TEST_LINK_OFF);
 		}
+
+		igt_describe("Test to validate DC3CO entry during link-off between active "
+			     "frames in non-PSR operation non-PSR operation.");
+		igt_subtest_with_dynamic("lobf-dc3co") {
+			igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35);
+
+			igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+
+			run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF | IGT_INTEL_CHECK_DC3CO);
+		}
 	}
 
 	igt_fixture() {
-- 
2.43.0

Re: [PATCH i-g-t 3/4] tests/kms_vrr: Add new test for DC3CO validation with LOBF

[Thasleem, Mohammed]

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On 04-03-2026 10:08 am, Jeevan B wrote:
> Add lobf-dc3co subtest to validate DC3CO entry during link-off
> between frames.
>
> Signed-off-by: Jeevan B<jeevan.b@intel.com>
> ---
>   tests/kms_vrr.c | 33 +++++++++++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
>
> diff --git a/tests/kms_vrr.c b/tests/kms_vrr.c
> index 569000fee..f8b830cc0 100644
> --- a/tests/kms_vrr.c
> +++ b/tests/kms_vrr.c
> @@ -29,6 +29,7 @@
>    */
>   
>   #include "igt.h"
> +#include "igt_pm.h"
>   #include "igt_psr.h"
>   #include "i915/intel_drrs.h"
>   #include "sw_sync.h" @@ -80,6 +81,9 @@ * * SUBTEST: negative-basic * Description: Make 
> sure that VRR should not be enabled on the Non-VRR panel. + * + * 
> SUBTEST: lobf-dc3co + * Description: Test DC3CO entry during LOBF. */ 
> #define NSECS_PER_SEC (1000000000ull) @@ -942,6 +946,25 @@ 
> test_lobf(data_t *data, igt_crtc_t *crtc, igt_output_t *output, 
> igt_assert_f(lobf_enabled, "LOBF not enabled\n");
>   }
>   
> +static void test_lobf_dc3co(data_t *data, igt_crtc_t *crtc,
> +			    igt_output_t *output, uint32_t flags)
> +{
> +	unsigned long dc3co_count_before, dc3co_count_after;
> +
> +	dc3co_count_before = igt_read_dc_counter(data->debugfs_fd,
> +						 IGT_INTEL_CHECK_DC3CO);
> +
> +	test_lobf(data, crtc, output, flags);
> +
> +	dc3co_count_after = igt_read_dc_counter(data->debugfs_fd,
> +						IGT_INTEL_CHECK_DC3CO);
> +
> +	igt_assert_f(dc3co_count_after > dc3co_count_before,
> +		     "DC3CO should be entered during link-off periods. "
> +		     "Before: %lu, After: %lu\n",
> +		     dc3co_count_before, dc3co_count_after);
> +}
> +
>   static void
>   test_cmrr(data_t *data, igt_crtc_t *crtc, igt_output_t *output,
>   	  uint32_t flags)
> @@ -1237,6 +1260,16 @@ int igt_main_args("drs:", long_opts, help_str, opt_handler, &data)
>   
>   			run_vrr_test(&data, test_lobf, TEST_LINK_OFF);
>   		}
> +
> +		igt_describe("Test to validate DC3CO entry during link-off between active "
> +			     "frames in non-PSR operation non-PSR operation.");
-->remove copy paste error in discription--> "non-PSR operation non-PSR 
operation" with "non-PSR operation"
> +		igt_subtest_with_dynamic("lobf-dc3co") {
> +			igt_require(intel_display_ver(intel_get_drm_devid(data.drm_fd)) >= 35);
> +
> +			igt_require_dc_counter(data.debugfs_fd, IGT_INTEL_CHECK_DC3CO);
> +
> +			run_vrr_test(&data, test_lobf_dc3co, TEST_LINK_OFF | IGT_INTEL_CHECK_DC3CO);
--> IGT_INTEL_CHECK_DC3CO is dc counter check type but not a test flag 
this might be conflit with other test flag bits. define a dedicated test 
flag. i think better use TEST_LINK_OFF instead mixing, you have already 
checked DC3CO inside ur test.

-->https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/tests/kms_vrr.c?ref_type=heads#L906 

|if(flags & TEST_LINK_OFF) at vrr.c might not execute with ur current 
approach?

-->https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/blob/master/tests/kms_vrr.c?ref_type=heads#L946
    is it expected to assert the test if lobf is not enabled?|
> +		}
>   	}
>   
>   	igt_fixture() {

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