[PATCH 2/2] tests/intel/xe_eudebug_online: Assert fsync return on debugger VM fd

[Jan Maslak <jan.maslak@intel.com>]

fsync() on a debugger VM fd triggers GPU cache invalidation, ensuring
that pwrite() and pread() operations observe a consistent memory state.
All call sites were silently ignoring the return value, allowing cache
flush failures to go undetected.

Wrap all fsync() calls with igt_assert_eq() so that a failure causes
an immediate abort.

Signed-off-by: Jan Maslak <jan.maslak@intel.com>
Reviewed-by: Maciej Patelczyk <maciej.patelczyk@intel.com>
---
 tests/intel/xe_eudebug_online.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_online.c
index 1af887bba..8d3bc644f 100644
--- a/tests/intel/xe_eudebug_online.c
+++ b/tests/intel/xe_eudebug_online.c
@@ -621,7 +621,7 @@ static bool set_breakpoint_once(struct xe_eudebug_debugger *d,
 		instr_usdw |= breakpoint_bit;
 		igt_assert_eq(pwrite(data->vm_fd, &instr_usdw, sz,
 				     data->bb_offset + aip), sz);
-		fsync(data->vm_fd);
+		igt_assert_eq(fsync(data->vm_fd), 0);
 
 		breakpoint_set = true;
 	}
@@ -648,7 +648,7 @@ static void get_aips_offset_table(struct online_debug_data *data, int threads)
 	data->first_aip = first_aip;
 	data->aips_offset_table[table_index++] = 0;
 
-	fsync(data->vm_fd);
+	igt_assert_eq(fsync(data->vm_fd), 0);
 	for (int i = sz; i < data->target_size; i += sz) {
 		igt_assert_eq(pread(data->vm_fd, &aip, sz, data->target_offset + i), sz);
 		if (aip == first_aip)
@@ -668,7 +668,7 @@ static int get_stepped_threads_count(struct online_debug_data *data, int threads
 	size_t sz = sizeof(uint32_t);
 	uint32_t aip;
 
-	fsync(data->vm_fd);
+	igt_assert_eq(fsync(data->vm_fd), 0);
 	for (int i = 0; i < threads; i++) {
 		igt_assert_eq(pread(data->vm_fd, &aip, sz,
 				    data->target_offset + data->aips_offset_table[i]), sz);
@@ -762,7 +762,7 @@ static void eu_attention_resume_trigger(struct xe_eudebug_debugger *d,
 		igt_assert_eq(pwrite(data->vm_fd, &val, sizeof(uint32_t),
 				     data->target_offset + steering_offset(threads)),
 			      sizeof(uint32_t));
-		fsync(data->vm_fd);
+		igt_assert_eq(fsync(data->vm_fd), 0);
 	}
 	pthread_mutex_unlock(&data->mutex);
 
@@ -857,7 +857,7 @@ static void eu_attention_resume_single_step_trigger(struct xe_eudebug_debugger *
 
 	igt_assert_eq(pwrite(data->vm_fd, &val, sz,
 			     data->target_offset + steering_offset(threads)), sz);
-	fsync(data->vm_fd);
+	igt_assert_eq(fsync(data->vm_fd), 0);
 
 	data->last_eu_control_seqno = eu_ctl_resume(d->master_fd, d->fd, att->client_handle,
 						    att->exec_queue_handle, att->lrc_handle,
@@ -988,7 +988,7 @@ static void overwrite_immediate_value_in_common_target_write(int vm_fd, uint64_t
 			igt_assert_eq(pread(vm_fd, &val, sizeof(uint32_t), addr),
 				      sizeof(uint32_t));
 			igt_debug("val_before_fsync[%d]: %08x\n", vals_changed, val);
-			fsync(vm_fd);
+			igt_assert_eq(fsync(vm_fd), 0);
 			igt_assert_eq(pread(vm_fd, &val, sizeof(uint32_t), addr),
 				      sizeof(uint32_t));
 			igt_debug("val_after_fsync[%d]: %08x\n", vals_changed, val);
@@ -1043,7 +1043,7 @@ static void eu_attention_resume_caching_trigger(struct xe_eudebug_debugger *d,
 				     data->bb_offset + *kernel_offset + shader_preamble->size * 4 +
 				     shader_write_instr->size * 4 * *counter),
 				     sizeof(instr_usdw));
-		fsync(data->vm_fd);
+		igt_assert_eq(fsync(data->vm_fd), 0);
 	}
 
 	/* restore current instruction */
-- 
2.34.1