From: nishit.sharma@intel.com
To: igt-dev@lists.freedesktop.org, thomas.hellstrom@intel.com
Subject: [PATCH i-g-t 2/2] tests/intel/xe_svm_usrptr_madvise: Unify batch buffer alignment
Date: Wed, 11 Mar 2026 17:03:54 +0000 [thread overview]
Message-ID: <20260311170354.475828-3-nishit.sharma@intel.com> (raw)
In-Reply-To: <20260311170354.475828-1-nishit.sharma@intel.com>
From: Nishit Sharma <nishit.sharma@intel.com>
This patch refactors the SVM userptr copy test and batch buffer setup
to use aligned buffer mapping for batch buffers, ensuring compatibility
across both Ponte Vecchio (PVC) and BMG platforms.
Batch buffer mapping now uses platform-required alignment, eliminating
the need for platform-specific address assignment and conditional code
paths.
Signed-off-by: Nishit Sharma <nishit.sharma@intel.com>
---
tests/intel/xe_svm_usrptr_madvise.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/tests/intel/xe_svm_usrptr_madvise.c b/tests/intel/xe_svm_usrptr_madvise.c
index bfa5864e4..db7b9ee35 100644
--- a/tests/intel/xe_svm_usrptr_madvise.c
+++ b/tests/intel/xe_svm_usrptr_madvise.c
@@ -98,7 +98,8 @@ gpu_batch_init(int fd, uint32_t vm, uint64_t src_addr,
{
uint32_t width = copy_size / 256;
uint32_t height = 1;
- uint32_t batch_bo_size = BATCH_SIZE(fd);
+ uint64_t alignment = xe_get_default_alignment(fd);
+ uint32_t batch_bo_size = ALIGN(BATCH_SIZE(fd), alignment);
uint32_t batch_bo;
uint64_t batch_addr;
void *batch;
@@ -108,7 +109,7 @@ gpu_batch_init(int fd, uint32_t vm, uint64_t src_addr,
int i = 0;
batch_bo = xe_bo_create(fd, vm, batch_bo_size, vram_if_possible(fd, 0), 0);
- batch = xe_bo_map(fd, batch_bo, batch_bo_size);
+ batch = xe_bo_map_aligned(fd, batch_bo, batch_bo_size, alignment);
cmd = (uint32_t *)batch;
cmd[i++] = MEM_COPY_CMD | (1 << 19);
cmd[i++] = width - 1;
@@ -140,7 +141,7 @@ gpu_copy_batch_create(int fd, uint32_t vm, uint32_t exec_queue,
uint64_t src_addr, uint64_t dst_addr,
uint32_t *batch_bo, uint64_t *batch_addr)
{
- gpu_batch_init(fd, vm, src_addr, dst_addr, SZ_4K, batch_bo, batch_addr);
+ gpu_batch_init(fd, vm, src_addr, dst_addr, SZ_16K, batch_bo, batch_addr);
}
static void
@@ -209,10 +210,10 @@ static void test_svm_userptr_copy(int fd)
&batch_bo, &batch_addr);
gpu_exec_sync(fd, vm, exec_queue, &batch_addr);
- igt_assert(memcmp(svm_ptr, userptr_ptr, SZ_4K) == 0);
+ igt_assert(memcmp(svm_ptr, userptr_ptr, 64) == 0);
bo_map = xe_bo_map(fd, bo, size);
- igt_assert(memcmp(bo_map, svm_ptr, SZ_4K) == 0);
+ igt_assert(memcmp(bo_map, svm_ptr, 64) == 0);
xe_vm_bind_lr_sync(fd, vm, 0, 0, batch_addr, BATCH_SIZE(fd),
DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR);
--
2.34.1
next prev parent reply other threads:[~2026-03-11 17:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-11 17:03 [PATCH i-g-t 0/2] Unify Batch Buffer Alignment and Introduce Aligned Buffer Mapping nishit.sharma
2026-03-11 17:03 ` [PATCH i-g-t 1/2] lib/xe: Introduce aligned buffer mapping nishit.sharma
2026-03-11 18:53 ` Hellstrom, Thomas
2026-03-11 17:03 ` nishit.sharma [this message]
2026-03-11 18:54 ` [PATCH i-g-t 2/2] tests/intel/xe_svm_usrptr_madvise: Unify batch buffer alignment Hellstrom, Thomas
2026-03-12 1:39 ` ✓ Xe.CI.BAT: success for Unify Batch Buffer Alignment and Introduce Aligned Buffer Mapping Patchwork
2026-03-12 1:48 ` ✓ i915.CI.BAT: " Patchwork
2026-03-12 21:03 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-12 21:45 ` ✓ i915.CI.Full: success " Patchwork
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