From: Aditya Chauhan <aditya.chauhan@intel.com>
To: ramadevi.gandi@intel.com, himanshu.girotra@intel.com,
swati2.sharma@intel.com, kamil.konieczny@intel.com,
igt-dev@lists.freedesktop.org
Subject: [PATCH v3 i-g-t 1/2] intel-ci: Add NVL core blocklist
Date: Thu, 12 Mar 2026 15:52:00 +0530 [thread overview]
Message-ID: <20260312102201.53909-2-aditya.chauhan@intel.com> (raw)
In-Reply-To: <20260312102201.53909-1-aditya.chauhan@intel.com>
Introduce core blocklist for the NVL platform containing
NVL-specific core test exclusions. Also add this blocklist file
to meson.build so that this can be used in execution.
v2: Make commit message more descriptive (Swati Sharma)
V3: Make comments more descriptive for blocklisted tests,
use correct subject(intel-ci) and add blocklist in alphabetical
order in meson.build(Swati Sharma)
Signed-off-by: Aditya Chauhan <aditya.chauhan@intel.com>
---
tests/intel-ci/meson.build | 1 +
tests/intel-ci/xe.nvl.core.blocklist.txt | 69 ++++++++++++++++++++++++
2 files changed, 70 insertions(+)
create mode 100644 tests/intel-ci/xe.nvl.core.blocklist.txt
diff --git a/tests/intel-ci/meson.build b/tests/intel-ci/meson.build
index cf0023c63..3c7fa28b7 100644
--- a/tests/intel-ci/meson.build
+++ b/tests/intel-ci/meson.build
@@ -23,6 +23,7 @@ intelci_files = [
'xe.lnl.display.blocklist.txt',
'xe.lnl.eudebug.blocklist.txt',
'xe.multigpu.blocklist.txt',
+ 'xe.nvl.core.blocklist.txt',
'xe.ptl.core.blocklist.txt',
'xe.ptl.display.blocklist.txt',
'xe.sriov-vf.blocklist.txt',
diff --git a/tests/intel-ci/xe.nvl.core.blocklist.txt b/tests/intel-ci/xe.nvl.core.blocklist.txt
new file mode 100644
index 000000000..aee1edd15
--- /dev/null
+++ b/tests/intel-ci/xe.nvl.core.blocklist.txt
@@ -0,0 +1,69 @@
+##################################################################
+# Valid Skip: Tests NA for Native
+##################################################################
+igt@.*iov.*
+##################################################################
+# KMS - Display related tests
+# Other Display specific tests
+##################################################################
+igt@.*kms.*
+igt@testdisplay
+igt@xe_pat@display-vs-wb-transient
+igt@fbdev@.*
+##################################################################
+# Valid skip: Integrated GPU has no vram
+##################################################################
+igt@xe_mmap@vram$
+igt@xe_mmap@small-bar
+igt@xe_noexec_ping_pong
+igt@xe_create@create-big-vram
+igt@xe_evict.*
+igt@xe_pm@d3hot-mmap-vram
+igt@xe_eudebug_online@writes-caching-(?!sram-bb-sram-target-sram).*
+igt@xe_compute_preempt@.*vram.*
+igt@xe_vm@out-of-memory
+##################################################################
+# Valid skip: Tests are expected to run
+# only on older platforms
+##################################################################
+igt@xe_pat@pat-index-xe3p-xpc
+igt@xe_pat@pat-index-xehpc
+igt@xe_pat@pat-index-xelp
+igt@xe_pat@pat-index-xelpg
+igt@xe_media_fill@media-fill
+igt@xe_pat@pat-index-xe2
+##################################################################
+# Valid skip: Tests need more than one CCS engine
+# which is not the case with NVL
+##################################################################
+igt@xe_compute@ccs-mode-basic
+igt@xe_compute@ccs-mode-compute-kernel
+igt@xe_compute@eu-busy-10s
+##################################################################
+# Valid skip: Not supported on NVL
+##################################################################
+igt@xe_huc_copy@huc_copy
+igt@xe_exec_balancer@.*
+igt@.*@.*tiles
+igt@xe_oa@oa-tlb-invalidate
+igt@xe_pxp@.*
+igt@xe_exec_system_allocator@.*
+##################################################################
+# Valid skip: Not Applicable for integrated platforms
+##################################################################
+igt@intel_hwmon@.*
+igt@.*@.*multigpu.*
+igt@xe_peer2peer@.*
+igt@xe_mmap@pci-membarrier.*
+igt@xe_pm@d3hot-i2c
+igt@xe_configfs@survivability-mode
+igt@xe_survivability@.*
+##################################################################
+# Valid skip: Kernel support not available yet
+##################################################################
+igt@xe_eudebug@.*
+igt@xe_eudebug_online@.*
+igt@xe_exec_sip@.*
+igt@xe_exec_sip_eudebug@.*
+igt@xe_live_ktest@xe_eudebug
+##################################################################
\ No newline at end of file
--
2.34.1
next prev parent reply other threads:[~2026-03-12 10:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-12 10:21 [PATCH v3 i-g-t 0/2] intel-ci: Add NVL display and core blocklists Aditya Chauhan
2026-03-12 10:22 ` Aditya Chauhan [this message]
2026-03-12 10:22 ` [PATCH v3 i-g-t 2/2] intel-ci: Add NVL Display blocklist to meson.build Aditya Chauhan
2026-03-12 12:58 ` Kamil Konieczny
2026-03-12 17:29 ` ✓ Xe.CI.BAT: success for intel-ci: Add NVL display and core blocklists Patchwork
2026-03-12 17:35 ` ✓ i915.CI.BAT: " Patchwork
2026-03-13 17:40 ` ✗ i915.CI.Full: failure " Patchwork
2026-03-13 18:21 ` ✗ Xe.CI.FULL: " Patchwork
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