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d="scan'208";a="246301756" Received: from nakshtra-system-product-name.iind.intel.com ([10.190.238.69]) by fmviesa002.fm.intel.com with ESMTP; 20 Mar 2026 05:29:27 -0700 From: nakshtra.goyal@intel.com To: igt-dev@lists.freedesktop.org Cc: tejas.upadhyay@intel.com, priyanka.dandamudi@intel.com Subject: [PATCH v2 i-g-t] tests/intel/xe_pat: Add negetive test to validate pat index Date: Fri, 20 Mar 2026 17:59:26 +0530 Message-Id: <20260320122926.1614740-1-nakshtra.goyal@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" From: Nakshtra Goyal Adding negative test to validate pat index restrictions, extending tests in userptr_coh_none and prime_export for index 18 and adding new svm test to validate for diff indexes , index 19 will pass in all cases , 18 will fail with EINVAL v2: Adding validation checks directly inside subtest call instead of different functions (Priyanka) Signed-off-by: Nakshtra Goyal --- tests/intel/xe_pat.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c index e91b037a5..6f107f345 100644 --- a/tests/intel/xe_pat.c +++ b/tests/intel/xe_pat.c @@ -34,6 +34,11 @@ #define XE_COH_NONE 1 #define XE_COH_AT_LEAST_1WAY 2 +/* + * PAT index 18: XA (eXclusive Access) + UC (Uncached). + */ +#define XE_PAT_IDX_XA_UC 18 + static bool do_slow_check; static char bus_addr[NAME_MAX]; static struct pci_device *pci_dev; @@ -82,6 +87,10 @@ static void userptr_coh_none(int fd) size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0, intel_get_pat_idx_wt(fd), 0), -EINVAL); + igt_assert_eq(__xe_vm_bind(fd, vm, 0, 0, to_user_pointer(data), 0x40000, + size, DRM_XE_VM_BIND_OP_MAP_USERPTR, 0, NULL, 0, 0, + XE_PAT_IDX_XA_UC, 0), + -EINVAL); munmap(data, size); xe_vm_destroy(fd, vm); @@ -755,6 +764,54 @@ static void pat_index_dw(struct xe_pat_param *p) xe_vm_destroy(fd, vm); } +/** + * SUBTEST: l2-flush-opt-svm-pat-restrict + * Test category: negative test + * Description: Validate that on L2 flush optimized platforms, SVM + * (CPU_ADDR_MIRROR) mappings only accept pat_index 19 + * (XA+2WAY) and reject all other pat indices with -EINVAL. + */ +static void l2_flush_opt_svm_pat_restrict(int fd) +{ + struct drm_xe_query_config *config = xe_config(fd); + uint32_t vm; + void *buffer; + size_t alloc_size = xe_get_default_alignment(fd); + struct xe_device *xe_dev = xe_device_get(fd); + uint64_t svm_size; + size_t size = xe_get_default_alignment(fd); + + svm_size = 1ull << xe_dev->va_bits; + vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE | + DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0); + xe_vm_bind_lr_sync(fd, vm, 0, 0, 0, svm_size, + DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR); + buffer = aligned_alloc(alloc_size, SZ_2M); + + igt_require(config->info[DRM_XE_QUERY_CONFIG_FLAGS] & + DRM_XE_QUERY_CONFIG_FLAG_HAS_CPU_ADDR_MIRROR); + + igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size, + 0, DRM_XE_MEM_RANGE_ATTR_PAT, + intel_get_pat_idx_wb(fd), 0, 0), 0); + + igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size, + 0, DRM_XE_MEM_RANGE_ATTR_PAT, + intel_get_pat_idx_uc(fd), 0, 0), -EINVAL); + + igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size, + 0, DRM_XE_MEM_RANGE_ATTR_PAT, + intel_get_pat_idx_wt(fd), 0, 0), -EINVAL); + + igt_assert_eq(__xe_vm_madvise(fd, vm, to_user_pointer(buffer), size, + 0, DRM_XE_MEM_RANGE_ATTR_PAT, + XE_PAT_IDX_XA_UC, 0, 0), -EINVAL); + + free(buffer); + xe_vm_unbind_lr_sync(fd, vm, 0, 0, svm_size); + xe_vm_destroy(fd, vm); +} + /** * SUBTEST: prime-self-import-coh * Test category: functionality test @@ -890,6 +947,11 @@ static void prime_external_import_coh(void) 0); xe_vm_unbind_sync(fd2, vm, 0, 0x40000, size); + igt_assert_eq(__xe_vm_bind(fd2, vm, 0, handle_import, 0, 0x40000, + size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0, + XE_PAT_IDX_XA_UC, 0), + -EINVAL); + xe_vm_destroy(fd2, vm); /* @@ -1771,6 +1833,11 @@ int igt_main_args("V", NULL, help_str, opt_handler, NULL) } } + igt_subtest("l2-flush-opt-svm-pat-restrict") { + igt_require(intel_graphics_ver(dev_id) == IP_VER(35, 10)); + l2_flush_opt_svm_pat_restrict(fd); + } + igt_fixture() drm_close_driver(fd); } -- 2.34.1