From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB114FF60F4 for ; Tue, 31 Mar 2026 17:13:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7838710EC8E; Tue, 31 Mar 2026 17:13:06 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=bootlin.com header.i=@bootlin.com header.b="UCuS4Gm2"; dkim-atps=neutral Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0C5A110EC39 for ; Tue, 31 Mar 2026 17:11:07 +0000 (UTC) Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id F40D01A30B3 for ; Tue, 31 Mar 2026 17:11:05 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CA62C6029D; Tue, 31 Mar 2026 17:11:05 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B48031045059C; Tue, 31 Mar 2026 19:11:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1774977065; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=FxffI9EjMYd18D+0pJ6hRbDCqgXzLmDSYkMhts5quME=; b=UCuS4Gm2Txu72G2r9v3JPEpLUvl5qRAq6Rx0h6ZLZ9Uluo8/vf8FNdXuVHeyhzyTr0KoD4 C0wuh4qv6Tzf2leqBL92bwWcfHAdp2hurYxizZot8eiSNHJU16vnv+8yvnypv8xkklYAK0 Mo639ST/4gxPe+8CVP7PWj81Tc89MYW/M8ESvQqJV33PWeIBSth5FMdmHOvCVTAvLn2J8B WmPZ6ZrjtWVhNWUWUxMAsBgqYOVJECqVX1TMAd/9r+AgJnRHXPVoU7TEmhy10z2NBUdv3p xXVp8zVdN80nobHCDid4o3INYx2PFnBTN0mynxhldmb7ci69Wo5R+qVXvo3ETg== From: Louis Chauvet Date: Tue, 31 Mar 2026 19:11:35 +0200 Subject: [PATCH i-g-t v10 18/49] lib/unigraf: Add used defines for TSI_Types MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260331-unigraf-integration-v10-18-12266c34cc1d@bootlin.com> References: <20260331-unigraf-integration-v10-0-12266c34cc1d@bootlin.com> In-Reply-To: <20260331-unigraf-integration-v10-0-12266c34cc1d@bootlin.com> To: igt-dev@lists.freedesktop.org Cc: thomas.petazzoni@bootlin.com, luca.ceresoli@bootlin.com, kory.maincent@bootlin.com, markyacoub@google.com, khaled.almahallawy@intel.com, Louis Chauvet X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6085; i=louis.chauvet@bootlin.com; h=from:subject:message-id; bh=8KuUT7vU5w/32PDwWXHaKT3BILIzo/kBonWZO5r0BPs=; b=owEBiQJ2/ZANAwAIASCtLsZbECziAcsmYgBpzAA97J0aFhaaq0OP2HFzDK03yS8NvQq72dH0g xBDtV8PCj+JAk8EAAEIADkWIQRPj7g/vng8MQxQWQQgrS7GWxAs4gUCacwAPRsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDIACgkQIK0uxlsQLOLmZhAA06FT0d/mzELRmdG7tOIsL9K6uZMNhcU TU/vmRTMiViZ5IFmXJezyVKdqmeWGJsU1pNzFnO0AWHwK/OPjjp1Nr8s0fXtjoZ+G36bwybaP8P Lx4uUYfvRsVb36dHHLqIbisfipP9UARljVnsmVgE846HVXP0na8DhaB6NtyRRzmLvi+FAeT/nkU pehahHKTFJIGq1yPcmpGLz7MzIcXsE6yx2ZI3Zzrio8broe/Am6IJTXFRTjcfBaJC179HDGpWCx CgQhq/8HEolDm0OZItqPp9m2M/sMnH+B2eGLF10jabMkPhiy+4PHzibq6xS07tKj0KTwfmtgIo1 OSDHbTsoicEWZs7zt/D5UcLWIavcfoED1OHtFNEArKYAE6VGdf4P3IawRlmmnNxLj0MuSHh6bdv 27KJRI1B2k6kEXc4teuTESTrQzQgHu+F+wOyUfjowTbxAE3GITDh8Q5AUWDzt7qnEOTo0soOrBG Sghzhz28dn4fwTV1QQvBCpwgQcsF3mKUp+AZa8ek6zGcraIavJ08YyOoCeZhsBo5hBALqrqNgrx wwqnBK5LWfxkD/pFMRLQmN8dfK/Mu1IiyosUN2koHIEMKKnTw4Z6zE2NLFAbj5uOP1hoIWNASQm hSZBeCOmo4m617+DGRns1OoTagcXj0BO7xCKnJ58V/K6vSYdNM2w= X-Developer-Key: i=louis.chauvet@bootlin.com; a=openpgp; fpr=8B7104AE9A272D6693F527F2EC1883F55E0B40A5 X-Last-TLS-Session-Version: TLSv1.3 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Current unigraf public release are not c-compatible, this file hardcode some values. One future release of libTSI may include a c-compatible TSI_types.h file with full structure definition, but until then. Reviewed-by: Kory Maincent Signed-off-by: Louis Chauvet --- lib/vendor/unigraf/TSI_types.h | 126 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/lib/vendor/unigraf/TSI_types.h b/lib/vendor/unigraf/TSI_types.h new file mode 100644 index 000000000000..c387ab4e1941 --- /dev/null +++ b/lib/vendor/unigraf/TSI_types.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: MIT */ + +// Current unigraf public release are not c-compatible, this file hardcode some values. +// The next release of libTSI should include a c-compatible TSI_types.h file, that will +// be directly used in place of this file. + +#ifndef TSI_REG_H + +#include +#include + +#define TSI_VERSION_TEXT 0x80000001 +#define TSI_DEVCAP_VIDEO_CAPTURE 0x00000001 +#define TSI_SEARCHOPTIONS_SHOW_DEVICES_IN_USE 0x00000001 + +#define TSI_EDID_TE_INPUT 0x1100 +#define TSI_EDID_SELECT_STREAM 0x1102 + +#define TSI_BASE_LEGACY_GENERIC(offset) (0x210 + (offset)) +#define TSI_FORCE_HOT_PLUG_STATE_W TSI_BASE_LEGACY_GENERIC(0x2) + +#define TSI_BASE_LEGACY_DPRX_MSA(offset) (0x260 + (offset)) +#define TSI_DPRX_MSA_COMMAND_W TSI_BASE_LEGACY_DPRX_MSA(0x0) +#define TSI_DPRX_MSA_STREAM_COUNT_R TSI_BASE_LEGACY_DPRX_MSA(0x1) +#define TSI_DPRX_MSA_STREAM_SELECT TSI_BASE_LEGACY_DPRX_MSA(0x3) +#define TSI_DPRX_MSA_HTOTAL_R TSI_BASE_LEGACY_DPRX_MSA(0x6) +#define TSI_DPRX_MSA_VTOTAL_R TSI_BASE_LEGACY_DPRX_MSA(0x7) +#define TSI_DPRX_MSA_HACTIVE_R TSI_BASE_LEGACY_DPRX_MSA(0x8) +#define TSI_DPRX_MSA_VACTIVE_R TSI_BASE_LEGACY_DPRX_MSA(0x9) +#define TSI_DPRX_MSA_HSYNC_WIDTH_R TSI_BASE_LEGACY_DPRX_MSA(0xa) +#define TSI_DPRX_MSA_VSYNC_WIDTH_R TSI_BASE_LEGACY_DPRX_MSA(0xb) +#define TSI_DPRX_MSA_HSTART_R TSI_BASE_LEGACY_DPRX_MSA(0xc) +#define TSI_DPRX_MSA_VSTART_R TSI_BASE_LEGACY_DPRX_MSA(0xd) + +#define TSI_DPRX_LINK_FLAGS_MST 0x01 +#define TSI_DPRX_LINK_FLAGS_TPS3 0x02 +#define TSI_DPRX_LINK_FLAGS_TPS4 0x03 +#define TSI_DPRX_LINK_FLAGS_EDP 0x04 +#define TSI_DPRX_NOT_DOCUMENTED_DP_128_132_SUPPORTED 0x10 +#define TSI_DPRX_NOT_DOCUMENTED_SIDEBAND_MSG_SUPPORT 0x20 + +#define TSI_BASE_DPRX(offset) (0x50000000u + 0x21000 + (offset)) +#define TSI_DPRX_HW_CAPS_R TSI_BASE_DPRX(0x4) + +/** + * struct TSI_DPRX_HW_CAPS_R_s - Structure representing the hardware capabilities of the DP RX. + * + * This structure defines the bitfields and fields that describe the hardware + * capabilities of the DP RX (DisplayPort Receiver) interface. Each field + * corresponds to a specific capability or feature supported by the hardware. + * + * This structure is used to interpret the value read from the + * TSI_DPRX_HW_CAPS_R register. + * + * @mst: MST support + * @hdcp_1_x: HDCP 1.x support. + * @hdcp_2_x: HDCP 2.x support. + * @fec_8_10_b: FEC for 8/10 link support. + * @dsc_8_10_b: DSC for 8/10 link support. + * @three_lanes: Three lane link configuration support. + * @edp_link_rate: eDP link rates are supported. + * @mst_stream_count: Number of MST streams supported. + * @max_link_rate: Maximum link rate supported. The unit is not specified in documentation, + * it is probably like other config rate = 0.27GHz * value + * @force_link_config: Forced link configuration support. + * @power_provision: Power provision support on DP_PWR pin of receptacle connector. + * @aux_swing_voltage_control: AUX output voltage swing control support. + * @custom_dp_rate: Custom DP 2.0 rate support. + * @custom_bit_rate: Custom bit rate support. + * @fec_128_132_b: FEC for 128/132 link support. + * @dsc_128_132_b: DSC for 128/132 link support. + */ +struct TSI_DPRX_HW_CAPS_R_s { + bool mst:1; + bool hdcp_1_x:1; + bool hdcp_2_x:1; + bool fec_8_10_b:1; + bool dsc_8_10_b:1; + bool reserved_1:1; + bool three_lanes:1; + bool edp_link_rates_supported:1; + uint8_t mst_stream_count:3; + uint8_t reserved_2:5; + uint8_t max_link_rate; + bool force_link_config:1; + bool reserved_3:1; + bool power_provision:1; + bool aux_swing_voltage_control:1; + bool custom_dp_rate:1; + bool custom_bit_rate:1; + bool fec_128_132_b:1; + bool dsc_128_132_b:1; +}; + +#define TSI_DPRX_LT_LANE_COUNT_R TSI_BASE_DPRX(0x0B) +#define TSI_DPRX_LT_RATE_R TSI_BASE_DPRX(0x0C) +#define TSI_DPRX_HPD_FORCE TSI_BASE_DPRX(0x12) +#define TSI_DPRX_MST_SINK_COUNT TSI_BASE_DPRX(0x9D) + +#define TSI_BASE_DP_RX(offset) (0x00010100 + (offset)) +#define TSI_DP_RX_DUT_MAX_LANE_COUNT TSI_BASE_DP_RX(0xf) + +#define TSI_BASE_DP_LTT(offset) (0x00010700 + (offset)) +#define TSI_DP_LTT_MAX_LANE_COUNT TSI_BASE_DP_LTT(0x01) + +#define TSI_BASE_LEGACY_DPRX(offset) (0x2b0 + (offset)) +#define TSI_DPRX_DPCD_BASE_W TSI_BASE_LEGACY_DPRX(0x9) +#define TSI_DPRX_DPCD_DATA TSI_BASE_LEGACY_DPRX(0xA) +#define TSI_DPRX_MAX_LANES TSI_BASE_LEGACY_DPRX(0x10) +#define TSI_DPRX_MAX_LINK_RATE TSI_BASE_LEGACY_DPRX(0x11) +#define TSI_DPRX_LINK_FLAGS TSI_BASE_LEGACY_DPRX(0x12) +#define TSI_DPRX_STREAM_SELECT TSI_BASE_LEGACY_DPRX(0x13) +#define TSI_DPRX_CRC_R_R TSI_BASE_LEGACY_DPRX(0x14) +#define TSI_DPRX_CRC_G_R TSI_BASE_LEGACY_DPRX(0x15) +#define TSI_DPRX_CRC_B_R TSI_BASE_LEGACY_DPRX(0x16) +#define TSI_DPRX_HPD_PULSE_W TSI_BASE_LEGACY_DPRX(0x1B) + +#define H2_SINK_LOAD_PROD_KEYS 0x002 +#define H2_SINK_UNLOAD_KEYS 0x003 +#define H2_SINK_SET_CAPABLE 0x004 +#define H2_SINK_CLEAR_CAPABLE 0x005 + +#define TSI_BASE_LEGACY_HDCP2(offset) (0x290 + (offset)) +#define TSI_HDCP_2X_COMMAND_W TSI_BASE_LEGACY_HDCP2(0x1) + +#endif /* TSI_REG_H */ -- 2.52.0