[i-g-t 0/3] tests/xe: Add IGT coverage for SVM madvise autoreset on unmap.

[i-g-t 0/3] tests/xe: Add IGT coverage for SVM madvise autoreset on unmap.

[Arvind Yadav]

Cover full and partial unmap cases for both CPU-only and GPU-touched
VMAs, and verify that only unmapped regions are reset to default
attributes.

Test cases:

  1. multi-region-partial-unmap-no-gpu
     Set PAT=UC on 10 x 1MB VMAs, unmap 3 non-sequential regions
     without GPU access and verify remaining mapped regions retain PAT=UC.

  2. single-vma-full-unmap-no-gpu
     Set PAT=UC on a 1MB VMA, fully unmap it without GPU access, and
     verify the attribute resets to default.

  3. multi-region-partial-unmap
     Run GPU workload on all regions, then unmap 3 non-sequential
     regions and verify remaining mapped regions retain PAT=UC.

Arvind Yadav (3):
  tests/intel/xe_madvise: Add multi-region-partial-unmap-no-gpu subtest
  tests/intel/xe_madvise: Add single-vma-full-unmap-no-gpu subtest
  tests/intel/xe_madvise: Add multi-region-partial-unmap subtest

 tests/intel/xe_madvise.c | 412 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 412 insertions(+)

-- 
2.43.0

[i-g-t 1/3] tests/intel/xe_madvise: Add multi-region-partial-unmap-no-gpu subtest

[Arvind Yadav]

Verify PAT preservation on partial unmap without GPU access.

Set PAT=UC on multiple regions, unmap a subset, and verify that
remaining mapped regions retain PAT=UC.

Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Cc: Nishit Sharma <nishit.sharma@intel.com>
Cc: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Arvind Yadav <arvind.yadav@intel.com>
---
 tests/intel/xe_madvise.c | 138 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 138 insertions(+)

diff --git a/tests/intel/xe_madvise.c b/tests/intel/xe_madvise.c
index 2375f5475..37411f342 100644
--- a/tests/intel/xe_madvise.c
+++ b/tests/intel/xe_madvise.c
@@ -17,6 +17,11 @@
 #include "xe/xe_ioctl.h"
 #include "xe/xe_query.h"
 #include "lib/igt_syncobj.h"
+#include "intel_pat.h"
+
+/* SVM madvise test constants */
+#define USER_FENCE_VALUE	0xdeadbeefdeadbeefull
+#define FIVE_SEC		(5LL * NSEC_PER_SEC)
 
 static bool xe_has_purgeable_support(int fd)
 {
@@ -775,6 +780,136 @@ out:
 		igt_skip("Unable to induce purge on this platform/config");
 }
 
+/**
+ * SUBTEST: multi-region-partial-unmap-no-gpu
+ * Description: Verify only unmapped regions are reset on partial unmap
+ *              without GPU access.
+ * Test category: functionality test
+ */
+static void
+test_multi_region_partial_unmap_no_gpu(int fd)
+{
+	static const int unmap_regions[] = {2, 5, 8};
+	static const int num_regions = 10;
+	const size_t region_size = SZ_1M;
+	const size_t total_size = num_regions * region_size;
+	const int num_unmap = ARRAY_SIZE(unmap_regions);
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		  .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		  .timeline_value = USER_FENCE_VALUE },
+	};
+	struct drm_xe_mem_range_attr *attrs;
+	struct drm_xe_madvise madvise;
+	uint32_t num_ranges;
+	uint64_t vm_sync = 0;
+	uint8_t pat_uc;
+	uint32_t va_bits;
+	void *base_addr;
+	uint32_t vm;
+	int i, j;
+
+	pat_uc = intel_get_pat_idx_uc(fd);
+	va_bits = xe_va_bits(fd);
+
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE |
+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
+
+	base_addr = mmap(NULL, total_size, PROT_READ | PROT_WRITE,
+			 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	igt_assert(base_addr != MAP_FAILED);
+
+	/* Bind address space with CPU_ADDR_MIRROR and MADVISE_AUTORESET */
+	sync[0].addr = to_user_pointer(&vm_sync);
+	__xe_vm_bind_assert(fd, vm, 0,
+			    0, 0, 0, 0x1ull << va_bits,
+			    DRM_XE_VM_BIND_OP_MAP,
+			    DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR |
+			    DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET,
+			    sync, 1, 0, 0);
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, FIVE_SEC);
+
+	/* Set PAT=UC on the entire 10MB region */
+	memset(&madvise, 0, sizeof(madvise));
+	madvise.vm_id = vm;
+	madvise.start = to_user_pointer(base_addr);
+	madvise.range = total_size;
+	madvise.type = DRM_XE_MEM_RANGE_ATTR_PAT;
+	madvise.pat_index.val = pat_uc;
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise), 0);
+
+	/* Verify PAT=UC across all regions */
+	attrs = xe_vm_get_mem_attr_values_in_range(fd, vm,
+						   to_user_pointer(base_addr),
+						   total_size, &num_ranges);
+	igt_assert_f(attrs && num_ranges > 0,
+		     "Expected at least 1 range after setting PAT\n");
+	for (i = 0; i < num_ranges; i++) {
+		uint8_t got = attrs[i].pat_index.val;
+
+		if (got != pat_uc) {
+			free(attrs);
+			igt_assert_f(false, "range[%d]: expected UC=%u got %u\n",
+				     i, pat_uc, got);
+		}
+	}
+	free(attrs);
+
+	/* Partially unmap non-sequential regions: 2, 5, 8 */
+	for (i = 0; i < num_unmap; i++)
+		igt_assert_eq(munmap(base_addr + (unmap_regions[i] * region_size), region_size), 0);
+
+	/* Remaining mapped regions must still have PAT=UC */
+	for (i = 0; i < num_regions; i++) {
+		bool is_unmapped = false;
+
+		for (j = 0; j < num_unmap; j++) {
+			if (unmap_regions[j] == i) {
+				is_unmapped = true;
+				break;
+			}
+		}
+
+		if (is_unmapped)
+			continue;
+
+		attrs = xe_vm_get_mem_attr_values_in_range(fd, vm,
+							   to_user_pointer(base_addr +
+							   (i * region_size)),
+							   region_size, &num_ranges);
+		igt_assert_f(attrs && num_ranges > 0,
+			     "Region %d: mapped region lost attributes after partial unmap\n", i);
+		for (j = 0; j < num_ranges; j++) {
+			uint8_t got = attrs[j].pat_index.val;
+
+			if (got != pat_uc) {
+				free(attrs);
+				igt_assert_f(false,
+					     "Region %d range[%d]: PAT changed to %u after partial unmap, expected UC=%u\n",
+					     i, j, got, pat_uc);
+			}
+		}
+		free(attrs);
+	}
+
+	/* Cleanup remaining mapped regions */
+	for (i = 0; i < num_regions; i++) {
+		bool is_unmapped = false;
+
+		for (j = 0; j < num_unmap; j++) {
+			if (unmap_regions[j] == i) {
+				is_unmapped = true;
+				break;
+			}
+		}
+
+		if (!is_unmapped)
+			munmap(base_addr + (i * region_size), region_size);
+	}
+
+	xe_vm_destroy(fd, vm);
+}
+
 int igt_main()
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -829,6 +964,9 @@ int igt_main()
 			break;
 		}
 
+	igt_subtest("multi-region-partial-unmap-no-gpu")
+		test_multi_region_partial_unmap_no_gpu(fd);
+
 	igt_fixture() {
 		xe_device_put(fd);
 		drm_close_driver(fd);
-- 
2.43.0

[i-g-t 2/3] tests/intel/xe_madvise: Add single-vma-full-unmap-no-gpu subtest

[Arvind Yadav]

Verify PAT reset after full unmap without GPU access.

Set PAT=UC on a 1MB VMA, fully unmap it, and verify the attribute
resets to default.

Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Cc: Nishit Sharma <nishit.sharma@intel.com>
Cc: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Arvind Yadav <arvind.yadav@intel.com>
---
 tests/intel/xe_madvise.c | 112 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/tests/intel/xe_madvise.c b/tests/intel/xe_madvise.c
index 37411f342..2c8c00f79 100644
--- a/tests/intel/xe_madvise.c
+++ b/tests/intel/xe_madvise.c
@@ -910,6 +910,115 @@ test_multi_region_partial_unmap_no_gpu(int fd)
 	xe_vm_destroy(fd, vm);
 }
 
+/**
+ * SUBTEST: single-vma-full-unmap-no-gpu
+ * Description: Verify PAT resets on full unmap without GPU access.
+ * Test category: functionality test
+ */
+static void
+test_single_vma_full_unmap_no_gpu(int fd)
+{
+	const size_t total_size = SZ_1M;
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		  .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		  .timeline_value = USER_FENCE_VALUE },
+	};
+	struct drm_xe_mem_range_attr *attrs;
+	struct drm_xe_madvise madvise;
+	uint32_t num_ranges;
+	uint64_t vm_sync = 0;
+	uint8_t pat_uc, pat_wb;
+	uint32_t va_bits;
+	void *base_addr;
+	bool reset_done;
+	uint32_t vm;
+	int i;
+
+	pat_uc = intel_get_pat_idx_uc(fd);
+	pat_wb = intel_get_pat_idx_wb(fd);
+	va_bits = xe_va_bits(fd);
+
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE |
+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
+
+	base_addr = mmap(NULL, total_size, PROT_READ | PROT_WRITE,
+			 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	igt_assert(base_addr != MAP_FAILED);
+
+	/* Bind address space with CPU_ADDR_MIRROR and MADVISE_AUTORESET */
+	sync[0].addr = to_user_pointer(&vm_sync);
+	__xe_vm_bind_assert(fd, vm, 0,
+			    0, 0, 0, 0x1ull << va_bits,
+			    DRM_XE_VM_BIND_OP_MAP,
+			    DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR |
+			    DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET,
+			    sync, 1, 0, 0);
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, FIVE_SEC);
+
+	/* Set PAT=UC on the entire 1MB region */
+	memset(&madvise, 0, sizeof(madvise));
+	madvise.vm_id = vm;
+	madvise.start = to_user_pointer(base_addr);
+	madvise.range = total_size;
+	madvise.type = DRM_XE_MEM_RANGE_ATTR_PAT;
+	madvise.pat_index.val = pat_uc;
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise), 0);
+
+	/* Verify PAT=UC is applied before unmap */
+	attrs = xe_vm_get_mem_attr_values_in_range(fd, vm,
+						   to_user_pointer(base_addr),
+						   total_size, &num_ranges);
+	igt_assert_f(attrs && num_ranges > 0,
+		     "Expected at least 1 range after setting PAT\n");
+	for (i = 0; i < num_ranges; i++) {
+		uint8_t got = attrs[i].pat_index.val;
+
+		if (got != pat_uc) {
+			free(attrs);
+			igt_assert_f(false, "range[%d]: expected UC=%u got %u\n",
+				     i, pat_uc, got);
+		}
+	}
+	free(attrs);
+
+	/* Full unmap — MADVISE_AUTORESET must reset the attribute */
+	igt_assert_eq(munmap(base_addr, total_size), 0);
+
+	/* Reset is asynchronous; poll for up to 5 seconds. */
+	reset_done = false;
+
+	for (i = 0; i < 5; i++) {
+		int j;
+
+		sleep(1);
+		attrs = xe_vm_get_mem_attr_values_in_range(fd, vm,
+							   to_user_pointer(base_addr),
+							   total_size, &num_ranges);
+		if (!attrs) {
+			reset_done = true; /* no ranges — reset complete */
+			break;
+		}
+
+		reset_done = true;
+		for (j = 0; j < num_ranges; j++) {
+			if (attrs[j].pat_index.val != pat_wb) {
+				reset_done = false;
+				break;
+			}
+		}
+		free(attrs);
+
+		if (reset_done)
+			break;
+	}
+
+	igt_assert_f(reset_done,
+		     "PAT not reset to WB=%u within 5s after full unmap\n", pat_wb);
+
+	xe_vm_destroy(fd, vm);
+}
+
 int igt_main()
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -967,6 +1076,9 @@ int igt_main()
 	igt_subtest("multi-region-partial-unmap-no-gpu")
 		test_multi_region_partial_unmap_no_gpu(fd);
 
+	igt_subtest("single-vma-full-unmap-no-gpu")
+		test_single_vma_full_unmap_no_gpu(fd);
+
 	igt_fixture() {
 		xe_device_put(fd);
 		drm_close_driver(fd);
-- 
2.43.0

[i-g-t 3/3] tests/intel/xe_madvise: Add multi-region-partial-unmap subtest

[Arvind Yadav]

Verify that madvise PAT attributes are preserved on mapped regions
after partial unmap.

Run GPU access on all regions and set PAT=UC on multiple regions,
unmap a subset, and verify that remaining mapped regions retain PAT=UC.

Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Cc: Nishit Sharma <nishit.sharma@intel.com>
Cc: Pravalika Gurram <pravalika.gurram@intel.com>
Signed-off-by: Arvind Yadav <arvind.yadav@intel.com>
---
 tests/intel/xe_madvise.c | 185 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 185 insertions(+)

diff --git a/tests/intel/xe_madvise.c b/tests/intel/xe_madvise.c
index 2c8c00f79..82ec4d99c 100644
--- a/tests/intel/xe_madvise.c
+++ b/tests/intel/xe_madvise.c
@@ -1019,6 +1019,185 @@ test_single_vma_full_unmap_no_gpu(int fd)
 	xe_vm_destroy(fd, vm);
 }
 
+/**
+ * SUBTEST: multi-region-partial-unmap
+ * Description: Verify only unmapped regions are reset on partial unmap
+ *              after GPU access.
+ * Test category: functionality test
+ */
+static void
+test_multi_region_partial_unmap(int fd, struct drm_xe_engine_class_instance *hwe)
+{
+	static const int unmap_regions[] = {2, 5, 8};
+	static const int num_regions = 10;
+	const size_t region_size = SZ_1M;
+	const size_t total_size = num_regions * region_size;
+	const int num_unmap = ARRAY_SIZE(unmap_regions);
+	struct drm_xe_sync sync[1] = {
+		{ .type = DRM_XE_SYNC_TYPE_USER_FENCE,
+		  .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+		  .timeline_value = USER_FENCE_VALUE },
+	};
+	struct region_work {
+		uint32_t batch[16];
+		uint64_t exec_sync;
+		uint32_t data;
+	} *rw;
+	struct drm_xe_exec exec = {
+		.num_batch_buffer = 1,
+		.num_syncs = 1,
+		.syncs = to_user_pointer(sync),
+	};
+	struct drm_xe_mem_range_attr *attrs;
+	struct drm_xe_madvise madvise;
+	uint32_t num_ranges;
+	uint64_t vm_sync = 0;
+	uint32_t exec_queue;
+	uint8_t pat_uc;
+	uint32_t va_bits;
+	void *base_addr;
+	uint32_t vm;
+	int i, j;
+
+	/* Require dGPU with visible VRAM for CPU-mirror page faults. */
+	igt_require(xe_visible_vram_size(fd, 0));
+
+	pat_uc = intel_get_pat_idx_uc(fd);
+	va_bits = xe_va_bits(fd);
+
+	vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE |
+			  DRM_XE_VM_CREATE_FLAG_FAULT_MODE, 0);
+
+	base_addr = mmap(NULL, total_size, PROT_READ | PROT_WRITE,
+			 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+	igt_assert(base_addr != MAP_FAILED);
+
+	/* Bind address space with CPU_ADDR_MIRROR and MADVISE_AUTORESET */
+	sync[0].addr = to_user_pointer(&vm_sync);
+	__xe_vm_bind_assert(fd, vm, 0,
+			    0, 0, 0, 0x1ull << va_bits,
+			    DRM_XE_VM_BIND_OP_MAP,
+			    DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR |
+			    DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET,
+			    sync, 1, 0, 0);
+	xe_wait_ufence(fd, &vm_sync, USER_FENCE_VALUE, 0, FIVE_SEC);
+
+	/* Set PAT=UC on the entire 10MB region */
+	memset(&madvise, 0, sizeof(madvise));
+	madvise.vm_id = vm;
+	madvise.start = to_user_pointer(base_addr);
+	madvise.range = total_size;
+	madvise.type = DRM_XE_MEM_RANGE_ATTR_PAT;
+	madvise.pat_index.val = pat_uc;
+	igt_assert_eq(igt_ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise), 0);
+
+	/* Verify PAT=UC across all regions */
+	attrs = xe_vm_get_mem_attr_values_in_range(fd, vm,
+						   to_user_pointer(base_addr),
+						   total_size, &num_ranges);
+	igt_assert_f(attrs && num_ranges > 0,
+		     "Expected at least 1 range after setting PAT\n");
+	for (i = 0; i < num_ranges; i++) {
+		uint8_t got = attrs[i].pat_index.val;
+
+		if (got != pat_uc) {
+			free(attrs);
+			igt_assert_f(false, "range[%d]: expected UC=%u got %u\n",
+				     i, pat_uc, got);
+		}
+	}
+	free(attrs);
+
+	/* Touch every region to trigger GPU page faults */
+	exec_queue = xe_exec_queue_create(fd, vm, hwe, 0);
+
+	for (i = 0; i < num_regions; i++) {
+		uint64_t data_addr;
+		int b = 0;
+
+		rw = base_addr + (i * region_size);
+		memset(rw, 0, sizeof(*rw));
+
+		data_addr = to_user_pointer(&rw->data);
+
+		rw->batch[b++] = MI_STORE_DWORD_IMM_GEN4;
+		rw->batch[b++] = (uint32_t)data_addr;
+		rw->batch[b++] = (uint32_t)(data_addr >> 32);
+		rw->batch[b++] = 0xc0de0000 | i;
+		rw->batch[b++] = MI_BATCH_BUFFER_END;
+
+		rw->exec_sync = 0;
+		sync[0].addr = to_user_pointer(&rw->exec_sync);
+
+		exec.exec_queue_id = exec_queue;
+		exec.address = to_user_pointer(rw->batch);
+
+		xe_exec(fd, &exec);
+		xe_wait_ufence(fd, &rw->exec_sync, USER_FENCE_VALUE,
+			       exec_queue, FIVE_SEC);
+		igt_assert_eq_u32(rw->data, 0xc0de0000 | i);
+	}
+
+	xe_exec_queue_destroy(fd, exec_queue);
+
+	/* Partially unmap non-sequential regions: 2, 5, 8 */
+	for (i = 0; i < num_unmap; i++)
+		igt_assert_eq(munmap(base_addr + (unmap_regions[i] * region_size), region_size), 0);
+
+	/*
+	 * Remaining mapped regions must still have PAT=UC.
+	 * A partial unmap must not reset attributes on untouched VMAs.
+	 */
+	for (i = 0; i < num_regions; i++) {
+		bool is_unmapped = false;
+
+		for (j = 0; j < num_unmap; j++) {
+			if (unmap_regions[j] == i) {
+				is_unmapped = true;
+				break;
+			}
+		}
+
+		if (is_unmapped)
+			continue;
+
+		attrs = xe_vm_get_mem_attr_values_in_range(fd, vm,
+							   to_user_pointer(base_addr +
+							   (i * region_size)),
+							   region_size, &num_ranges);
+		igt_assert_f(attrs && num_ranges > 0,
+			     "Region %d: mapped region lost attributes after partial unmap\n", i);
+		for (j = 0; j < num_ranges; j++) {
+			uint8_t got = attrs[j].pat_index.val;
+
+			if (got != pat_uc) {
+				free(attrs);
+				igt_assert_f(false,
+					     "Region %d range[%d]: PAT changed to %u after partial unmap, expected UC=%u\n",
+					     i, j, got, pat_uc);
+			}
+		}
+		free(attrs);
+	}
+
+	/* Cleanup remaining mapped regions */
+	for (i = 0; i < num_regions; i++) {
+		bool is_unmapped = false;
+
+		for (j = 0; j < num_unmap; j++) {
+			if (unmap_regions[j] == i) {
+				is_unmapped = true;
+				break;
+			}
+		}
+
+		if (!is_unmapped)
+			munmap(base_addr + (i * region_size), region_size);
+	}
+
+	xe_vm_destroy(fd, vm);
+}
+
 int igt_main()
 {
 	struct drm_xe_engine_class_instance *hwe;
@@ -1079,6 +1258,12 @@ int igt_main()
 	igt_subtest("single-vma-full-unmap-no-gpu")
 		test_single_vma_full_unmap_no_gpu(fd);
 
+	igt_subtest("multi-region-partial-unmap")
+		xe_for_each_engine(fd, hwe) {
+			test_multi_region_partial_unmap(fd, hwe);
+			break;
+		}
+
 	igt_fixture() {
 		xe_device_put(fd);
 		drm_close_driver(fd);
-- 
2.43.0

✗ Fi.CI.BUILD: failure for tests/xe: Add IGT coverage for SVM madvise autoreset on unmap.

[Patchwork]

== Series Details ==

Series: tests/xe: Add IGT coverage for SVM madvise autoreset on unmap.
URL   : https://patchwork.freedesktop.org/series/164387/
State : failure

== Summary ==

Applying: tests/intel/xe_madvise: Add multi-region-partial-unmap-no-gpu subtest
Using index info to reconstruct a base tree...
A	tests/intel/xe_madvise.c
Falling back to patching base and 3-way merge...
CONFLICT (modify/delete): tests/intel/xe_madvise.c deleted in HEAD and modified in tests/intel/xe_madvise: Add multi-region-partial-unmap-no-gpu subtest. Version tests/intel/xe_madvise: Add multi-region-partial-unmap-no-gpu subtest of tests/intel/xe_madvise.c left in tree.
Patch failed at 0001 tests/intel/xe_madvise: Add multi-region-partial-unmap-no-gpu subtest
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".