[PATCH i-g-t, v2] tests/intel/kms_cdclk: Skip CDCLK bump validation on eDP with fixed clock modes

[Swati Sharma <swati2.sharma@intel.com>]

eDP panels may expose modes with the same resolution and pixel clock
but different vtotal. Since only the vblank region differs, the CDCLK
requirement remains identical across such modes, so no CDCLK bump is
expected.

Skip CDCLK bump validation on eDP connectors where modes share the
same hdisplay, vdisplay and clock but vary only in vtotal.

Suggested-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 tests/intel/kms_cdclk.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/tests/intel/kms_cdclk.c b/tests/intel/kms_cdclk.c
index 20b8a5f0a..a015afa29 100644
--- a/tests/intel/kms_cdclk.c
+++ b/tests/intel/kms_cdclk.c
@@ -72,6 +72,24 @@ static bool hardware_supported(data_t *data)
 	return false;
 }
 
+static bool edp_has_fixed_clock_modes(igt_output_t *output)
+{
+	drmModeConnector *connector = output->config.connector;
+
+	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+		return false;
+
+	for (int i = 0; i < connector->count_modes; i++)
+		for (int j = i + 1; j < connector->count_modes; j++)
+			if (connector->modes[i].hdisplay == connector->modes[j].hdisplay &&
+			    connector->modes[i].vdisplay == connector->modes[j].vdisplay &&
+			    connector->modes[i].clock == connector->modes[j].clock &&
+			    connector->modes[i].vtotal != connector->modes[j].vtotal)
+				return true;
+
+	return false;
+}
+
 static __u64 get_mode_data_rate(drmModeModeInfo *mode)
 {
 	__u64 data_rate = (__u64)mode->hdisplay * (__u64)mode->vdisplay * (__u64)mode->vrefresh;
@@ -329,6 +347,20 @@ static void run_cdclk_test(data_t *data, uint32_t flags)
 	igt_crtc_t *crtc;
 
 	for_each_crtc_with_valid_output(display, crtc, output) {
+		/*
+		 * eDP panels may expose modes with the same resolution and
+		 * pixel clock but different vtotal. Since only the vblank
+		 * region differs, the CDCLK requirement remains identical
+		 * across such modes, so no CDCLK bump is expected and
+		 * validating it would lead to false failures.
+		 */
+		if ((flags & TEST_MODETRANSITION) &&
+		    edp_has_fixed_clock_modes(output)) {
+			igt_info("Skipping %s: eDP has modes with same clock "
+				 "but different vtotal\n", output->name);
+			continue;
+		}
+
 		igt_output_set_crtc(output,
 				    crtc);
 		if (!intel_pipe_output_combo_valid(display)) {
-- 
2.25.1