[PATCH i-g-t v3 6/6] RFC: tests/intel/kms_pm_dc: Add new test for DC3CO recovery after DC6

Jeevan B
2026-04-23T17:36:46Z

Adds a test to verify DC3CO continues to function properly
after a DC6 power cycle.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
tests/intel/kms_pm_dc.c | 65 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)

diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 22ae51b51..6d2bd0ee1 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -55,6 +55,11 @@
* Description: Verify that DC3CO entry does not cause frame drops and successfully
* enters the power state
*
+ * SUBTEST: dc3co-after-dc6
+ * Description: Verify DC3CO entry is still functional after a DC6 entry and
+ * exit cycle, ensuring DC3CO is not broken by deeper power state
+ * transitions.
+ *
* SUBTEST: dc5-dpms
* Description: Validate display engine entry to DC5 state while all connectors's
* DPMS property set to OFF
@@ -629,6 +634,42 @@ static int has_panels_without_dc_support(igt_display_t *display)
return external_panel;
}

+static void test_dc3co_after_dc6(data_t *data, enum psr_mode mode)
+{
+ uint32_t dc6_prev_cnt;
+
+ igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+ igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC6);
+
+ setup_output(data);
+
+ /* Enable PSR2/PR */
+ data->op_psr_mode = mode;
+ psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, NULL);
+ igt_require_f(psr_wait_entry(data->debugfs_fd, data->op_psr_mode, NULL),
+ "%s is not enabled\n",
+ mode == PSR_MODE_2 ? "PSR2" : "Panel Replay");
+
+ /* Trigger a DC6 cycle */
+ dc6_prev_cnt = igt_read_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC6);
+ setup_dc_dpms(data);
+ dpms_off(data);
+ assert_dc_counter(data, IGT_INTEL_CHECK_DC6, dc6_prev_cnt);
+ dpms_on(data);
+ cleanup_dc_dpms(data);
+
+ /* Re-enable PSR2/PR after DC6 exit */
+ psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, NULL);
+ igt_require_f(psr_wait_entry(data->debugfs_fd, data->op_psr_mode, NULL),
+ "%s not re-enabled after DC6 exit\n",
+ mode == PSR_MODE_2 ? "PSR2" : "Panel Replay");
+
+ /* Verify DC3CO still works after DC6 */
+ setup_videoplayback(data);
+ check_dc3co_with_videoplayback_like_load(data);
+ cleanup_dc3co_fbs(data);
+}
+
static void test_deep_pkgc_state(data_t *data)
{
unsigned int pre_val = 0, cur_val = 0;
@@ -799,6 +840,30 @@ int igt_main()
}
}

+ igt_describe("Verify DC3CO entry is still functional after a DC6 entry "
+ "and exit cycle");
+ igt_subtest_with_dynamic("dc3co-after-dc6") {
+ igt_dynamic("psr2") {
+ igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+ PSR_MODE_2, NULL));
+ igt_require_f(IS_TIGERLAKE(data.devid) ||
+ intel_display_ver(data.devid) >= 35,
+ "Platform does not support DC3CO with PSR2\n");
+ igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
+ "PC8+ residencies not supported\n");
+ test_dc3co_after_dc6(&data, PSR_MODE_2);
+ }
+ igt_dynamic("pr") {
+ igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+ PR_MODE, NULL));
+ igt_require_f(intel_display_ver(data.devid) >= 35,
+ "Platform does not support DC3CO with Panel Replay\n");
+ igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
+ "PC8+ residencies not supported\n");
+ test_dc3co_after_dc6(&data, PR_MODE);
+ }
+ }
+
igt_describe("This test validates display engine entry to DC5 state "
"while PSR is active");
igt_subtest("dc5-psr") {
--
2.43.0