[PATCH i-g-t v3 5/6] tests/intel/kms_pm_dc: Add new test for dc3co framedrop validation

Jeevan B
2026-04-23T17:36:57Z

Add a new subtest to validate that no frame drops occur during
DC3CO entry, ensuring that no frame drops are detected and DC3CO
is successfully triggered during the test.

v2: update check_dc3co_framedrop for detecting frame drops via
drmWaitVBlank vblank sequence numbers, checks DC3CO counter
to confirm entry and cast variable 'delay'.
v3: Rename function name from check_dc3co* to detect_dc3co*.

Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
tests/intel/kms_pm_dc.c | 105 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)

diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 83652e9f8..22ae51b51 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -51,6 +51,10 @@
* Description: Make sure that system enters DC3CO when PSR2 is active and system
* is in SLEEP state
*
+ * SUBTEST: dc3co-framedrop-check
+ * Description: Verify that DC3CO entry does not cause frame drops and successfully
+ * enters the power state
+ *
* SUBTEST: dc5-dpms
* Description: Validate display engine entry to DC5 state while all connectors's
* DPMS property set to OFF
@@ -343,6 +347,87 @@ static void test_dc3co_vpb_simulation(data_t *data, enum psr_mode mode)
cleanup_dc3co_fbs(data);
}

+static void detect_dc3co_framedrop(data_t *data)
+{
+ igt_plane_t *primary;
+ uint32_t dc3co_prev_cnt;
+ int delay;
+ int frame_count = 0, frame_drops = 0;
+ int max_count = 60;
+ bool dc3co_flag = false;
+ bool front = false;
+ struct drm_event_vblank ev;
+ uint64_t last_flip_ns = 0, cur_flip_ns;
+ uint64_t frame_time_ns;
+
+ igt_require_f(data->mode->vrefresh != 0, "Invalid vrefresh rate of 0\n");
+
+ frame_time_ns = UINT64_C(1000000000) / data->mode->vrefresh;
+
+ primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY);
+ igt_plane_set_fb(primary, NULL);
+ igt_display_commit(&data->display);
+
+ dc3co_prev_cnt = igt_read_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+
+ delay = (int)(1.5 * (1000000 / data->mode->vrefresh));
+
+ igt_plane_set_fb(primary, &data->fb_rgb);
+ igt_assert_eq(igt_display_try_commit_atomic(&data->display,
+ DRM_MODE_ATOMIC_NONBLOCK |
+ DRM_MODE_PAGE_FLIP_EVENT,
+ data), 0);
+ igt_assert_eq(read(data->drm_fd, &ev, sizeof(ev)), sizeof(ev));
+ last_flip_ns = (uint64_t)ev.tv_sec * UINT64_C(1000000000) +
+ (uint64_t)ev.tv_usec * 1000;
+
+ while (frame_count < max_count) {
+ front = !front;
+ igt_plane_set_fb(primary, front ? &data->fb_rgr : &data->fb_rgb);
+ usleep(delay);
+
+ igt_assert_eq(igt_display_try_commit_atomic(&data->display,
+ DRM_MODE_ATOMIC_NONBLOCK |
+ DRM_MODE_PAGE_FLIP_EVENT,
+ data), 0);
+
+ igt_set_timeout(2, "Waiting for flip event\n");
+ igt_assert_eq(read(data->drm_fd, &ev, sizeof(ev)), sizeof(ev));
+ igt_reset_timeout();
+
+ cur_flip_ns = (uint64_t)ev.tv_sec * UINT64_C(1000000000) +
+ (uint64_t)ev.tv_usec * 1000;
+
+ if (last_flip_ns != 0 &&
+ (cur_flip_ns - last_flip_ns) > 2 * frame_time_ns)
+ frame_drops++;
+
+ last_flip_ns = cur_flip_ns;
+
+ if (!dc3co_flag &&
+ igt_read_dc_counter(data->debugfs_fd,
+ IGT_INTEL_CHECK_DC3CO) > dc3co_prev_cnt)
+ dc3co_flag = true;
+
+ frame_count++;
+ }
+
+ igt_assert_f(dc3co_flag, "DC3CO was not entered during the test\n");
+ igt_assert_f(frame_drops == 0,
+ "Frame drops detected: %d drops out of %d frames\n",
+ frame_drops, frame_count);
+}
+
+static void test_dc3co_framedrop(data_t *data, enum psr_mode mode)
+{
+ igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
+ setup_output(data);
+ setup_dc3co(data, mode);
+ setup_videoplayback(data);
+ detect_dc3co_framedrop(data);
+ cleanup_dc3co_fbs(data);
+}
+
static void test_dc5_retention_flops(data_t *data, int dc_flag)
{
uint32_t dc_counter_before_psr;
@@ -694,6 +779,26 @@ int igt_main()
}
}

+ igt_describe("Validate that no frame drops occur during DC3CO entry "
+ "while alternating framebuffers with PSR2 or Panel Replay active");
+ igt_subtest_with_dynamic("dc3co-framedrop-check") {
+ igt_dynamic("psr2") {
+ igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+ PSR_MODE_2, NULL));
+ igt_require_f(IS_TIGERLAKE(data.devid) ||
+ intel_display_ver(data.devid) >= 35,
+ "Platform does not support DC3CO with PSR2\n");
+ test_dc3co_framedrop(&data, PSR_MODE_2);
+ }
+ igt_dynamic("pr") {
+ igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+ PR_MODE, NULL));
+ igt_require_f(intel_display_ver(data.devid) >= 35,
+ "Platform does not support DC3CO with Panel Replay\n");
+ test_dc3co_framedrop(&data, PR_MODE);
+ }
+ }
+
igt_describe("This test validates display engine entry to DC5 state "
"while PSR is active");
igt_subtest("dc5-psr") {
--
2.43.0