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Thu, 16 Jul 2026 01:33:15 -0500 Received: from james-PlumDAP-MDS1.amd.com (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Thu, 16 Jul 2026 01:33:08 -0500 From: James Lin To: CC: , , , , James Lin Subject: [PATCH i-g-t] tests/kms_plane_alpha_blend: Skip 7efc alpha-swap CRC check on AMD at >8bpc/DSC Date: Thu, 16 Jul 2026 14:35:59 +0800 Message-ID: <20260716063619.3344-1-PingLei.Lin@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003441:EE_|CYYPR12MB8889:EE_ X-MS-Office365-Filtering-Correlation-Id: 168186a1-bb7f-464b-15f6-08dee3041e38 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|36860700016|376014|1800799024|82310400026|6133799003|56012099006|11063799006|18002099003|10067099003|3023799007; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QDZJrJ8EcWU19OYVcWeRTGeoFBGFWu/ISUDyTcEpzbq9hLYERQefUQJa7fsNf3TF3+YlWDnDu/vO3ClXRIFhuCV1u8Gq7an3wlXSkKmU8jCIavFbmTa4FzFxkcB/vIPA1wGNeeG4wkgwCM+WOs7VD+nhnF8fCBPJG5REnVqg1V7WkjYTuvnI3DahIT4z8WcNagllkKEvxb4d9OtR6DCwBGcpZtgeYEsluT9+xsp/LYsy9WYEKsLNBaXXiY69qy25IcqqusheaSm1GPBZ1/fzFPMy0fAek79+0SI8XO6i56IKxRGuKvoyW6sY9TP4QkxHdpub6n4EEXD39/lryOlA+PNt5RO6/9Ip3YMEMQ5IbPhXet6ISp6wGczWRdyuZJiL3uLJf++bJ0pWbgyh57pEa1j80EaRr/EbEfxSfoLslh890wnVp6TeBbDFXlieR2Qn X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2026 06:33:15.9166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 168186a1-bb7f-464b-15f6-08dee3041e38 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003441.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8889 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" [Why] alpha-7efc and coverage-7efc assert that swapping the plane global alpha (the KMS "alpha" property) with the per-pixel fb alpha (0x7e <-> 0xfc) yields a bit-identical pipe CRC. That identity only holds when the whole blend datapath collapses to exact 8-bit arithmetic. On AMD DCN the alpha/gain values are 8-bit, but the blend is carried at higher internal precision and only quantized down to the output bpc at the very end. A swap that is exact in idealized 8-bit math can therefore leave a sub-LSB residue: at 8 bpc the output quantization discards it and the CRCs match, but at >8 bpc, or when the stream is DSC-compressed (carried at its native >8 bpc), the residue survives and the CRCs differ. The strict compare then turns a legitimate precision artifact into a test failure - observed as a CRC mismatch on an eDP link brought up with DSC, while the same test passes on an 8-bit non-DSC link. [How] Add skip_if_alpha_swap_not_exact() and call it at the start of alpha_7efc and coverage_7efc. It is a no-op on non-AMD devices, so every other driver keeps the strict check unchanged. On amdgpu it reads the CRTC's current bpc and the connector's DSC status, and skips only when bpc > 8 or DSC is active - the conditions under which the alpha swap is legitimately not bit-exact. 8 bpc AMD configurations still run the strict compare, preserving the regression coverage the test was written for. Track the output in data_t so the DSC state of the current connector can be queried. Signed-off-by: James Lin --- tests/kms_plane_alpha_blend.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/kms_plane_alpha_blend.c b/tests/kms_plane_alpha_blend.c index 3a2649833..e040d5bec 100644 --- a/tests/kms_plane_alpha_blend.c +++ b/tests/kms_plane_alpha_blend.c @@ -33,6 +33,7 @@ */ #include "igt.h" +#include "igt_amd.h" /** * SUBTEST: alpha-%s @@ -77,6 +78,7 @@ typedef struct { struct igt_fb xrgb_fb, argb_fb_0, argb_fb_cov_0, argb_fb_7e, argb_fb_cov_7e, argb_fb_fc, argb_fb_cov_fc, argb_fb_100, black_fb, gray_fb; igt_crc_t ref_crc; igt_pipe_crc_t *pipe_crc; + igt_output_t *output; } data_t; static bool in_simulation; @@ -442,11 +444,49 @@ static void constant_alpha_max(data_t *data, igt_crtc_t *crtc, igt_plane_set_fb(plane, NULL); } +/* + * The 7e/fc subtests (alpha-7efc, coverage-7efc) assert that swapping the + * plane global alpha with the per-pixel fb alpha (0x7e <-> 0xfc) yields a + * bit-identical pipe CRC. That identity only holds when the whole blend + * datapath collapses to exact 8-bit arithmetic. + * + * On AMD DCN the alpha/gain values are 8-bit, but the blend itself is carried + * at higher internal precision and only quantized down to the output bpc at + * the very end, so the swap can leave a sub-LSB residue. At 8 bpc the output + * quantization discards it and the two CRCs match; at >8 bpc, or when the + * stream is DSC-compressed (carried at its native >8 bpc), the residue is + * retained and the CRCs differ. This matches observation: the same test + * PASSes on an 8 bpc eDP link without DSC and FAILs on an eDP link brought + * up with DSC. + * + * So keep the strict bit-exact check everywhere except AMD at >8 bpc or with + * DSC active, where the swap is legitimately not bit-exact. + */ +static void skip_if_alpha_swap_not_exact(data_t *data, igt_crtc_t *crtc) +{ + unsigned int bpc; + bool dsc; + + if (!is_amdgpu_device(data->gfx_fd)) + return; + + bpc = igt_get_crtc_current_bpc(crtc); + dsc = data->output && + is_dp_dsc_supported(data->gfx_fd, data->output->name) && + igt_amd_read_dsc_clock_status(data->gfx_fd, data->output->name) > 0; + + igt_skip_on_f(bpc > 8 || dsc, + "plane-alpha/fb-alpha swap is not bit-exact on AMD DCN " + "at >8bpc/DSC (bpc=%u, dsc=%d)\n", bpc, dsc); +} + static void alpha_7efc(data_t *data, igt_crtc_t *crtc, igt_plane_t *plane) { igt_display_t *display = &data->display; igt_crc_t ref_crc = {}, crc = {}; + skip_if_alpha_swap_not_exact(data, crtc); + if (plane->type != DRM_PLANE_TYPE_PRIMARY) igt_plane_set_fb(igt_crtc_get_plane_type(crtc, DRM_PLANE_TYPE_PRIMARY), &data->gray_fb); @@ -475,6 +515,8 @@ static void coverage_7efc(data_t *data, igt_crtc_t *crtc, igt_plane_t *plane) igt_display_t *display = &data->display; igt_crc_t ref_crc = {}, crc = {}; + skip_if_alpha_swap_not_exact(data, crtc); + igt_require(igt_plane_try_prop_enum(plane, IGT_PLANE_PIXEL_BLEND_MODE, "Coverage")); igt_display_commit2(display, COMMIT_ATOMIC); igt_pipe_crc_start(data->pipe_crc); @@ -539,6 +581,8 @@ static void run_test_on_crtc_planes(data_t *data, igt_crtc_t *crtc, int first_plane = -1; int last_plane = -1; + data->output = output; + for_each_plane_on_crtc(crtc, plane) { if (!igt_plane_has_prop(plane, IGT_PLANE_ALPHA)) continue; -- 2.43.0