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Mon, 20 Jul 2026 02:56:02 -0700 Received: from JesseDEV.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Mon, 20 Jul 2026 04:55:56 -0500 From: Jesse Zhang To: CC: Vitaly Prosyak , Alex Deucher , Christian Koenig , Jesse Zhang , Jesse Zhang Subject: [PATCH i-g-t 1/2] tests/amdgpu/amd_deadlock: add gfx user-queue clean-hang reset test Date: Mon, 20 Jul 2026 17:55:41 +0800 Message-ID: <20260720095555.1537413-1-Jesse.Zhang@amd.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066EC:EE_|CH3PR12MB8712:EE_ X-MS-Office365-Filtering-Correlation-Id: 3520bcbd-7deb-4eb7-bad1-08dee6451e9a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700016|376014|82310400026|23010399003|18002099003|10067099003|11063799006|56012099006|6133799003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /TsogaOAgDURVf3HJGCmxMs6iapZxinnCflatTzbx99dj6G+YgjyztIRNsMEtl740/eTUQIFwxx4clGzrHwcP6BdCFIPrlIszRh0d5G+uhCmQm77k8kxVAEotIHpdOUjLMe0ochOC4k/axcgLbfXod0m0OdwNvE/c5cuBuyUjNAF7ILOEpPF1YfWk0nKejgQnBlTeatWh0kNV4wX4KFZKOqwYVYIY7EyN8IMe+K4itNKXG6LHkuaOEtXrGNir4AF52vl1bjmD21+xp+ZD8P2I4b6GgpX/2p57AaoTjc8J9/2lpK315e4gV5VwysbKSMkErBbr+WfIMBu7Ys6ODfXv9Wmx0ft70Qc6Tur3G1kVDPcnc32I053ymHp6a4YMjl1wTCPUCgdt2fVsFjrkR4eMbV+F237qudOfTJmMGaIY3tylywggq1RkREW1Vg8/2N6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2026 09:56:07.2451 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3520bcbd-7deb-4eb7-bad1-08dee6451e9a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066EC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8712 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Submit a gfx user-queue job whose only packet is a WAIT_REG_MEM that never completes (polls a resident BO for a value that never arrives). The queue hangs with no fault, so the driver recovers it with a per-queue reset. Add it as the amdgpu-deadlock-gfx-umq subtest, gated on AMDGPU_ENABLE_USERQTEST and per-queue reset capability. Signed-off-by: Jesse Zhang --- lib/amdgpu/amd_deadlock_helpers.c | 91 +++++++++++++++++++++++++++++++ lib/amdgpu/amd_deadlock_helpers.h | 4 ++ tests/amdgpu/amd_deadlock.c | 9 +++ 3 files changed, 104 insertions(+) diff --git a/lib/amdgpu/amd_deadlock_helpers.c b/lib/amdgpu/amd_deadlock_helpers.c index 06c577085..c679e60c7 100644 --- a/lib/amdgpu/amd_deadlock_helpers.c +++ b/lib/amdgpu/amd_deadlock_helpers.c @@ -412,6 +412,97 @@ bad_access_helper(amdgpu_device_handle device_handle, unsigned int cmd_error, } } +/* + * Emit a WAIT_REG_MEM that waits forever: poll bo_mc (initialised to 0) for a + * value != 0. This is a valid packet that never completes, i.e. a clean hang + * with no page fault, so it can be recovered by a per-queue reset. + */ +static void gfx_ring_emit_wait_reg_mem_hang(struct amdgpu_ring_context *ring_context) +{ + uint32_t i = 0; + + ring_context->pm4[i++] = PACKET3(PACKET3_WAIT_REG_MEM, 5); + ring_context->pm4[i++] = WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ + WAIT_REG_MEM_FUNCTION(4) | /* != */ + WAIT_REG_MEM_ENGINE(0); /* me */ + ring_context->pm4[i++] = ring_context->bo_mc & 0xfffffffc; + ring_context->pm4[i++] = (ring_context->bo_mc >> 32) & 0xffffffff; + ring_context->pm4[i++] = 0; /* reference value */ + ring_context->pm4[i++] = 0xffffffff; /* and mask */ + ring_context->pm4[i++] = 0x00000004; /* poll interval */ + ring_context->pm4_dw = i; +} + +/* + * Submit a single job that hangs the queue on a WAIT_REG_MEM (no fault) and + * let per-queue reset recover it. Uses the normal (synchronised) submit path + * so the CP actually runs the packet. + */ +void amdgpu_hang_ring_helper(amdgpu_device_handle device_handle, unsigned int ip_type, + struct pci_addr *pci, bool user_queue) +{ + const struct amdgpu_ip_block_version *ip_block; + const int write_length = 128; + const int pm4_dw = 256; + struct amdgpu_ring_context *ring_context; + int r = 0; + + ip_block = get_ip_block(device_handle, ip_type); + ring_context = calloc(1, sizeof(*ring_context)); + igt_assert(ring_context); + + if (user_queue) { + ip_block->funcs->userq_create(device_handle, ring_context, ip_type); + } else { + r = amdgpu_cs_ctx_create(device_handle, &ring_context->context_handle); + igt_assert_eq(r, 0); + } + + ring_context->write_length = write_length; + ring_context->pm4 = calloc(pm4_dw, sizeof(*ring_context->pm4)); + ring_context->pm4_size = pm4_dw; + ring_context->res_cnt = 1; + ring_context->ring_id = 0; + ring_context->user_queue = user_queue; + igt_assert(ring_context->pm4); + + r = amdgpu_bo_alloc_and_map_sync(device_handle, + ring_context->write_length * sizeof(uint32_t), + 4096, AMDGPU_GEM_DOMAIN_GTT, + AMDGPU_GEM_CREATE_CPU_GTT_USWC, + AMDGPU_VM_MTYPE_UC, + &ring_context->bo, + (void **)&ring_context->bo_cpu, + &ring_context->bo_mc, + &ring_context->va_handle, + ring_context->timeline_syncobj_handle, + ++ring_context->point, user_queue); + igt_assert_eq(r, 0); + if (user_queue) { + r = amdgpu_timeline_syncobj_wait(device_handle, + ring_context->timeline_syncobj_handle, + ring_context->point); + igt_assert_eq(r, 0); + } + + /* the memory the queue polls stays 0, so the queue hangs */ + memset((void *)ring_context->bo_cpu, 0, ring_context->write_length * sizeof(uint32_t)); + ring_context->resources[0] = ring_context->bo; + + gfx_ring_emit_wait_reg_mem_hang(ring_context); + + amdgpu_test_exec_cs_helper(device_handle, ip_block->type, ring_context, 0); + + amdgpu_bo_unmap_and_free(ring_context->bo, ring_context->va_handle, ring_context->bo_mc, + ring_context->write_length * sizeof(uint32_t)); + if (user_queue) { + ip_block->funcs->userq_destroy(device_handle, ring_context, ip_type); + } else { + free(ring_context->pm4); + free(ring_context); + } +} + #define MAX_DMABUF_COUNT 0x20000 #define MAX_DWORD_COUNT 256 diff --git a/lib/amdgpu/amd_deadlock_helpers.h b/lib/amdgpu/amd_deadlock_helpers.h index c46ebb67b..accbf2e41 100644 --- a/lib/amdgpu/amd_deadlock_helpers.h +++ b/lib/amdgpu/amd_deadlock_helpers.h @@ -33,5 +33,9 @@ bad_access_ring_helper(amdgpu_device_handle device_handle, unsigned int cmd_erro void amdgpu_hang_sdma_ring_helper(amdgpu_device_handle device_handle, uint8_t hang_type, struct pci_addr *pci); + +void +amdgpu_hang_ring_helper(amdgpu_device_handle device_handle, unsigned int ip_type, + struct pci_addr *pci, bool user_queue); #endif diff --git a/tests/amdgpu/amd_deadlock.c b/tests/amdgpu/amd_deadlock.c index 5325c0ade..118948992 100644 --- a/tests/amdgpu/amd_deadlock.c +++ b/tests/amdgpu/amd_deadlock.c @@ -246,6 +246,15 @@ int igt_main() amdgpu_wait_memory_helper(device, AMDGPU_HW_IP_DMA, &pci, true); } } + + igt_describe("Test-per-queue-reset-of-a-cleanly-hung-gfx-user-queue"); + igt_subtest_with_dynamic("amdgpu-deadlock-gfx-umq") { + if (enable_test && userq_arr_cap[AMD_IP_GFX] && + is_reset_enable(AMD_IP_GFX, AMDGPU_RESET_TYPE_PER_QUEUE, &pci)) { + igt_dynamic_f("amdgpu-deadlock-gfx-umq") + amdgpu_hang_ring_helper(device, AMDGPU_HW_IP_GFX, &pci, true); + } + } #endif igt_fixture() { -- 2.49.0