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Fri, 21 Aug 2026 07:42:00 -0500 From: Junhua Shen To: CC: Vitaly Prosyak , Jesse Zhang , Sunil Khatri , Honglei Huang , Huang Rui , Yiru Ma , Junhua Shen Subject: [PATCH i-g-t v1 3/4] lib/amdgpu: source packet operands from params and size the IB from pm4_size Date: Fri, 21 Aug 2026 20:41:51 +0800 Message-ID: <20260821124152.19670-4-Junhua.Shen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260821124152.19670-1-Junhua.Shen@amd.com> References: <20260821124152.19670-1-Junhua.Shen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|DS7PR12MB5911:EE_ X-MS-Office365-Filtering-Correlation-Id: f55c6189-1e34-422c-896e-08deff819b90 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|1800799024|82310400026|376014|23010399003|22082099003|18002099003|56012099006|11063799006|10067099003; X-Microsoft-Antispam-Message-Info: Jbm4Ef2ZOyqoYxREXjQXMOjS+W31qsMnKTc+T9WOteqPb348iDYsxT4rISRhxy/ICd7hIvFCWZbdaNeJkRaTXQjqNGNFmLFFQKZqpXVy5VzV6UXIyFEGOQe72g29gwuL4i/qy7u0p8+YbSkqaD2Xul9Nj8KNHOkE5FL13JowsAmHdMS82Ezr4yDK8CdcQzW6UyVyi8LnH8hPRliAJlQ0s+iRMpWXuxJXG1g0tFT1QPQmCPL8dIE+w3Mq0PoqBRuHD2LgRjJi4Uec8VsQKCfz/UeID8UvBcCECoRhMn3Iu+XZQ+4l5tqwP80JegOVQFnWG7Ix6t3r33C4JMfSeTamuab+lCo9tOaNqn9oZJHJSgcA5u9NpA1McdkP7pbVLWOy9EcmA2Rv3zIgdoMgTz1v/JGBNPtZnWedwBCg+9waVxPKNOFiSBlhKspnEwZGg9Xu3Qwp1dNfvWjoW7qWDm4jYGDGLbC6vD9cMvnZdYFCD2eIP0MDMYpMiqUX2DD424WcyTA07EJMznCKKt5hpldlXGOPThc3v/FvJL/K13JGskVm9BXYrHkYbniqpnD2zjnCrFE8eEq8EIDyT4WC4VFUo5W8RI2y0LUpOWDvPG+rvZTDm7f3u/nShuSV1GCKqyXCLp6rLm3Xe/qLMTqpT7BvVorrgNAtjFOC+E66s2vzaM2gw+6Ef1C3NtIQlhVx56PN57RC6zkzALigKboT2EvRTQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5911 X-Mailman-Approved-At: Mon, 24 Aug 2026 08:18:13 +0000 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" - Size the legacy IB from pm4_size: the IB carries the PM4 command stream, so its byte size derives from pm4_size, not from write_length (the data transfer size). amdgpu_test_exec_cs_helper() now computes ib_size from pm4_size. - WRITE_LINEAR/WRITE_ATOMIC/COPY_LINEAR take their operand GPU VAs (src/dst) from cmd_packet_params_t, so callers pass virtual addresses directly instead of relying on context-internal BOs. Signed-off-by: Junhua Shen --- lib/amdgpu/amd_command_submission.c | 31 ++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/lib/amdgpu/amd_command_submission.c b/lib/amdgpu/amd_command_submission.c index 26f36256a..261ae096c 100644 --- a/lib/amdgpu/amd_command_submission.c +++ b/lib/amdgpu/amd_command_submission.c @@ -46,13 +46,15 @@ int amdgpu_test_exec_cs_helper(amdgpu_device_handle device, unsigned int ip_type bool user_queue = ring_context->user_queue; const struct amdgpu_ip_block_version *ip_block = NULL; amdgpu_bo_handle *all_res; + uint64_t ib_size; ip_block = get_ip_block(device, ip_type); all_res = alloca(sizeof(ring_context->resources[0]) * (ring_context->res_cnt + 1)); + ib_size = (uint64_t)ring_context->pm4_size * sizeof(*ring_context->pm4); if (expect_failure) { /* allocate IB */ - r = amdgpu_bo_alloc_and_map_sync(device, ring_context->write_length, 4096, + r = amdgpu_bo_alloc_and_map_sync(device, ib_size, 4096, AMDGPU_GEM_DOMAIN_GTT, 0, AMDGPU_VM_MTYPE_UC, &ib_result_handle, &ib_result_cpu, &ib_result_mc_address, &va_handle, @@ -62,7 +64,7 @@ int amdgpu_test_exec_cs_helper(amdgpu_device_handle device, unsigned int ip_type /* prepare CS */ igt_assert(ring_context->pm4_dw <= 1024); /* allocate IB */ - r = amdgpu_bo_alloc_and_map_sync(device, ring_context->write_length, 4096, + r = amdgpu_bo_alloc_and_map_sync(device, ib_size, 4096, AMDGPU_GEM_DOMAIN_GTT, 0, AMDGPU_VM_MTYPE_UC, &ib_result_handle, &ib_result_cpu, &ib_result_mc_address, &va_handle, @@ -1225,8 +1227,11 @@ int cmd_place_packet(cmd_context_t *ctx, const cmd_packet_params_t *params) if (!ctx->ip_block->funcs->write_linear) return -ENOTSUP; - /* TODO: allow user set the dst and data */ - //ctx->ring_ctx->bo_mc = params->dst_addr; + /* Destination operand comes from the caller. */ + if (params->dst_addr) + ctx->ring_ctx->bo_mc = params->dst_addr; + igt_assert_f(ctx->ring_ctx->bo_mc, + "WRITE_LINEAR requires a destination address\n"); ctx->ring_ctx->write_length = params->size; /* Build PM4 packet */ @@ -1239,8 +1244,11 @@ int cmd_place_packet(cmd_context_t *ctx, const cmd_packet_params_t *params) if (!ctx->ip_block->funcs->write_linear_atomic) return -ENOTSUP; - /* TODO: allow user set the dst and data */ - //ctx->ring_ctx->bo_mc = params->dst_addr; + /* Destination operand comes from the caller. */ + if (params->dst_addr) + ctx->ring_ctx->bo_mc = params->dst_addr; + igt_assert_f(ctx->ring_ctx->bo_mc, + "WRITE_ATOMIC requires a destination address\n"); ctx->ring_ctx->write_length = 1; /* Atomic operations typically work on single DWORD */ result = ctx->ip_block->funcs->write_linear_atomic(ctx->ip_block->funcs, @@ -1252,9 +1260,14 @@ int cmd_place_packet(cmd_context_t *ctx, const cmd_packet_params_t *params) if (!ctx->ip_block->funcs->copy_linear) return -ENOTSUP; - /* For copy operations, we need both source and destination addresses */ - /* This would require extending the API to pass both addresses */ - /* For now, use the internal buffer as source */ + /* Copy takes both operands from the caller: bo_mc = source VA, + * bo_mc2 = destination VA. */ + if (params->src_addr) + ctx->ring_ctx->bo_mc = params->src_addr; + if (params->dst_addr) + ctx->ring_ctx->bo_mc2 = params->dst_addr; + igt_assert_f(ctx->ring_ctx->bo_mc && ctx->ring_ctx->bo_mc2, + "COPY_LINEAR requires source and destination addresses\n"); ctx->ring_ctx->write_length = params->size; result = ctx->ip_block->funcs->copy_linear(ctx->ip_block->funcs, -- 2.34.1