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Let's > use the XA 1-way-coherent index for that (PAT index 19), because other > 1-way coherent configurations do not cause GPU caches to be > automatically flushed at the end of a batch in certain occasions due > to the L2 Flush Optimization feature in Xe3p. > > In the specific case of the xe_pat "false-sharing" subtest, it already > checks for XA 1-way-coherent, so it is just simpler to skip the > creation of the dynamic subtest for the 2-way-coherent PAT indices, > which are tagged as reserved by the KMD on the debugfs dump of > pat_sw_config when the workaround is active. > > Signed-off-by: Gustavo Sousa Obviously some feedback from others on early parts of this series, however if this stays the same after... LGTM Reviewed-by: Matt Atwood > --- > lib/intel_pat.c | 4 ++++ > tests/intel/xe_pat.c | 28 ++++++++++++++++++++-------- > 2 files changed, 24 insertions(+), 8 deletions(-) > > diff --git a/lib/intel_pat.c b/lib/intel_pat.c > index ebf5cd428c68..caac00ad68fc 100644 > --- a/lib/intel_pat.c > +++ b/lib/intel_pat.c > @@ -7,6 +7,7 @@ > #include "igt.h" > #include "intel_pat.h" > #include "xe/xe_query.h" > +#include "xe/xe_wa.h" > > enum xe_pat_config { > PAT_SW_CONFIG, > @@ -109,6 +110,9 @@ static int32_t xe_get_pat_config(struct xe_device *xe_dev, struct intel_pat_cach > free(line); > fclose(dbgfs_file); > > + if (xe_wa_from_cache(xe_dev, "14026539277")) > + xe_pat_cache->wb = 19; /* XA 1-way-coherent. */ > + > return parsed; > } > > diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c > index bb2975b545e6..e1d329637aa1 100644 > --- a/tests/intel/xe_pat.c > +++ b/tests/intel/xe_pat.c > @@ -32,6 +32,7 @@ > #include "xe/xe_ioctl.h" > #include "xe/xe_query.h" > #include "xe/xe_util.h" > +#include "xe/xe_wa.h" > > #define XE_COH_NONE 1 > #define XE_COH_AT_LEAST_1WAY 2 > @@ -1865,30 +1866,41 @@ static void false_sharing(int fd) > uint16_t dev_id = intel_get_drm_devid(fd); > uint32_t graphics_ver = intel_get_device_info(dev_id)->graphics_ver; > bool is_dgfx = xe_has_vram(fd); > - > const struct fs_pat_entry *fs_entries; > - int num_entries; > + int num_fs_entries; > + struct intel_pat_cache pat_sw_config; > + int num_pat_entries; > + > + if (xe_wa(fd, "14026539277")) > + num_pat_entries = xe_fetch_pat_sw_config(fd, &pat_sw_config); > > if (intel_graphics_ver(dev_id) == IP_VER(35, 11)) { > - num_entries = ARRAY_SIZE(fs_xe3p_xpc); > + num_fs_entries = ARRAY_SIZE(fs_xe3p_xpc); > fs_entries = fs_xe3p_xpc; > } else if (intel_graphics_ver(dev_id) == IP_VER(35, 10)) { > - num_entries = ARRAY_SIZE(fs_xe3p_lpg); > + num_fs_entries = ARRAY_SIZE(fs_xe3p_lpg); > fs_entries = fs_xe3p_lpg; > } else if (graphics_ver == 20) { > if (is_dgfx) { > - num_entries = ARRAY_SIZE(fs_xe2_discrete); > + num_fs_entries = ARRAY_SIZE(fs_xe2_discrete); > fs_entries = fs_xe2_discrete; > } else { > - num_entries = ARRAY_SIZE(fs_xe2_integrated); > + num_fs_entries = ARRAY_SIZE(fs_xe2_integrated); > fs_entries = fs_xe2_integrated; > } > } else { > - num_entries = ARRAY_SIZE(fs_xe3); > + num_fs_entries = ARRAY_SIZE(fs_xe3); > fs_entries = fs_xe3; > } > > - for (int i = 0; i < num_entries; i++) { > + for (int i = 0; i < num_fs_entries; i++) { > + if (xe_wa(fd, "14026539277")) { > + igt_assert(fs_entries[i].pat_index < num_pat_entries); > + > + if (pat_sw_config.entries[fs_entries[i].pat_index].rsvd) > + continue; > + } > + > igt_dynamic_f("%s", fs_entries[i].name) { > __false_sharing(fd, &fs_entries[i]); > } > > -- > 2.55.0 >