[PATCH v2 0/2] xe/shaders: remove explicit regioning and channel offsets

[Andrzej Hajda <andrzej.hajda@intel.com>]

There is no need to specify regioning and channel offset in
most cases. Default genisa values are:
- <0;1,0> for source region,
- <1> for destination region,
- M0 for channel offset.
The patch also enforces common formating for all asms:
- preprocessor instructions and predicates start from beginning of the line,
- instruction mnemonic starts from 1st tab,
- exec size follows mnemonic after one space,
- flag modifiers, if any, are placed after exec size,
- arguments starts from 3rd tab,
- no tabs/multi-spaces between/after arguments

The changes do not affect produced binary code.

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
Changes in v2:
- split patch to lib and test parts, remove script change (Kamil)
- Link to v1: https://patch.msgid.link/20261027-remove_gpu_asm_annotations-v1-1-55a0fb61b96d@intel.com

---
Andrzej Hajda (2):
      lib/shaders: remove explicit regioning and channel offsets
      tests/intel/xe_prefetch_fault: remove explicit regioning and channel offsets

 lib/gpgpu_fill.c                                  | 104 +++++++++---------
 lib/gpgpu_fill.c.gen.iga64_codes.c                |   2 +-
 lib/gpgpu_shader.c                                | 126 +++++++++++-----------
 lib/gpgpu_shader.c.gen.iga64_codes.c              |   2 +-
 lib/iga64_macros.h                                |  70 ++++++------
 tests/intel/xe_prefetch_fault.c                   |  16 +--
 tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c |   2 +-
 7 files changed, 160 insertions(+), 162 deletions(-)
---
base-commit: fc75d6d7ffcb79e8a3316e80c7085460568a7670
change-id: 20261027-remove_gpu_asm_annotations-94b7b32841dd

Best regards,
--  
Andrzej Hajda <andrzej.hajda@intel.com>