From: Brajesh Gupta <brajesh.gupta@imgtec.com>
To: Development mailing list for IGT GPU Tools
<igt-dev@lists.freedesktop.org>
Cc: Alessio Belle <alessio.belle@imgtec.com>,
Brajesh Gupta <brajesh.gupta@imgtec.com>,
Luigi Santivetti <luigi.santivetti@imgtec.com>
Subject: [PATCH i-g-t v3 1/3] lib/igt_pvr: Update general heap allocation interface to pass flags
Date: Wed, 11 Nov 2026 10:32:21 +0530 [thread overview]
Message-ID: <20261111-b4-render_update-v3-1-979dcf01ff43@imgtec.com> (raw)
In-Reply-To: <20261111-b4-render_update-v3-0-979dcf01ff43@imgtec.com>
Update igt_pvr_allocate_general() interface to pass flags for allocation.
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Signed-off-by: Brajesh Gupta <brajesh.gupta@imgtec.com>
---
lib/igt_pvr.c | 36 ++++++++++++++++++++++++------------
lib/igt_pvr.h | 3 ++-
tests/imagination/pvr_submit_jobs.c | 13 ++++++++++---
3 files changed, 36 insertions(+), 16 deletions(-)
diff --git a/lib/igt_pvr.c b/lib/igt_pvr.c
index 799852da5..e771d0660 100644
--- a/lib/igt_pvr.c
+++ b/lib/igt_pvr.c
@@ -399,7 +399,9 @@ uint32_t igt_pvr_ioctl_create_context(int fd, enum drm_pvr_ctx_type type,
create_context_args.callstack_addr =
igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd,
vm_ctx_handle,
- POWERVR_GPU_PAGE_SIZE));
+ POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
create_context_args.static_context_state = to_user_pointer(init_render_context_stream);
create_context_args.static_context_state_len =
init_render_context_state_stream(init_render_context_stream);
@@ -673,17 +675,15 @@ struct igt_pvr_allocation *igt_pvr_allocate(int fd, uint32_t vm_ctx, size_t size
* @fd: The file descriptor of the DRM device.
* @vm_ctx: The virtual memory context.
* @size: The size of the allocation.
+ * @flags: Allocation flags.
*
* Function to allocate and map GPU memory from the general heap.
*
* Returns: Pointer to the allocation structure.
*/
-struct igt_pvr_allocation *igt_pvr_allocate_general(int fd, uint32_t vm_ctx, size_t size)
+struct igt_pvr_allocation *igt_pvr_allocate_general(int fd, uint32_t vm_ctx, size_t size, uint64_t flags)
{
- return igt_pvr_allocate(fd, vm_ctx, size,
- DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
- DRM_PVR_BO_BYPASS_DEVICE_CACHE,
- DRM_PVR_HEAP_GENERAL);
+ return igt_pvr_allocate(fd, vm_ctx, size, flags, DRM_PVR_HEAP_GENERAL);
}
/**
@@ -817,11 +817,17 @@ static void igt_pvr_create_hwrt_geom_data_args(int fd, uint32_t vm_ctx,
*geom_data_args)
{
geom_data_args->rtc_dev_addr =
- igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE));
+ igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
geom_data_args->tpc_dev_addr =
- igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE));
+ igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
geom_data_args->vheap_table_dev_addr =
- igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE));
+ igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
geom_data_args->tpc_size = POWERVR_GPU_PAGE_SIZE;
geom_data_args->tpc_stride = 0x1;
}
@@ -839,11 +845,17 @@ static void igt_pvr_create_hwrt_rt_data_args(int fd, uint32_t vm_ctx,
struct drm_pvr_create_hwrt_rt_data_args *rt_data_args)
{
rt_data_args->pm_mlist_dev_addr =
- igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE));
+ igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
rt_data_args->macrotile_array_dev_addr =
- igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE));
+ igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
rt_data_args->region_header_dev_addr =
- igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE));
+ igt_pvr_get_gpu_addr(igt_pvr_allocate_general(fd, vm_ctx, POWERVR_GPU_PAGE_SIZE,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE));
}
/**
diff --git a/lib/igt_pvr.h b/lib/igt_pvr.h
index b6e3dd676..bed02f968 100644
--- a/lib/igt_pvr.h
+++ b/lib/igt_pvr.h
@@ -67,7 +67,8 @@ struct igt_pvr_allocation *igt_pvr_allocate_addr(int fd, uint32_t vm_ctx, size_t
uint64_t flags, uint64_t gpu_addr);
struct igt_pvr_allocation *igt_pvr_allocate(int fd, uint32_t vm_ctx, size_t size, uint64_t flags,
uint32_t heap_index);
-struct igt_pvr_allocation *igt_pvr_allocate_general(int fd, uint32_t vm_ctx, size_t size);
+struct igt_pvr_allocation *igt_pvr_allocate_general(int fd, uint32_t vm_ctx, size_t size,
+ uint64_t flags);
void *igt_pvr_get_cpu_addr(int fd, struct igt_pvr_allocation *alloc);
uint64_t igt_pvr_get_gpu_addr(struct igt_pvr_allocation *alloc);
size_t igt_pvr_get_size(struct igt_pvr_allocation *alloc);
diff --git a/tests/imagination/pvr_submit_jobs.c b/tests/imagination/pvr_submit_jobs.c
index 566f9d2b2..21ccb03fd 100644
--- a/tests/imagination/pvr_submit_jobs.c
+++ b/tests/imagination/pvr_submit_jobs.c
@@ -52,7 +52,10 @@ static uint32_t init_compute_cmd_stream(int fd, uint32_t vm_ctx,
void *cdm_stream_map;
uint32_t stream_length;
- struct igt_pvr_allocation *cdm_stream_alloc = igt_pvr_allocate_general(fd, vm_ctx, 0x1000);
+ struct igt_pvr_allocation *cdm_stream_alloc =
+ igt_pvr_allocate_general(fd, vm_ctx, 0x1000,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE);
cdm_stream_gpu_addr = igt_pvr_get_gpu_addr(cdm_stream_alloc);
@@ -212,14 +215,18 @@ int igt_main()
pds_buffer_base[0x20] = pds_inst_encode_halt();
vdm_alloc =
- igt_pvr_allocate_general(fd, render_vm_ctx_handle, size);
+ igt_pvr_allocate_general(fd, render_vm_ctx_handle, size,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE);
vdm_buffer = igt_pvr_get_cpu_addr(fd, vdm_alloc);
size = PVR_BO_SIZE;
ppp_alloc =
- igt_pvr_allocate_general(fd, render_vm_ctx_handle, size);
+ igt_pvr_allocate_general(fd, render_vm_ctx_handle, size,
+ DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS |
+ DRM_PVR_BO_BYPASS_DEVICE_CACHE);
ppp_buffer_base = igt_pvr_get_cpu_addr(fd, ppp_alloc);
--
2.43.0
next prev parent reply other threads:[~2026-11-11 5:04 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-11 5:02 [PATCH i-g-t v3 0/3] imagination: Update allocation flags for buffers in submit job Brajesh Gupta
2026-11-11 5:02 ` Brajesh Gupta [this message]
2026-11-11 5:02 ` [PATCH i-g-t v3 2/3] imagination: Skip CPU access flag for a few Render related allocations Brajesh Gupta
2026-11-11 5:02 ` [PATCH i-g-t v3 3/3] lib/igt_pvr: Pass DRM_PVR_BO_PM_FW_PROTECT flag for PM MList allocation Brajesh Gupta
2026-11-11 6:26 ` ✓ Xe.CI.BAT: success for imagination: Update allocation flags for buffers in submit job (rev2) Patchwork
2026-11-11 6:47 ` ✓ i915.CI.BAT: " Patchwork
2026-11-11 11:25 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-11-11 16:52 ` ✓ i915.CI.Full: success " Patchwork
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