[PATCH i-g-t 3/5] tests/xe_pat: Add pat indices for XA App Transient in false-sharing test

priyanka.dandamudi
2026-02-13T08:46:12Z

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

Added PAT 18,19 indices to test new XA WB-App Transient where buffer is being
shared by both CPU and GPU.XA WB-App Transient is a feature where
specific l3 cache lines marked as XA WB-App Transient will get invalidated
instead of whole l3 cache when CPU wanted to access the same buffer of
GPU. These pat indices are added as part of false-sharing test.

Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
tests/intel/xe_pat.c | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
index 918f59c9e..132ac4773 100644
--- a/tests/intel/xe_pat.c
+++ b/tests/intel/xe_pat.c
@@ -1307,6 +1307,12 @@ const struct fs_pat_entry fs_xe3p_xpc[] = {
{ 4, "cpu-wb-gpu-uc-1way", DRM_XE_GEM_CPU_CACHING_WB, true },
};

+const struct fs_pat_entry fs_xe3p_lpg[] = {
+ { 2, "cpu-wb-gpu-l3-2way", DRM_XE_GEM_CPU_CACHING_WB, true },
+ { 18, "cpu-wc-gpu-xa-non-coh", DRM_XE_GEM_CPU_CACHING_WC, true },
+ { 19, "cpu-wb-gpu-xa-1way", DRM_XE_GEM_CPU_CACHING_WB, true },
+};
+
#define CPUDW_INC 0x0
#define GPUDW_WRITE 0x4
#define GPUDW_READY 0x40
@@ -1451,6 +1457,9 @@ static void false_sharing(int fd)
if (intel_graphics_ver(dev_id) == IP_VER(35, 11)) {
num_entries = ARRAY_SIZE(fs_xe3p_xpc);
fs_entries = fs_xe3p_xpc;
+ } else if (intel_graphics_ver(dev_id) == IP_VER(35, 10)) {
+ num_entries = ARRAY_SIZE(fs_xe3p_lpg);
+ fs_entries = fs_xe3p_lpg;
} else if (graphics_ver == 20) {
if (is_dgfx) {
num_entries = ARRAY_SIZE(fs_xe2_discrete);
--
2.43.0