[PATCH i-g-t 4/5] tests/intel/xe_pat: Use intel_get_defer_to_pat_mocs_index() to exercise coherency

priyanka.dandamudi
2026-02-13T08:46:13Z

From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>

With the existing moc indices the render and blit with be uncached on GPU side,
cached MOCS setting need to be selected specifically for blitter and render.
Otherwise the caching in the PAT index is overridden which means GPU vs CPU coherency
will not be exercised completely.
So, used intel_get_defer_to_pat_mocs_index() for xe2 and above versions
otherwise keep the existing UC MOCS setting.

Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
tests/intel/xe_pat.c | 27 +++++++++++++++++++++------
1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
index 132ac4773..f2dff62a9 100644
--- a/tests/intel/xe_pat.c
+++ b/tests/intel/xe_pat.c
@@ -338,9 +338,13 @@ static void pat_index_blt(struct xe_pat_param *p)
int bpp = 32;
uint32_t alias, name;
int fd = p->fd;
+ uint16_t dev_id = intel_get_drm_devid(fd);
+ uint8_t mocs_index;
int i;

igt_require(blt_has_fast_copy(fd));
+ mocs_index = intel_get_device_info(dev_id)->graphics_ver >= 20 ?
+ intel_get_defer_to_pat_mocs_index(fd) : intel_get_uc_mocs_index(fd);

vm = xe_vm_create(fd, 0, 0);
exec_queue = xe_exec_queue_create(fd, vm, &inst, 0);
@@ -364,12 +368,12 @@ static void pat_index_blt(struct xe_pat_param *p)
blt_copy_init(fd, &blt);
blt.color_depth = CD_32bit;

- blt_set_object(&src, p->r1_bo, size, p->r1, intel_get_uc_mocs_index(fd),
+ blt_set_object(&src, p->r1_bo, size, p->r1, mocs_index,
p->r1_pat_index, T_LINEAR,
COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
blt_set_geom(&src, stride, 0, 0, width, height, 0, 0);

- blt_set_object(&dst, p->r2_bo, size, p->r2, intel_get_uc_mocs_index(fd),
+ blt_set_object(&dst, p->r2_bo, size, p->r2, mocs_index,
p->r2_pat_index, T_LINEAR,
COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
blt_set_geom(&dst, stride, 0, 0, width, height, 0, 0);
@@ -448,6 +452,8 @@ static void pat_index_blt(struct xe_pat_param *p)
static void pat_index_render(struct xe_pat_param *p)
{
int fd = p->fd;
+ uint16_t dev_id = intel_get_drm_devid(fd);
+ uint8_t mocs_index;
igt_render_copyfunc_t render_copy = NULL;
int size, stride, width = p->size->width, height = p->size->height;
struct intel_buf src, dst;
@@ -463,6 +469,9 @@ static void pat_index_render(struct xe_pat_param *p)
if (p->r2_compressed) /* XXX */
return;

+ mocs_index = intel_get_device_info(dev_id)->graphics_ver >= 20 ?
+ intel_get_defer_to_pat_mocs_index(fd) : DEFAULT_MOCS_INDEX;
+
bops = buf_ops_create(fd);

ibb = intel_bb_create_full(fd, 0, 0, NULL, xe_get_default_alignment(fd),
@@ -475,11 +484,11 @@ static void pat_index_render(struct xe_pat_param *p)

intel_buf_init_full(bops, p->r1_bo, &src, width, height, bpp, 0,
I915_TILING_NONE, I915_COMPRESSION_NONE, size,
- stride, p->r1, p->r1_pat_index, DEFAULT_MOCS_INDEX);
+ stride, p->r1, p->r1_pat_index, mocs_index);

intel_buf_init_full(bops, p->r2_bo, &dst, width, height, bpp, 0,
I915_TILING_NONE, I915_COMPRESSION_NONE, size,
- stride, p->r2, p->r2_pat_index, DEFAULT_MOCS_INDEX);
+ stride, p->r2, p->r2_pat_index, mocs_index);

/* Ensure we always see zeroes for the initial KMD zeroing */
render_copy(ibb,
@@ -557,6 +566,8 @@ static void pat_index_render(struct xe_pat_param *p)
static void pat_index_dw(struct xe_pat_param *p)
{
int fd = p->fd;
+ uint16_t dev_id = intel_get_drm_devid(fd);
+ uint8_t mocs_index;
int size, stride, width = p->size->width, height = p->size->height;
struct drm_xe_engine_class_instance *hwe;
struct intel_bb *ibb;
@@ -579,6 +590,9 @@ static void pat_index_dw(struct xe_pat_param *p)
break;
}

+ mocs_index = intel_get_device_info(dev_id)->graphics_ver >= 20 ?
+ intel_get_defer_to_pat_mocs_index(fd) : DEFAULT_MOCS_INDEX;
+
vm = xe_vm_create(fd, 0, 0);
ctx = xe_exec_queue_create(fd, vm, hwe, 0);

@@ -592,12 +606,13 @@ static void pat_index_dw(struct xe_pat_param *p)

intel_buf_init_full(bops, p->r1_bo, &r1_buf, width, height, bpp, 0,
I915_TILING_NONE, I915_COMPRESSION_NONE, size,
- stride, p->r1, p->r1_pat_index, DEFAULT_MOCS_INDEX);
+ stride, p->r1, p->r1_pat_index, mocs_index);
intel_bb_add_intel_buf(ibb, &r1_buf, true);

intel_buf_init_full(bops, p->r2_bo, &r2_buf, width, height, bpp, 0,
I915_TILING_NONE, I915_COMPRESSION_NONE, size,
- stride, p->r2, p->r2_pat_index, DEFAULT_MOCS_INDEX);
+ stride, p->r2, p->r2_pat_index, mocs_index);
+
intel_bb_add_intel_buf(ibb, &r2_buf, true);

/*
--
2.43.0