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aCCwgRblvsEwzD7gkAe8Y4DKQI0EtcBx0K9qA4eMOFNbG/uL+foqOj4YiSs8r14YGgjGFzUQeTbVHzGGMYKEemMLcCcDy4dW+M6Ydm+fvBQ= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB6941 X-OriginatorOrg: intel.com X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" LGTM: Reviewed-by: Mohammed Thasleem On 27-05-2026 02:19 pm, Jeevan B wrote: > Add a new subtest to validate DC3CO counter increments across > frame gaps exceeding the threshold during a video-like workload > with PSR2/PR enabled. > > v2: Update commit message and test description. > > Signed-off-by: Jeevan B > --- > tests/intel/kms_pm_dc.c | 91 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > > diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c > index 59cb9983d..3f17effc8 100644 > --- a/tests/intel/kms_pm_dc.c > +++ b/tests/intel/kms_pm_dc.c > @@ -60,6 +60,10 @@ > * exit cycle, ensuring DC3CO is not broken by deeper power state > * transitions. > * > + * SUBTEST: dc3co-vpb-framegap > + * Description: Validate DC3CO counter increments before and after a delay greater > + * than 6 frame gaps during video-like load with PSR2 active. > + * > * SUBTEST: dc5-dpms > * Description: Validate display engine entry to DC5 state while all connectors's > * DPMS property set to OFF > @@ -427,6 +431,63 @@ static void test_dc3co_framedrop(data_t *data) > cleanup_dc3co_fbs(data); > } > > +static void check_dc3co_with_framegap_load(data_t *data) > +{ > + igt_plane_t *primary; > + uint32_t dc3co_cnt_before, dc3co_cnt_after_gap; > + int delay, long_gap_us; > + time_t secs = 3; > + time_t start_time; > + > + primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY); > + igt_plane_set_fb(primary, NULL); > + > + delay = 1.5 * ((1000 * 1000) / data->mode->vrefresh); > + > + dc3co_cnt_before = igt_read_dc_counter(data->debugfs_fd, > + IGT_INTEL_CHECK_DC3CO); > + start_time = time(NULL); > + while (time(NULL) - start_time < secs) { > + igt_plane_set_fb(primary, &data->fb_rgb); > + igt_display_commit(&data->display); > + usleep(delay); > + > + igt_plane_set_fb(primary, &data->fb_rgr); > + igt_display_commit(&data->display); > + usleep(delay); > + } > + > + assert_dc_counter(data, IGT_INTEL_CHECK_DC3CO, dc3co_cnt_before); > + > + long_gap_us = 7 * ((1000 * 1000) / data->mode->vrefresh); > + usleep(long_gap_us); > + > + dc3co_cnt_after_gap = igt_read_dc_counter(data->debugfs_fd, > + IGT_INTEL_CHECK_DC3CO); > + start_time = time(NULL); > + while (time(NULL) - start_time < secs) { > + igt_plane_set_fb(primary, &data->fb_rgb); > + igt_display_commit(&data->display); > + usleep(delay); > + > + igt_plane_set_fb(primary, &data->fb_rgr); > + igt_display_commit(&data->display); > + usleep(delay); > + } > + > + assert_dc_counter(data, IGT_INTEL_CHECK_DC3CO, dc3co_cnt_after_gap); > +} > + > +static void test_dc3co_vpb_framegap(data_t *data) > +{ > + igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO); > + setup_output(data); > + setup_dc3co(data); > + setup_videoplayback(data); > + check_dc3co_with_framegap_load(data); > + cleanup_dc3co_fbs(data); > +} > + > static void test_dc5_retention_flops(data_t *data, int dc_flag) > { > uint32_t dc_counter_before_psr; > @@ -854,6 +915,36 @@ int igt_main() > } > } > > + igt_describe("Validate DC3CO counter increments before and after a delay " > + "greater than 6 frame gaps during video-like load with PSR2/PR active"); > + igt_subtest_with_dynamic("dc3co-vpb-framegap") { > + static const struct dc3co_test_mode dc3co_modes[] = { > + { PSR_MODE_2, "psr2" }, > + { PR_MODE, "pr" }, > + }; > + > + for (int i = 0; i < ARRAY_SIZE(dc3co_modes); i++) { > + const char *name = dc3co_modes[i].name; > + data.op_psr_mode = dc3co_modes[i].mode; > + > + igt_dynamic_f("%s", name) { > + igt_require(psr_sink_support(data.drm_fd, > + data.debugfs_fd, > + data.op_psr_mode, NULL)); > + > + if (data.op_psr_mode == PSR_MODE_2) > + igt_require_f(IS_TIGERLAKE(data.devid) || > + intel_display_ver(data.devid) >= 35, > + "Platform does not support DC3CO with PSR2\n"); > + else > + igt_require_f(intel_display_ver(data.devid) >= 35, > + "Platform does not support DC3CO with Panel Replay\n"); > + > + test_dc3co_vpb_framegap(&data); > + } > + } > + } > + > igt_describe("This test validates display engine entry to DC5 state " > "while PSR is active"); > igt_subtest("dc5-psr") {