Re: [PATCH v2 2/2] tests/intel/xe_pat: sync with Xe PAT debugfs parser

[Matthew Auld <matthew.auld@intel.com>]

On 06/12/2025 01:12, Xin Wang wrote:
> Pull in the Xe PAT table parsed by lib/intel_pat so Gen20+ tests

Nit: s/Gen20/graphics vesion 20+/ or just xe2+. We stopped using the 
"gen" terminology on modern hw, and moved to the ip version stuff.

> use the driver-provided entries instead of hard-coded reservations.
> 
> CC: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> ---
>   tests/intel/xe_pat.c | 38 ++++++++++++++++++++++++++++++++++++--
>   1 file changed, 36 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index 59dfb6b11..b911e9cbf 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -77,6 +77,18 @@ static void userptr_coh_none(int fd)
>   	xe_vm_destroy(fd, vm);
>   }
>   
> +#define BITS_TO(n)		(n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
> +#define BITMASK(high, low)	(uint32_t)(BITS_TO(high+1) & ~BITS_TO(low))
> +#define FIELD_GET(val, high, low)	(((val) & (BITMASK(high, low))) >> (low))
> +#define FIELD_GET_BIT(val, n)		FIELD_GET(val, n, n)
> +
> +#define XE_NO_PROMOTE(val)	FIELD_GET_BIT(val, 10)
> +#define XE_COMP_EN(val)		FIELD_GET_BIT(val, 9)
> +#define XE_L3_CLOS(val)		FIELD_GET(val, 7, 6)
> +#define XE_L3_POLICY(val)	FIELD_GET(val, 5, 4)
> +#define XE_L4_POLICY(val)	FIELD_GET(val, 3, 2)
> +#define XE_COH_MODE(val)	FIELD_GET(val, 1, 0)
> +
>   /**
>    * SUBTEST: pat-index-all
>    * Test category: functionality test
> @@ -86,6 +98,7 @@ static void pat_index_all(int fd)
>   {
>   	uint16_t dev_id = intel_get_drm_devid(fd);
>   	size_t size = xe_get_default_alignment(fd);
> +	struct xe_pat_entry xe_pat_table[XE_PAT_MAX_ENTRIES] = {0};
>   	uint32_t vm, bo;
>   	uint8_t pat_index;
>   
> @@ -114,10 +127,31 @@ static void pat_index_all(int fd)
>   
>   	igt_assert(intel_get_max_pat_index(fd));
>   
> +	if (intel_gen(dev_id) >= 20) {

s/intel_gen/intel_graphics_ver/

> +		/* Get the Xe PAT entries from debugfs */
> +		uint8_t pat_entries = xe_get_pat_entries(fd, xe_pat_table);
> +
> +		for (int i = 0; i < pat_entries; i++) {
> +			uint32_t pat = xe_pat_table[i].pat;
> +			igt_debug("PAT[%2d] = [ %u, %u, %u, %u, %u, %u]  (%#8x)%s\n", i,
> +				  XE_NO_PROMOTE(pat),
> +				  XE_COMP_EN(pat),
> +				  XE_L3_CLOS(pat),
> +				  XE_L3_POLICY(pat),
> +				  XE_L4_POLICY(pat),
> +				  XE_COH_MODE(pat),
> +				  pat,
> +				  xe_pat_table[i].rsvd ? " *" : "");
> +		}
> +	}
> +
>   	for (pat_index = 0; pat_index <= intel_get_max_pat_index(fd);
>   	     pat_index++) {
> -		if (intel_get_device_info(dev_id)->graphics_ver >= 20 &&
> -		    pat_index >= 16 && pat_index <= 19) { /* hw reserved */
> +
> +		bool hw_reserved = intel_gen(dev_id) >= 20 ?

intel_graphics_ver

Otherwise lgtm. This should make things easier to maintain going 
forward. Thanks for working on this,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> +			      xe_pat_table[pat_index].rsvd : false;
> +
> +		if (hw_reserved) {
>   			igt_assert_eq(__xe_vm_bind(fd, vm, 0, bo, 0, 0x40000,
>   						   size, DRM_XE_VM_BIND_OP_MAP, 0, NULL, 0, 0,
>   						   pat_index, 0),