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Thu, 16 May 2024 09:11:36 +0000 Message-ID: <3f4e5dbe-794b-46f1-8972-3a8644097b3b@amd.com> Date: Thu, 16 May 2024 14:41:28 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH i-g-t 1/2] tests/amdgpu: support jpeg test on gfx940 To: Kamil Konieczny , igt-dev@lists.freedesktop.org, Sathishkumar S , Leo Liu References: <20240513135705.2399645-1-sathishkumar.sundararaju@amd.com> <20240515171632.6qavel4ojvvtwcck@kamilkon-DESK.igk.intel.com> Content-Language: en-US From: "Sundararaju, Sathishkumar" In-Reply-To: <20240515171632.6qavel4ojvvtwcck@kamilkon-DESK.igk.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: MAXP287CA0017.INDP287.PROD.OUTLOOK.COM (2603:1096:a00:49::35) To MN0PR12MB6293.namprd12.prod.outlook.com (2603:10b6:208:3c2::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN0PR12MB6293:EE_|LV3PR12MB9233:EE_ X-MS-Office365-Filtering-Correlation-Id: e63579c9-9bf5-4517-553a-08dc7588300e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|366007|1800799015|376005; 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No need for resend, > this can be corrected at merge. Noted, I will update this, thank you. Regards, Sathish > > Regards, > Kamil > >> Signed-off-by: Sathishkumar S >> Acked-by: Leo Liu >> --- >> tests/amdgpu/amd_jpeg_dec.c | 167 +++++++++++++++++++++++++++--------- >> 1 file changed, 127 insertions(+), 40 deletions(-) >> >> diff --git a/tests/amdgpu/amd_jpeg_dec.c b/tests/amdgpu/amd_jpeg_dec.c >> index bb2a8e97e530..12f5bfcff556 100644 >> --- a/tests/amdgpu/amd_jpeg_dec.c >> +++ b/tests/amdgpu/amd_jpeg_dec.c >> @@ -53,6 +53,47 @@ >> #define vcnipUVD_JPEG_RB_RPTR 0x4003 >> #define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d >> >> +#define vcnipUVD_JPEG_DEC_SOFT_RST_1 0x4051 >> +#define vcnipUVD_JPEG_PITCH_1 0x4043 >> +#define vcnipUVD_JPEG_UV_PITCH_1 0x4044 >> +#define vcnipJPEG_DEC_ADDR_MODE_1 0x404B >> +#define vcnipUVD_JPEG_TIER_CNTL2_1 0x400E >> +#define vcnipUVD_JPEG_OUTBUF_CNTL_1 0x4040 >> +#define vcnipUVD_JPEG_OUTBUF_WPTR_1 0x4041 >> +#define vcnipUVD_JPEG_OUTBUF_RPTR_1 0x4042 >> +#define vcnipUVD_JPEG_LUMA_BASE0_0 0x41C0 >> +#define vcnipUVD_JPEG_CHROMA_BASE0_0 0x41C1 >> +#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1 0x4048 >> +#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1 0x4049 >> +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1 0x40B5 >> +#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1 0x40B4 >> +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1 0x40B3 >> +#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1 0x40B2 >> + >> +static uint32_t jpeg_dec_soft_rst; >> +static uint32_t jrbc_ib_cond_rd_timer; >> +static uint32_t jrbc_ib_ref_data; >> +static uint32_t lmi_jpeg_read_64bit_bar_high; >> +static uint32_t lmi_jpeg_read_64bit_bar_low; >> +static uint32_t jpeg_rb_base; >> +static uint32_t jpeg_rb_size; >> +static uint32_t jpeg_rb_wptr; >> +static uint32_t jpeg_pitch; >> +static uint32_t jpeg_uv_pitch; >> +static uint32_t dec_addr_mode; >> +static uint32_t dec_y_gfx10_tiling_surface; >> +static uint32_t dec_uv_gfx10_tiling_surface; >> +static uint32_t lmi_jpeg_write_64bit_bar_high; >> +static uint32_t lmi_jpeg_write_64bit_bar_low; >> +static uint32_t jpeg_tier_cntl2; >> +static uint32_t jpeg_outbuf_rptr; >> +static uint32_t jpeg_outbuf_cntl; >> +static uint32_t jpeg_int_en; >> +static uint32_t jpeg_cntl; >> +static uint32_t jpeg_rb_rptr; >> +static uint32_t jpeg_outbuf_wptr; >> +static uint32_t jpeg_luma_base0_0; >> +static uint32_t jpeg_chroma_base0_0; >> >> #define RDECODE_PKT_REG_J(x) ((unsigned int)(x)&0x3FFFF) >> #define RDECODE_PKT_RES_J(x) (((unsigned int)(x)&0x3F) << 18) >> @@ -104,6 +145,50 @@ is_jpeg_tests_enable(amdgpu_device_handle device_handle, >> else >> return false; >> >> + jrbc_ib_cond_rd_timer = vcnipUVD_JRBC_IB_COND_RD_TIMER; >> + jrbc_ib_ref_data = vcnipUVD_JRBC_IB_REF_DATA; >> + jpeg_rb_base = vcnipUVD_JPEG_RB_BASE; >> + jpeg_rb_size = vcnipUVD_JPEG_RB_SIZE; >> + jpeg_rb_wptr = vcnipUVD_JPEG_RB_WPTR; >> + jpeg_int_en = vcnipUVD_JPEG_INT_EN; >> + jpeg_cntl = vcnipUVD_JPEG_CNTL; >> + jpeg_rb_rptr = vcnipUVD_JPEG_RB_RPTR; >> + >> + if (context->family_id == AMDGPU_FAMILY_AI && >> + (context->chip_id - context->chip_rev) > 0x3c) { /* gfx940 */ >> + jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST_1; >> + lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1; >> + lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1; >> + jpeg_pitch = vcnipUVD_JPEG_PITCH_1; >> + jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH_1; >> + dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE_1; >> + dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1; >> + dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1; >> + lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1; >> + lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1; >> + jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2_1; >> + jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL_1; >> + jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR_1; >> + jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR_1; >> + jpeg_luma_base0_0 = vcnipUVD_JPEG_LUMA_BASE0_0; >> + jpeg_chroma_base0_0 = vcnipUVD_JPEG_CHROMA_BASE0_0; >> + } else { >> + jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST; >> + lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH; >> + lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW; >> + jpeg_pitch = vcnipUVD_JPEG_PITCH; >> + jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH; >> + dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE; >> + dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE; >> + dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE; >> + lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH; >> + lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW; >> + jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2; >> + jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL; >> + jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR; >> + jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR; >> + } >> + >> return true; >> } >> >> @@ -277,39 +362,34 @@ send_cmd_bitstream_direct(struct mmd_context *context, uint64_t addr, >> { >> >> /* jpeg soft reset */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1, idx); >> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 1, idx); >> >> /* ensuring the Reset is asserted in SCLK domain */ >> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, >> - 0x01400200, idx); >> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, >> - (0x1 << 0x10), idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, >> - (0x1 << 0x10), idx); >> + set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200, idx); >> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10), idx); >> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx); >> >> /* wait mem */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0, idx); >> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND0, TYPE0, 0, idx); >> >> /* ensuring the Reset is de-asserted in SCLK domain */ >> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10), >> - idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, >> - (0x1 << 0x10), idx); >> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10), idx); >> + set_reg_jpeg(context, jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10), idx); >> >> /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ >> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, >> + set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_high, COND0, TYPE0, >> (addr >> 32), idx); >> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, >> + set_reg_jpeg(context, lmi_jpeg_read_64bit_bar_low, COND0, TYPE0, >> addr, idx); >> >> /* set jpeg_rb_base */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0, idx); >> + set_reg_jpeg(context, jpeg_rb_base, COND0, TYPE0, 0, idx); >> >> /* set jpeg_rb_base */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0, idx); >> + set_reg_jpeg(context, jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0, idx); >> >> /* set jpeg_rb_wptr */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, >> + set_reg_jpeg(context, jpeg_rb_wptr, COND0, TYPE0, >> (JPEG_DEC_BSD_SIZE >> 2), idx); >> } >> >> @@ -319,59 +399,66 @@ send_cmd_target_direct(struct mmd_context *context, uint64_t addr, >> uint32_t *idx) >> { >> >> - set_reg_jpeg(context, vcnipUVD_JPEG_PITCH, COND0, TYPE0, >> + set_reg_jpeg(context, jpeg_pitch, COND0, TYPE0, >> (JPEG_DEC_DT_PITCH >> 4), idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, >> + set_reg_jpeg(context, jpeg_uv_pitch, COND0, TYPE0, >> (JPEG_DEC_DT_PITCH >> 4), idx); >> >> - set_reg_jpeg(context, vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0, idx); >> - set_reg_jpeg(context, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, >> + set_reg_jpeg(context, dec_addr_mode, COND0, TYPE0, 0, idx); >> + set_reg_jpeg(context, dec_y_gfx10_tiling_surface, COND0, TYPE0, >> 0, idx); >> - set_reg_jpeg(context, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, >> + set_reg_jpeg(context, dec_uv_gfx10_tiling_surface, COND0, TYPE0, >> 0, idx); >> >> /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ >> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, >> + set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_high, COND0, TYPE0, >> (addr >> 32), idx); >> - set_reg_jpeg(context, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, >> + set_reg_jpeg(context, lmi_jpeg_write_64bit_bar_low, COND0, TYPE0, >> addr, idx); >> >> /* set output buffer data address */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET, >> - idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, >> + if (jpeg_luma_base0_0) { >> + set_reg_jpeg(context, jpeg_luma_base0_0, COND0, TYPE0, >> + JPEG_DEC_LUMA_OFFSET, idx); >> + set_reg_jpeg(context, jpeg_chroma_base0_0, COND0, TYPE0, >> JPEG_DEC_CHROMA_OFFSET, idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0, idx); >> + } else { >> + set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0, idx); >> + set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, >> + JPEG_DEC_LUMA_OFFSET, idx); >> + set_reg_jpeg(context, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1, idx); >> + set_reg_jpeg(context, vcnipUVD_JPEG_DATA, COND0, TYPE0, >> + JPEG_DEC_CHROMA_OFFSET, idx); >> + } >> + set_reg_jpeg(context, jpeg_tier_cntl2, COND0, 0, 0, idx); >> >> /* set output buffer read pointer */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0, idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0, >> + set_reg_jpeg(context, jpeg_outbuf_rptr, COND0, TYPE0, 0, idx); >> + set_reg_jpeg(context, jpeg_outbuf_cntl, COND0, TYPE0, >> ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)), >> idx); >> >> /* enable error interrupts */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE, idx); >> + set_reg_jpeg(context, jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE, idx); >> >> /* start engine command */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE, idx); >> + set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0xE, idx); >> >> /* wait for job completion, wait for job JBSI fetch done */ >> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, >> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, >> (JPEG_DEC_BSD_SIZE >> 2), idx); >> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, >> + set_reg_jpeg(context, jrbc_ib_cond_rd_timer, COND0, TYPE0, >> 0x01400200, idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF, idx); >> + set_reg_jpeg(context, jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF, idx); >> >> /* wait for job jpeg outbuf idle */ >> - set_reg_jpeg(context, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF, >> + set_reg_jpeg(context, jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF, >> idx); >> - set_reg_jpeg(context, vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001, >> + set_reg_jpeg(context, jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001, >> idx); >> >> /* stop engine */ >> - set_reg_jpeg(context, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4, idx); >> + set_reg_jpeg(context, jpeg_cntl, COND0, TYPE0, 0x4, idx); >> } >> >> static void >> -- >> 2.25.1 >>