From: Matthew Auld <matthew.auld@intel.com>
To: priyanka.dandamudi@intel.com, zbigniew.kempczynski@intel.com,
igt-dev@lists.freedesktop.org
Subject: Re: [PATCH i-g-t 5/5] tests/intel/xe_pat: Validate XA App Transient feature
Date: Tue, 3 Mar 2026 10:37:38 +0000 [thread overview]
Message-ID: <4524e97d-4da5-4776-a877-493ca023c801@intel.com> (raw)
In-Reply-To: <20260303043853.1656156-6-priyanka.dandamudi@intel.com>
On 03/03/2026 04:38, priyanka.dandamudi@intel.com wrote:
> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>
> Test the scenarios when media is on/off.
> When media is off/on, for xa app transient buffer, data should be coherent
> between cpu and gpu. Coherency should be maintained from KMD side
> irrespective of media engine on/off.
>
> v2: Added comment to explain the reason of forcewaking.
> Added 2way also in the index along with XA.(Matt)
> Reordered headers.(Kamil)
>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> ---
> tests/intel/xe_pat.c | 103 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 103 insertions(+)
>
> diff --git a/tests/intel/xe_pat.c b/tests/intel/xe_pat.c
> index aeb84dbb7..dbeb7c7d9 100644
> --- a/tests/intel/xe_pat.c
> +++ b/tests/intel/xe_pat.c
> @@ -16,11 +16,17 @@
> #include "igt.h"
> #include "igt_syncobj.h"
> #include "igt_vgem.h"
> +#include "igt_configfs.h"
> +#include "igt_device.h"
> +#include "igt_fs.h"
> +#include "igt_kmod.h"
> +#include "igt_sysfs.h"
> #include "intel_blt.h"
> #include "intel_mocs.h"
> #include "intel_pat.h"
> #include "linux_scaffold.h"
>
> +#include "xe/xe_gt.h"
> #include "xe/xe_ioctl.h"
> #include "xe/xe_query.h"
> #include "xe/xe_util.h"
> @@ -29,6 +35,8 @@
> #define XE_COH_AT_LEAST_1WAY 2
>
> static bool do_slow_check;
> +static char bus_addr[NAME_MAX];
> +static struct pci_device *pci_dev;
>
> static uint32_t create_object(int fd, int r, int size, uint16_t coh_mode,
> bool force_cpu_wc);
> @@ -1184,6 +1192,12 @@ const struct pat_index_entry bmg_g21_pat_index_modes[] = {
> { NULL, 27, false, "c2-2way", XE_COH_AT_LEAST_1WAY },
> };
>
> +const struct pat_index_entry xe3p_lpg_coherency_pat_index_modes[] = {
> + { NULL, 18, false, "xa-l3-uc", XE_COH_NONE },
> + { NULL, 19, false, "xa-l3-2way", XE_COH_AT_LEAST_1WAY },
Nit: there is no 2way+xa, so the string here is not really accurate.
> + { NULL, 2, false, "2way", XE_COH_AT_LEAST_1WAY },
> +};
> +
> /*
> * Depending on 2M/1G GTT pages we might trigger different PTE layouts for the
> * PAT bits, so make sure we test with and without huge-pages. Also ensure we
> @@ -1248,6 +1262,18 @@ static uint32_t create_object(int fd, int r, int size, uint16_t coh_mode,
> * Description: Check some of the xe2 pat_index modes.
> */
>
> +/**
> + * SUBTEST: xa-app-transient-media-off
> + * Test category: functionality test
> + * Description: Check some of the xe4-lpg pat_index modes with media off.
> + */
> +
> +/**
> + * SUBTEST: xa-app-transient-media-on
> + * Test category: functionality test
> + * Description: Check some of the xe3p-lpg pat_index modes with media on.
> + */
> +
> static void subtest_pat_index_modes_with_regions(int fd,
> const struct pat_index_entry *modes_arr,
> int n_modes)
> @@ -1561,6 +1587,53 @@ static void false_sharing(int fd)
> }
> }
>
> +static void reset(int sig)
> +{
> + int configfs_fd;
> +
> + igt_kmod_unbind("xe", bus_addr);
> +
> + /* Drop all custom configfs settings from subtests */
> + configfs_fd = igt_configfs_open("xe");
> + if (configfs_fd >= 0)
> + igt_fs_remove_dir(configfs_fd, bus_addr);
> + close(configfs_fd);
> +
> + /* Bind again a clean driver with no custom settings */
> + igt_kmod_bind("xe", bus_addr);
> +}
> +
> +static void xa_app_transient_test(int configfs_device_fd, bool media_on)
> +{
> + int fd, fw_handle, gt;
> +
> + igt_kmod_unbind("xe", bus_addr);
> +
> + if (media_on)
> + igt_assert(igt_sysfs_set(configfs_device_fd,
> + "gt_types_allowed", "primary,media"));
> + else
> + igt_assert(igt_sysfs_set(configfs_device_fd,
> + "gt_types_allowed", "primary"));
> +
> + igt_kmod_bind("xe", bus_addr);
> +
> + fd = drm_open_driver(DRIVER_XE);
> +
> + /* To prevent entering into rc6 for the duration of test. */
"Prevent entering C6 for the duration of the test, since this can result
in randomly flushing the entire device side caches, invalidating our XA
testing."
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
But please do keep an eye on:
https://patchwork.freedesktop.org/patch/708272/?series=158017&rev=6
Anything which claims to be rejected by uAPI we will want a negative test.
> + fw_handle = igt_debugfs_open(fd, "forcewake_all", O_RDONLY);
> + igt_require(fw_handle >= 0);
> +
> + subtest_pat_index_modes_with_regions(fd, xe3p_lpg_coherency_pat_index_modes,
> + ARRAY_SIZE(xe3p_lpg_coherency_pat_index_modes));
> +
> + /* check status of c state, it should not be in c6 due to forcewake. */
> + xe_for_each_gt(fd, gt)
> + igt_assert(!xe_gt_is_in_c6(fd, gt));
> +
> + close(fw_handle);
> +}
> +
> static int opt_handler(int opt, int opt_index, void *data)
> {
> switch (opt) {
> @@ -1652,6 +1725,36 @@ int igt_main_args("V", NULL, help_str, opt_handler, NULL)
> false_sharing(fd);
> }
>
> + igt_subtest_group() {
> + int configfs_fd, configfs_device_fd;
> +
> + igt_fixture() {
> + igt_require(intel_graphics_ver(dev_id) == IP_VER(35, 10));
> +
> + pci_dev = igt_device_get_pci_device(fd);
> + snprintf(bus_addr, sizeof(bus_addr), "%04x:%02x:%02x.%01x",
> + pci_dev->domain, pci_dev->bus, pci_dev->dev, pci_dev->func);
> +
> + configfs_fd = igt_configfs_open("xe");
> + igt_require(configfs_fd != -1);
> + configfs_device_fd = igt_fs_create_dir(configfs_fd, bus_addr,
> + S_IRWXU | S_IRGRP | S_IXGRP |
> + S_IROTH | S_IXOTH);
> + igt_install_exit_handler(reset);
> + }
> +
> + igt_subtest_with_dynamic("xa-app-transient-media-off")
> + xa_app_transient_test(configfs_device_fd, false);
> +
> + igt_subtest_with_dynamic("xa-app-transient-media-on")
> + xa_app_transient_test(configfs_device_fd, true);
> +
> + igt_fixture() {
> + close(configfs_device_fd);
> + close(configfs_fd);
> + }
> + }
> +
> igt_fixture()
> drm_close_driver(fd);
> }
next prev parent reply other threads:[~2026-03-03 10:37 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-03 4:38 [PATCH i-g-t 0/5] Add false sharing and XA app transient tests priyanka.dandamudi
2026-03-03 4:38 ` [PATCH i-g-t 1/5] tests/xe_pat: Add false-sharing subtest priyanka.dandamudi
2026-03-03 4:38 ` [PATCH i-g-t 2/5] tests/xe_pat: Handle false-sharing on Xe3 priyanka.dandamudi
2026-03-03 4:38 ` [PATCH i-g-t 3/5] tests/xe_pat: Add pat indices for XA App Transient in false-sharing test priyanka.dandamudi
2026-03-03 4:38 ` [PATCH i-g-t 4/5] tests/intel/xe_pat: Use intel_get_defer_to_pat_mocs_index() to exercise coherency priyanka.dandamudi
2026-03-03 4:38 ` [PATCH i-g-t 5/5] tests/intel/xe_pat: Validate XA App Transient feature priyanka.dandamudi
2026-03-03 10:37 ` Matthew Auld [this message]
2026-03-03 13:10 ` Dandamudi, Priyanka
2026-03-04 11:45 ` Kamil Konieczny
2026-03-03 23:00 ` ✓ Xe.CI.BAT: success for Add false sharing and XA app transient tests (rev2) Patchwork
2026-03-03 23:20 ` ✓ i915.CI.BAT: " Patchwork
2026-03-04 12:33 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-04 15:03 ` ✗ i915.CI.Full: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2026-03-06 4:17 [PATCH i-g-t 0/5] Add false sharing and XA app transient tests priyanka.dandamudi
2026-03-06 4:17 ` [PATCH i-g-t 5/5] tests/intel/xe_pat: Validate XA App Transient feature priyanka.dandamudi
2026-02-13 8:45 [PATCH i-g-t 0/5] Add false sharing and XA app transient tests priyanka.dandamudi
2026-02-13 8:46 ` [PATCH i-g-t 5/5] tests/intel/xe_pat: Validate XA App Transient feature priyanka.dandamudi
2026-02-17 12:30 ` Matthew Auld
2026-02-26 4:56 ` Dandamudi, Priyanka
2026-02-26 11:28 ` Matthew Auld
2026-02-26 4:59 ` Dandamudi, Priyanka
2026-02-18 11:09 ` Kamil Konieczny
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