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d="scan'208";a="67809385" Received: from nirmoyda-mobl.ger.corp.intel.com (HELO [10.245.192.32]) ([10.245.192.32]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2024 09:12:51 -0700 Message-ID: <45e3b3d6-66b9-4ed6-8241-91cc24e0a559@linux.intel.com> Date: Tue, 27 Aug 2024 18:12:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH i-g-t] tests/intel/xe_exec_fault_mode: Don't return early To: Matthew Brost , Nirmoy Das Cc: igt-dev@lists.freedesktop.org, kamil.konieczny@linux.intel.com, Andrzej Hajda , Tejas Upadhyay References: <20240827105222.13650-1-nirmoy.das@intel.com> Content-Language: en-US From: Nirmoy Das In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On 8/27/2024 5:52 PM, Matthew Brost wrote: > On Tue, Aug 27, 2024 at 12:52:22PM +0200, Nirmoy Das wrote: >> Tests that are causing pagefaults should wait for exec queue to be ban >> otherwise pending engine resets because of on-going pagefaults would >> cause failure in subsequent tests to fail. >> >> Cc: Andrzej Hajda >> Cc: Matthew Brost > Reviewed-by: Matthew Brost Hi Matt, have sent a v2, with few minor suggestion Andrzej, could you please review that https://patchwork.freedesktop.org/patch/610883/?series=137836&rev=2 Regards, Nirmoy > >> Cc: Tejas Upadhyay >> Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1630 >> Signed-off-by: Nirmoy Das >> --- >> tests/intel/xe_exec_fault_mode.c | 27 +++++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/tests/intel/xe_exec_fault_mode.c b/tests/intel/xe_exec_fault_mode.c >> index 1f1f1e50b..339c79353 100644 >> --- a/tests/intel/xe_exec_fault_mode.c >> +++ b/tests/intel/xe_exec_fault_mode.c >> @@ -36,6 +36,22 @@ >> #define INVALID_VA (0x1 << 8) >> #define ENABLE_SCRATCH (0x1 << 9) >> >> +static int get_ban_property(int xe, struct drm_xe_engine_class_instance *eci, >> + uint32_t vm, uint32_t exec_queue) >> +{ >> + struct drm_xe_exec_queue_get_property args = { >> + .value = -1, >> + .reserved[0] = 0, >> + .property = DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN, >> + }; >> + >> + args.exec_queue_id = exec_queue; >> + >> + do_ioctl(xe, DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY, &args); >> + >> + return args.value; >> +} >> + >> /** >> * SUBTEST: invalid-va >> * Description: Access invalid va and check for EIO through user fence. >> @@ -324,6 +340,17 @@ test_exec(int fd, struct drm_xe_engine_class_instance *eci, >> xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, >> bind_exec_queues[0], NSEC_PER_SEC); >> >> + if ((flags & INVALID_FAULT)) { >> + igt_set_timeout(1, ""); >> + for (i = 0; i < n_execs; i++) { >> + int e = i % n_exec_queues; >> + while (!get_ban_property(fd, eci, vm, >> + exec_queues[e])) >> + sched_yield(); >> + } >> + igt_reset_timeout(); >> + } >> + >> if (!(flags & INVALID_FAULT) && !(flags & INVALID_VA)) { >> for (i = j; i < n_execs; i++) >> igt_assert_eq(data[i].data, 0xc0ffee); >> -- >> 2.42.0 >>