From: "Naladala, Ramanaidu" <Ramanaidu.naladala@intel.com>
To: Jeevan B <jeevan.b@intel.com>, <igt-dev@lists.freedesktop.org>
Cc: <animesh.manna@intel.com>,
<dibin.moolakadan.subrahmanian@intel.com>,
<mohammed.thasleem@intel.com>
Subject: Re: [PATCH i-g-t v4 6/7] tests/intel/kms_pm_dc: Add new test for DC3CO recovery after DC6
Date: Wed, 13 May 2026 13:57:02 +0530 [thread overview]
Message-ID: <53c51d4f-7a8a-421f-80a4-45cb7a3efcd3@intel.com> (raw)
In-Reply-To: <20260511171820.461666-7-jeevan.b@intel.com>
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Hi Jeevan,
On 5/11/2026 10:48 PM, Jeevan B wrote:
> Adds a test to verify DC3CO continues to function properly
> after a DC6 power cycle.
>
> Signed-off-by: Jeevan B<jeevan.b@intel.com>
> ---
> tests/intel/kms_pm_dc.c | 65 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
> index 22ae51b51..6d2bd0ee1 100644
> --- a/tests/intel/kms_pm_dc.c
> +++ b/tests/intel/kms_pm_dc.c
> @@ -55,6 +55,11 @@
> * Description: Verify that DC3CO entry does not cause frame drops and successfully
> * enters the power state
> *
> + * SUBTEST: dc3co-after-dc6
> + * Description: Verify DC3CO entry is still functional after a DC6 entry and
> + * exit cycle, ensuring DC3CO is not broken by deeper power state
> + * transitions.
> + *
> * SUBTEST: dc5-dpms
> * Description: Validate display engine entry to DC5 state while all connectors's
> * DPMS property set to OFF
> @@ -629,6 +634,42 @@ static int has_panels_without_dc_support(igt_display_t *display)
> return external_panel;
> }
>
> +static void test_dc3co_after_dc6(data_t *data, enum psr_mode mode)
> +{
> + uint32_t dc6_prev_cnt;
> +
> + igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
> + igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC6);
> +
> + setup_output(data);
> +
> + /* Enable PSR2/PR */
> + data->op_psr_mode = mode;
This needs to be above setup_output(data);
> + psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, NULL);
> + igt_require_f(psr_wait_entry(data->debugfs_fd, data->op_psr_mode, NULL),
> + "%s is not enabled\n",
> + mode == PSR_MODE_2 ? "PSR2" : "Panel Replay");
> +
> + /* Trigger a DC6 cycle */
> + dc6_prev_cnt = igt_read_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC6);
> + setup_dc_dpms(data);
> + dpms_off(data);
> + assert_dc_counter(data, IGT_INTEL_CHECK_DC6, dc6_prev_cnt);
> + dpms_on(data);
> + cleanup_dc_dpms(data);
This dpms and DC6 cycle you can use existing function test_dc_state_dpms().
> +
> + /* Re-enable PSR2/PR after DC6 exit */
> + psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, NULL);
Is psr not restored after dpms. If it restore automatically this is not
required.
> + igt_require_f(psr_wait_entry(data->debugfs_fd, data->op_psr_mode, NULL),
> + "%s not re-enabled after DC6 exit\n",
> + mode == PSR_MODE_2 ? "PSR2" : "Panel Replay");
> +
> + /* Verify DC3CO still works after DC6 */
> + setup_videoplayback(data);
> + check_dc3co_with_videoplayback_like_load(data);
> + cleanup_dc3co_fbs(data);
> +}
> +
> static void test_deep_pkgc_state(data_t *data)
> {
> unsigned int pre_val = 0, cur_val = 0;
> @@ -799,6 +840,30 @@ int igt_main()
> }
> }
>
> + igt_describe("Verify DC3CO entry is still functional after a DC6 entry "
> + "and exit cycle");
> + igt_subtest_with_dynamic("dc3co-after-dc6") {
> + igt_dynamic("psr2") {
> + igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
> + PSR_MODE_2, NULL));
> + igt_require_f(IS_TIGERLAKE(data.devid) ||
> + intel_display_ver(data.devid) >= 35,
> + "Platform does not support DC3CO with PSR2\n");
> + igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
> + "PC8+ residencies not supported\n");
> + test_dc3co_after_dc6(&data, PSR_MODE_2);
> + }
> + igt_dynamic("pr") {
> + igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
> + PR_MODE, NULL));
> + igt_require_f(intel_display_ver(data.devid) >= 35,
> + "Platform does not support DC3CO with Panel Replay\n");
> + igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
> + "PC8+ residencies not supported\n");
> + test_dc3co_after_dc6(&data, PR_MODE);
> + }
> + }
> +
> igt_describe("This test validates display engine entry to DC5 state "
> "while PSR is active");
> igt_subtest("dc5-psr") {
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next prev parent reply other threads:[~2026-05-13 8:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 17:18 [PATCH i-g-t v4 0/7] Enable and Add new tests for DC3CO Jeevan B
2026-05-11 17:18 ` [PATCH i-g-t v4 1/7] tests: s/check_dc_counter/assert_dc_counter Jeevan B
2026-05-11 17:18 ` [PATCH i-g-t v4 2/7] tests/intel/kms_pm_dc: Replace require with proper assertion Jeevan B
2026-05-11 17:18 ` [PATCH i-g-t v4 3/7] tests/intel/kms_pm_dc: Enable DC3CO test for PSR2/PR modes Jeevan B
2026-05-12 6:18 ` Naladala, Ramanaidu
2026-05-11 17:18 ` [PATCH i-g-t v4 4/7] tests/kms_vrr: Add new test for DC3CO validation with LOBF Jeevan B
2026-05-13 6:11 ` Naladala, Ramanaidu
2026-05-11 17:18 ` [PATCH i-g-t v4 5/7] tests/intel/kms_pm_dc: Add new test for dc3co framedrop validation Jeevan B
2026-05-11 17:18 ` [PATCH i-g-t v4 6/7] tests/intel/kms_pm_dc: Add new test for DC3CO recovery after DC6 Jeevan B
2026-05-13 8:27 ` Naladala, Ramanaidu [this message]
2026-05-11 17:18 ` [PATCH i-g-t v4 7/7] tests/intel/kms_pm_dc: Add dc3co-vpb-framegap subtest Jeevan B
2026-05-13 8:06 ` Naladala, Ramanaidu
2026-05-15 15:29 ` B, Jeevan
2026-05-12 4:32 ` ✓ i915.CI.BAT: success for Enable and Add new tests for DC3CO (rev5) Patchwork
2026-05-12 5:58 ` ✓ Xe.CI.BAT: " Patchwork
2026-05-12 12:07 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-05-12 18:14 ` ✗ i915.CI.Full: " Patchwork
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