From: Matthew Auld <matthew.auld@intel.com>
To: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t v3 10/12] lib/xe_ioctl: update vm_bind to account for pat_index
Date: Tue, 17 Oct 2023 12:08:49 +0100 [thread overview]
Message-ID: <67b3af34-e7d1-095e-7d5a-961542c3f84e@intel.com> (raw)
In-Reply-To: <ZS29S3jpxlzSTCN1@nvishwa1-DESK>
On 16/10/2023 23:46, Niranjana Vishwanathapura wrote:
> On Mon, Oct 16, 2023 at 03:14:48PM +0100, Matthew Auld wrote:
>> Keep things minimal and select the 1way+ by default on all platforms.
>> Other users can use intel_buf, get_offset_pat_index etc or use
>> __xe_vm_bind() directly. Display tests don't directly use this
>> interface.
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Pallavi Mishra <pallavi.mishra@intel.com>
>> ---
>> lib/xe/xe_ioctl.c | 8 ++++++--
>> lib/xe/xe_ioctl.h | 2 +-
>> tests/intel/xe_vm.c | 4 +++-
>> 3 files changed, 10 insertions(+), 4 deletions(-)
>>
>> diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c
>> index 80696aa59..ebaed1e96 100644
>> --- a/lib/xe/xe_ioctl.c
>> +++ b/lib/xe/xe_ioctl.c
>> @@ -41,6 +41,7 @@
>> #include "config.h"
>> #include "drmtest.h"
>> #include "igt_syncobj.h"
>> +#include "intel_pat.h"
>> #include "ioctl_wrappers.h"
>> #include "xe_ioctl.h"
>> #include "xe_query.h"
>> @@ -92,7 +93,7 @@ void xe_vm_bind_array(int fd, uint32_t vm, uint32_t
>> exec_queue,
>> int __xe_vm_bind(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo,
>> uint64_t offset, uint64_t addr, uint64_t size, uint32_t op,
>> struct drm_xe_sync *sync, uint32_t num_syncs, uint32_t region,
>> - uint64_t ext)
>> + uint8_t pat_index, uint64_t ext)
>> {
>> struct drm_xe_vm_bind bind = {
>> .extensions = ext,
>> @@ -107,6 +108,8 @@ int __xe_vm_bind(int fd, uint32_t vm, uint32_t
>> exec_queue, uint32_t bo,
>> .num_syncs = num_syncs,
>> .syncs = (uintptr_t)sync,
>> .exec_queue_id = exec_queue,
>> + .bind.pat_index = (pat_index == DEFAULT_PAT_INDEX) ?
>> + intel_get_pat_idx_wb(fd) : pat_index,
>
> Ok, so KMD has no idea of default PAT, UMD always has to specify it. Ok.
>
> NIT...keep all bind.* setting together?
>
> Also, there seems to be vm_bind_array() all invocations of which also needs
> update to include bind.pat_index=DEFAULT_PAT_INDEX?
Ah, I think I missed the one in tests/intel/xe_vm.c. vm_bind_array()
should rather use the real pat_index. Or at least some higher level
things needs to do it.
>
> Niranjana
>
>> };
>>
>> if (igt_ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind))
>> @@ -121,7 +124,8 @@ void __xe_vm_bind_assert(int fd, uint32_t vm,
>> uint32_t exec_queue, uint32_t bo,
>> uint32_t num_syncs, uint32_t region, uint64_t ext)
>> {
>> igt_assert_eq(__xe_vm_bind(fd, vm, exec_queue, bo, offset, addr,
>> size,
>> - op, sync, num_syncs, region, ext), 0);
>> + op, sync, num_syncs, region, DEFAULT_PAT_INDEX,
>> + ext), 0);
>> }
>>
>> void xe_vm_bind(int fd, uint32_t vm, uint32_t bo, uint64_t offset,
>> diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h
>> index c18fc878c..cafbb011a 100644
>> --- a/lib/xe/xe_ioctl.h
>> +++ b/lib/xe/xe_ioctl.h
>> @@ -20,7 +20,7 @@ uint32_t xe_vm_create(int fd, uint32_t flags,
>> uint64_t ext);
>> int __xe_vm_bind(int fd, uint32_t vm, uint32_t exec_queue, uint32_t bo,
>> uint64_t offset, uint64_t addr, uint64_t size, uint32_t op,
>> struct drm_xe_sync *sync, uint32_t num_syncs, uint32_t region,
>> - uint64_t ext);
>> + uint8_t pat_index, uint64_t ext);
>> void __xe_vm_bind_assert(int fd, uint32_t vm, uint32_t exec_queue,
>> uint32_t bo,
>> uint64_t offset, uint64_t addr, uint64_t size,
>> uint32_t op, struct drm_xe_sync *sync,
>> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
>> index 4952ea786..ffb70973b 100644
>> --- a/tests/intel/xe_vm.c
>> +++ b/tests/intel/xe_vm.c
>> @@ -10,6 +10,7 @@
>> */
>>
>> #include "igt.h"
>> +#include "intel_pat.h"
>> #include "lib/igt_syncobj.h"
>> #include "lib/intel_reg.h"
>> #include "xe_drm.h"
>> @@ -316,7 +317,8 @@ static void userptr_invalid(int fd)
>> vm = xe_vm_create(fd, 0, 0);
>> munmap(data, size);
>> ret = __xe_vm_bind(fd, vm, 0, 0, to_user_pointer(data), 0x40000,
>> - size, XE_VM_BIND_OP_MAP_USERPTR, NULL, 0, 0, 0);
>> + size, XE_VM_BIND_OP_MAP_USERPTR, NULL, 0, 0,
>> + DEFAULT_PAT_INDEX, 0);
>> igt_assert(ret == -EFAULT);
>>
>> xe_vm_destroy(fd, vm);
>> --
>> 2.41.0
>>
next prev parent reply other threads:[~2023-10-17 11:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 14:14 [igt-dev] [PATCH i-g-t v3 00/12] PAT and cache coherency support Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 01/12] drm-uapi/xe_drm: sync to get pat and coherency bits Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 02/12] lib/igt_fb: mark buffers as SCANOUT Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 03/12] lib/igt_draw: " Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 04/12] lib/xe: support cpu_caching and coh_mod for gem_create Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 05/12] tests/xe/mmap: add some tests for cpu_caching and coh_mode Matthew Auld
2023-10-16 16:04 ` Mishra, Pallavi
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 06/12] lib/intel_pat: add helpers for common pat_index modes Matthew Auld
2023-10-16 22:07 ` Niranjana Vishwanathapura
2023-10-17 10:59 ` Matthew Auld
2023-10-19 4:45 ` Niranjana Vishwanathapura
2023-10-17 22:54 ` Mishra, Pallavi
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 07/12] lib/allocator: add get_offset_pat_index() helper Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 08/12] lib/intel_blt: support pat_index Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 09/12] lib/intel_buf: " Matthew Auld
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 10/12] lib/xe_ioctl: update vm_bind to account for pat_index Matthew Auld
2023-10-16 22:46 ` Niranjana Vishwanathapura
2023-10-17 11:08 ` Matthew Auld [this message]
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 11/12] tests/xe: add some vm_bind pat_index tests Matthew Auld
2023-10-18 4:16 ` Niranjana Vishwanathapura
2023-10-18 8:10 ` Matthew Auld
2023-10-19 4:32 ` Niranjana Vishwanathapura
2023-10-16 14:14 ` [igt-dev] [PATCH i-g-t v3 12/12] tests/intel-ci/xe: add pat and caching related tests Matthew Auld
2023-10-19 4:37 ` Niranjana Vishwanathapura
2023-10-16 20:03 ` [igt-dev] ✗ CI.xeBAT: failure for PAT and cache coherency support (rev3) Patchwork
2023-10-16 20:03 ` [igt-dev] ✗ Fi.CI.BAT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=67b3af34-e7d1-095e-7d5a-961542c3f84e@intel.com \
--to=matthew.auld@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=niranjana.vishwanathapura@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox