From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Content-Type: multipart/alternative; boundary="===============7608639721886487534==" MIME-Version: 1.0 From: Patchwork To: =?utf-8?q?Zbigniew_Kempczy=C5=84ski?= Date: Tue, 11 Jul 2023 12:09:40 -0000 Message-ID: <168907738054.18665.10177057709113941285@emeril.freedesktop.org> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> Subject: [igt-dev] =?utf-8?q?=E2=97=8B_CI=2ExeBAT=3A_info_for_Extend_inte?= =?utf-8?q?l=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: igt-dev@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: --===============7608639721886487534== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit == Series Details == Series: Extend intel_blt to work on Xe (rev3) URL : https://patchwork.freedesktop.org/series/120162/ State : info == Summary == Participating hosts: bat-atsm-2 bat-dg2-oem2 bat-adlp-7 Missing hosts results[0]: Results: [IGTPW_9383](https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9383/index.html) --===============7608639721886487534== Content-Type: text/html; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Project List - Patchwork Patch Details
Series:Extend intel_blt to work on Xe (rev3)
URL:https://patchwork.freedesktop.org/series/120162/
State:info

Participating hosts:
bat-atsm-2
bat-dg2-oem2
bat-adlp-7
Missing hosts results[0]:
Results: IGTPW_9383

--===============7608639721886487534==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0835F10E37C for ; Tue, 11 Jul 2023 11:20:19 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:52 +0200 Message-Id: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 00/17] Extend intel_blt to work on Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Blitter library currently supports block-copy, ctrl-surf-copy and fast-copy on i915. Lets extend this to xe as most of the code is driver independent. v2: Rewrite tracking allocator calls alloc()/free() to handle multiprocess/multithreaded scenarios. api_intel_allocator now supports both drivers (i915 and xe). v3: Address review comments (Karolina) Cc: Kamil Konieczny Cc: Karolina Stolarek Cc: Juha-Pekka Heikkila Cc: Bhanuprakash Modem Zbigniew Kempczyński (17): tests/api_intel_allocator: Don't use allocator ahnd aliasing api lib/intel_allocator: Drop aliasing allocator handle api lib/intel_allocator: Remove extensive debugging lib/xe_ioctl: Export non-assert xe_exec function lib/xe_query: Use vramN when returning string region name lib/xe_query: Add xe_region_class() helper lib/drmtest: Add get_intel_driver() helper lib/xe_util: Return dynamic subtest name for Xe lib/xe_util: Add vm bind/unbind helper for Xe lib/intel_allocator: Add intel_allocator_bind() lib/intel_ctx: Add xe context information lib/intel_blt: Introduce blt_copy_init() helper to cache driver lib/intel_blt: Extend blitter library to support xe driver tests/xe_ccs: Check if flatccs is working with block-copy for Xe tests/xe_exercise_blt: Check blitter library fast-copy for Xe tests/api-intel-allocator: Adopt to exercise allocator to Xe tests/gem_ccs: Avoid writing png twice lib/drmtest.c | 10 + lib/drmtest.h | 1 + lib/igt_core.c | 5 + lib/igt_fb.c | 2 +- lib/intel_allocator.c | 341 ++++++++++---- lib/intel_allocator.h | 4 +- lib/intel_allocator_msgchannel.h | 8 +- lib/intel_blt.c | 271 +++++++---- lib/intel_blt.h | 10 +- lib/intel_ctx.c | 98 +++- lib/intel_ctx.h | 14 + lib/meson.build | 3 +- lib/xe/xe_ioctl.c | 2 +- lib/xe/xe_ioctl.h | 1 + lib/xe/xe_query.c | 20 +- lib/xe/xe_query.h | 1 + lib/xe/xe_util.c | 229 ++++++++++ lib/xe/xe_util.h | 47 ++ tests/i915/api_intel_allocator.c | 46 +- tests/i915/gem_ccs.c | 35 +- tests/i915/gem_exercise_blt.c | 22 +- tests/i915/gem_lmem_swapping.c | 4 +- tests/meson.build | 2 + tests/xe/xe_ccs.c | 757 +++++++++++++++++++++++++++++++ tests/xe/xe_exercise_blt.c | 377 +++++++++++++++ 25 files changed, 2074 insertions(+), 236 deletions(-) create mode 100644 lib/xe/xe_util.c create mode 100644 lib/xe/xe_util.h create mode 100644 tests/xe/xe_ccs.c create mode 100644 tests/xe/xe_exercise_blt.c -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 17AE410E37E for ; Tue, 11 Jul 2023 11:20:23 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:53 +0200 Message-Id: <20230711112009.122482-2-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 01/17] tests/api_intel_allocator: Don't use allocator ahnd aliasing api List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: There's no tests (apart this one) which are using aliasing ahnd - intel_allocator_open_vm_as(). Additionally it is problematic on adopting allocator to xe where I need to track allocations to support easy vm binding. Let's adopt "open-vm" to not to use this api. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- tests/i915/api_intel_allocator.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c index b7e3efb87f..77c2d25e83 100644 --- a/tests/i915/api_intel_allocator.c +++ b/tests/i915/api_intel_allocator.c @@ -612,32 +612,27 @@ static void reopen_fork(int fd) static void open_vm(int fd) { - uint64_t ahnd[4], offset[4], size = 0x1000; + uint64_t ahnd[3], offset[3], size = 0x1000; int i, n = ARRAY_SIZE(ahnd); ahnd[0] = intel_allocator_open_vm(fd, 1, INTEL_ALLOCATOR_SIMPLE); ahnd[1] = intel_allocator_open_vm(fd, 1, INTEL_ALLOCATOR_SIMPLE); - ahnd[2] = intel_allocator_open_vm_as(ahnd[1], 2); - ahnd[3] = intel_allocator_open(fd, 3, INTEL_ALLOCATOR_SIMPLE); + ahnd[2] = intel_allocator_open(fd, 2, INTEL_ALLOCATOR_SIMPLE); offset[0] = intel_allocator_alloc(ahnd[0], 1, size, 0); offset[1] = intel_allocator_alloc(ahnd[1], 2, size, 0); igt_assert(offset[0] != offset[1]); - offset[2] = intel_allocator_alloc(ahnd[2], 3, size, 0); - igt_assert(offset[0] != offset[2] && offset[1] != offset[2]); - - offset[3] = intel_allocator_alloc(ahnd[3], 1, size, 0); - igt_assert(offset[0] == offset[3]); + offset[2] = intel_allocator_alloc(ahnd[2], 1, size, 0); + igt_assert(offset[0] == offset[2]); /* - * As ahnd[0-2] lead to same allocator check can we free all handles + * As ahnd[0-1] lead to same allocator check we can free all handles * using selected ahnd. */ - intel_allocator_free(ahnd[0], 1); - intel_allocator_free(ahnd[0], 2); - intel_allocator_free(ahnd[0], 3); - intel_allocator_free(ahnd[3], 1); + igt_assert_eq(intel_allocator_free(ahnd[0], 1), true); + igt_assert_eq(intel_allocator_free(ahnd[1], 2), true); + igt_assert_eq(intel_allocator_free(ahnd[2], 1), true); for (i = 0; i < n - 1; i++) igt_assert_eq(intel_allocator_close(ahnd[i]), (i == n - 2)); -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id F098010E37F for ; Tue, 11 Jul 2023 11:20:25 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:54 +0200 Message-Id: <20230711112009.122482-3-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 02/17] lib/intel_allocator: Drop aliasing allocator handle api List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: There's no real user of this api, lets drop it. Signed-off-by: Zbigniew Kempczyński -- v3: Remove also ipc message passing for open-as (Karolina) --- lib/intel_allocator.c | 73 -------------------------------- lib/intel_allocator.h | 1 - lib/intel_allocator_msgchannel.h | 8 +--- 3 files changed, 1 insertion(+), 81 deletions(-) diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c index 8161221dbf..09f665fbb9 100644 --- a/lib/intel_allocator.c +++ b/lib/intel_allocator.c @@ -25,7 +25,6 @@ static const char *reqtype_str[] = { [REQ_STOP] = "stop", [REQ_OPEN] = "open", - [REQ_OPEN_AS] = "open as", [REQ_CLOSE] = "close", [REQ_ADDRESS_RANGE] = "address range", [REQ_ALLOC] = "alloc", @@ -376,19 +375,6 @@ static struct allocator *allocator_open(int fd, uint32_t ctx, uint32_t vm, return al; } -static struct allocator *allocator_open_as(struct allocator *base, - uint32_t new_vm, uint64_t *ahndp) -{ - struct allocator *al; - - igt_assert(ahndp); - al = __allocator_create(base->fd, base->ctx, new_vm, base->ial); - __allocator_get(al); - *ahndp = __handle_create(al); - - return al; -} - static bool allocator_close(uint64_t ahnd) { struct allocator *al; @@ -512,47 +498,6 @@ static int handle_request(struct alloc_req *req, struct alloc_resp *resp) refcnt - 1, refcnt, ret - 1, ret); break; - case REQ_OPEN_AS: - /* lock first to avoid concurrent close */ - pthread_mutex_lock(&map_mutex); - - al = __allocator_find_by_handle(req->allocator_handle); - resp->response_type = RESP_OPEN_AS; - - if (!al) { - alloc_info(" [tid: %ld] ahnd: %" PRIx64 - " -> no handle\n", - (long) req->tid, req->allocator_handle); - pthread_mutex_unlock(&map_mutex); - break; - } - - if (!al->vm) { - alloc_info(" [tid: %ld] ahnd: %" PRIx64 - " -> only open as for is possible\n", - (long) req->tid, req->allocator_handle); - pthread_mutex_unlock(&map_mutex); - break; - } - - - al = allocator_open_as(al, req->open_as.new_vm, &ahnd); - refcnt = atomic_load(&al->refcount); - ret = atomic_load(&al->ial->refcount); - pthread_mutex_unlock(&map_mutex); - - resp->response_type = RESP_OPEN_AS; - resp->open.allocator_handle = ahnd; - - alloc_info(" [tid: %ld] fd: %d, ahnd: %" PRIx64 - ", ctx: %u, vm: %u" - ", alloc_type: %u, al->refcnt: %ld->%ld" - ", refcnt: %d->%d\n", - (long) req->tid, al->fd, ahnd, - al->ctx, al->vm, al->ial->type, - refcnt - 1, refcnt, ret - 1, ret); - break; - case REQ_CLOSE: pthread_mutex_lock(&map_mutex); al = __allocator_find_by_handle(req->allocator_handle); @@ -1037,24 +982,6 @@ uint64_t intel_allocator_open_vm(int fd, uint32_t vm, uint8_t allocator_type) ALLOC_STRATEGY_HIGH_TO_LOW, 0); } -uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm) -{ - struct alloc_req req = { .request_type = REQ_OPEN_AS, - .allocator_handle = allocator_handle, - .open_as.new_vm = new_vm }; - struct alloc_resp resp; - - /* Get child_tid only once at open() */ - if (child_tid == -1) - child_tid = gettid(); - - igt_assert(handle_request(&req, &resp) == 0); - igt_assert(resp.open_as.allocator_handle); - igt_assert(resp.response_type == RESP_OPEN_AS); - - return resp.open.allocator_handle; -} - /** * intel_allocator_close: * @allocator_handle: handle to the allocator that will be closed diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h index a6bf573e9d..3ec74f6191 100644 --- a/lib/intel_allocator.h +++ b/lib/intel_allocator.h @@ -182,7 +182,6 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm, enum allocator_strategy strategy, uint64_t default_alignment); -uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm); bool intel_allocator_close(uint64_t allocator_handle); void intel_allocator_get_address_range(uint64_t allocator_handle, uint64_t *startp, uint64_t *endp); diff --git a/lib/intel_allocator_msgchannel.h b/lib/intel_allocator_msgchannel.h index cefbf4ce33..ba38530fd1 100644 --- a/lib/intel_allocator_msgchannel.h +++ b/lib/intel_allocator_msgchannel.h @@ -13,7 +13,6 @@ enum reqtype { REQ_STOP, REQ_OPEN, - REQ_OPEN_AS, REQ_CLOSE, REQ_ADDRESS_RANGE, REQ_ALLOC, @@ -27,7 +26,6 @@ enum reqtype { enum resptype { RESP_OPEN, - RESP_OPEN_AS, RESP_CLOSE, RESP_ADDRESS_RANGE, RESP_ALLOC, @@ -58,10 +56,6 @@ struct alloc_req { uint64_t default_alignment; } open; - struct { - uint32_t new_vm; - } open_as; - struct { uint32_t handle; uint64_t size; @@ -100,7 +94,7 @@ struct alloc_resp { union { struct { uint64_t allocator_handle; - } open, open_as; + } open; struct { bool is_empty; -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 39E3B10E381 for ; Tue, 11 Jul 2023 11:20:29 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:55 +0200 Message-Id: <20230711112009.122482-4-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 03/17] lib/intel_allocator: Remove extensive debugging List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Debugging map keys comparison leads to produce extensive logging what in turn obscures analysis. Remove it to get clearer logs. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- lib/intel_allocator.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c index 09f665fbb9..cf964ccc41 100644 --- a/lib/intel_allocator.c +++ b/lib/intel_allocator.c @@ -1330,9 +1330,6 @@ static int equal_handles(const void *key1, const void *key2) { const struct handle_entry *h1 = key1, *h2 = key2; - alloc_debug("h1: %llx, h2: %llx\n", - (long long) h1->handle, (long long) h2->handle); - return h1->handle == h2->handle; } @@ -1340,9 +1337,6 @@ static int equal_ctx(const void *key1, const void *key2) { const struct allocator *a1 = key1, *a2 = key2; - alloc_debug("a1: , a2 \n", - a1->fd, a1->ctx, a2->fd, a2->ctx); - return a1->fd == a2->fd && a1->ctx == a2->ctx; } @@ -1350,9 +1344,6 @@ static int equal_vm(const void *key1, const void *key2) { const struct allocator *a1 = key1, *a2 = key2; - alloc_debug("a1: , a2 \n", - a1->fd, a1->vm, a2->fd, a2->vm); - return a1->fd == a2->fd && a1->vm == a2->vm; } -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CACA910E382 for ; Tue, 11 Jul 2023 11:20:32 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:56 +0200 Message-Id: <20230711112009.122482-5-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 04/17] lib/xe_ioctl: Export non-assert xe_exec function List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Export __xe_exec() helper to allow caller to handle the error individually. Signed-off-by: Zbigniew Kempczyński --- lib/xe/xe_ioctl.c | 2 +- lib/xe/xe_ioctl.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c index 9ead7307c4..0b5c7a4fce 100644 --- a/lib/xe/xe_ioctl.c +++ b/lib/xe/xe_ioctl.c @@ -357,7 +357,7 @@ void *xe_bo_mmap_ext(int fd, uint32_t bo, size_t size, int prot) return __xe_bo_map(fd, bo, size, prot); } -static int __xe_exec(int fd, struct drm_xe_exec *exec) +int __xe_exec(int fd, struct drm_xe_exec *exec) { int err = 0; diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h index e014ad66c9..320e0f9f68 100644 --- a/lib/xe/xe_ioctl.h +++ b/lib/xe/xe_ioctl.h @@ -75,6 +75,7 @@ void xe_engine_destroy(int fd, uint32_t engine); uint64_t xe_bo_mmap_offset(int fd, uint32_t bo); void *xe_bo_map(int fd, uint32_t bo, size_t size); void *xe_bo_mmap_ext(int fd, uint32_t bo, size_t size, int prot); +int __xe_exec(int fd, struct drm_xe_exec *exec); void xe_exec(int fd, struct drm_xe_exec *exec); void xe_exec_sync(int fd, uint32_t engine, uint64_t addr, struct drm_xe_sync *sync, uint32_t num_syncs); -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id F29F610E383 for ; Tue, 11 Jul 2023 11:20:35 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:57 +0200 Message-Id: <20230711112009.122482-6-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 05/17] lib/xe_query: Use vramN when returning string region name List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: For tests which are mixing regions (like xe_ccs) name is confusing. As an example might be example "subtest-name-vram-1-vram-1". It's more readable when it will be renamed to "subtest-name-vram1-vram1". Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- lib/xe/xe_query.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c index 48fb5afba7..830b7e401d 100644 --- a/lib/xe/xe_query.c +++ b/lib/xe/xe_query.c @@ -445,7 +445,7 @@ struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region) * xe_region_name: * @region: region mask * - * Returns region string like "system" or "vram-n" where n=0...62. + * Returns region string like "system" or "vramN" where N=0...62. */ const char *xe_region_name(uint64_t region) { @@ -457,7 +457,7 @@ const char *xe_region_name(uint64_t region) vrams = calloc(64, sizeof(char *)); for (int i = 0; i < 64; i++) { if (i != 0) - asprintf(&vrams[i], "vram-%d", i - 1); + asprintf(&vrams[i], "vram%d", i - 1); else asprintf(&vrams[i], "system"); igt_assert(vrams[i]); -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 80AC110E384 for ; Tue, 11 Jul 2023 11:20:39 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:58 +0200 Message-Id: <20230711112009.122482-7-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 06/17] lib/xe_query: Add xe_region_class() helper List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: In the common code we often need to be aware of region class. Add helper which returns it from region id. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- lib/xe/xe_query.c | 16 ++++++++++++++++ lib/xe/xe_query.h | 1 + 2 files changed, 17 insertions(+) diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c index 830b7e401d..f535ad8534 100644 --- a/lib/xe/xe_query.c +++ b/lib/xe/xe_query.c @@ -467,6 +467,22 @@ const char *xe_region_name(uint64_t region) return vrams[region_idx]; } +/** + * xe_region_class: + * @fd: xe device fd + * @region: region mask + * + * Returns class of memory region structure for @region mask. + */ +uint16_t xe_region_class(int fd, uint64_t region) +{ + struct drm_xe_query_mem_region *memreg; + + memreg = xe_mem_region(fd, region); + + return memreg->mem_class; +} + /** * xe_min_page_size: * @fd: xe device fd diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h index ff328ab942..68ca5a680c 100644 --- a/lib/xe/xe_query.h +++ b/lib/xe/xe_query.h @@ -85,6 +85,7 @@ struct drm_xe_engine_class_instance *xe_hw_engines(int fd); struct drm_xe_engine_class_instance *xe_hw_engine(int fd, int idx); struct drm_xe_query_mem_region *xe_mem_region(int fd, uint64_t region); const char *xe_region_name(uint64_t region); +uint16_t xe_region_class(int fd, uint64_t region); uint32_t xe_min_page_size(int fd, uint64_t region); struct drm_xe_query_config *xe_config(int fd); unsigned int xe_number_hw_engines(int fd); -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 08DE510E386 for ; Tue, 11 Jul 2023 11:20:46 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:00 +0200 Message-Id: <20230711112009.122482-9-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 08/17] lib/xe_util: Return dynamic subtest name for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: For tests which are working on more than one region using name suffix like "vram01-system" etc. is common thing. Instead handcrafting this naming add xe_memregion_dynamic_subtest_name() function which is similar to memregion_dynamic_subtest_name() for i915. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- lib/meson.build | 3 +- lib/xe/xe_util.c | 104 +++++++++++++++++++++++++++++++++++++++++++++++ lib/xe/xe_util.h | 30 ++++++++++++++ 3 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 lib/xe/xe_util.c create mode 100644 lib/xe/xe_util.h diff --git a/lib/meson.build b/lib/meson.build index 5523b4450e..ce11c0715f 100644 --- a/lib/meson.build +++ b/lib/meson.build @@ -105,7 +105,8 @@ lib_sources = [ 'xe/xe_compute_square_kernels.c', 'xe/xe_ioctl.c', 'xe/xe_query.c', - 'xe/xe_spin.c' + 'xe/xe_spin.c', + 'xe/xe_util.c', ] lib_deps = [ diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c new file mode 100644 index 0000000000..5f0f69a8c6 --- /dev/null +++ b/lib/xe/xe_util.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + */ + +#include "igt.h" +#include "igt_syncobj.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" + +static bool __region_belongs_to_regions_type(struct drm_xe_query_mem_region *region, + uint32_t *mem_regions_type, + int num_regions) +{ + for (int i = 0; i < num_regions; i++) + if (mem_regions_type[i] == region->mem_class) + return true; + return false; +} + +struct igt_collection * +__xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions) +{ + struct drm_xe_query_mem_region *memregion; + struct igt_collection *set = NULL; + uint64_t memreg = all_memory_regions(xe), region; + int count = 0, pos = 0; + + xe_for_each_mem_region(xe, memreg, region) { + memregion = xe_mem_region(xe, region); + if (__region_belongs_to_regions_type(memregion, + mem_regions_type, + num_regions)) + count++; + } + + set = igt_collection_create(count); + + xe_for_each_mem_region(xe, memreg, region) { + memregion = xe_mem_region(xe, region); + igt_assert(region < (1ull << 31)); + if (__region_belongs_to_regions_type(memregion, + mem_regions_type, + num_regions)) { + igt_collection_set_value(set, pos++, (int)region); + } + } + + igt_assert(count == pos); + + return set; +} + +/** + * xe_memregion_dynamic_subtest_name: + * @xe: drm fd of Xe device + * @igt_collection: memory region collection + * + * Function iterates over all memory regions inside the collection (keeped + * in the value field) and generates the name which can be used during dynamic + * subtest creation. + * + * Returns: newly allocated string, has to be freed by caller. Asserts if + * caller tries to create a name using empty collection. + */ +char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set) +{ + struct igt_collection_data *data; + char *name, *p; + uint32_t region, len; + + igt_assert(set && set->size); + /* enough for "name%d-" * n */ + len = set->size * 8; + p = name = malloc(len); + igt_assert(name); + + for_each_collection_data(data, set) { + struct drm_xe_query_mem_region *memreg; + int r; + + region = data->value; + memreg = xe_mem_region(xe, region); + + if (XE_IS_CLASS_VRAM(memreg)) + r = snprintf(p, len, "%s%d-", + xe_region_name(region), + memreg->instance); + else + r = snprintf(p, len, "%s-", + xe_region_name(region)); + + igt_assert(r > 0); + p += r; + len -= r; + } + + /* remove last '-' */ + *(p - 1) = 0; + + return name; +} + diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h new file mode 100644 index 0000000000..9f56fa9898 --- /dev/null +++ b/lib/xe/xe_util.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + * + */ + +#ifndef XE_UTIL_H +#define XE_UTIL_H + +#include +#include +#include +#include + +#define XE_IS_SYSMEM_MEMORY_REGION(fd, region) \ + (xe_region_class(fd, region) == XE_MEM_REGION_CLASS_SYSMEM) +#define XE_IS_VRAM_MEMORY_REGION(fd, region) \ + (xe_region_class(fd, region) == XE_MEM_REGION_CLASS_VRAM) + +struct igt_collection * +__xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions); + +#define xe_get_memory_region_set(regions, mem_region_types...) ({ \ + unsigned int arr__[] = { mem_region_types }; \ + __xe_get_memory_region_set(regions, arr__, ARRAY_SIZE(arr__)); \ +}) + +char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set); + +#endif /* XE_UTIL_H */ -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id AAC9810E37E for ; Tue, 11 Jul 2023 11:20:42 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:19:59 +0200 Message-Id: <20230711112009.122482-8-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 07/17] lib/drmtest: Add get_intel_driver() helper List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: In libraries with i915 and Xe code divergence we might use is_xe_device() or is_i915_device() to distinct code paths. But to avoid additional open and string compare we can cache this information in data structures. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- lib/drmtest.c | 10 ++++++++++ lib/drmtest.h | 1 + 2 files changed, 11 insertions(+) diff --git a/lib/drmtest.c b/lib/drmtest.c index 5cdb0196d3..e1da66c877 100644 --- a/lib/drmtest.c +++ b/lib/drmtest.c @@ -151,6 +151,16 @@ bool is_intel_device(int fd) return is_i915_device(fd) || is_xe_device(fd); } +enum intel_driver get_intel_driver(int fd) +{ + if (is_xe_device(fd)) + return INTEL_DRIVER_XE; + else if (is_i915_device(fd)) + return INTEL_DRIVER_I915; + + igt_assert_f(0, "Device is not handled by Intel driver\n"); +} + static char _forced_driver[16] = ""; /** diff --git a/lib/drmtest.h b/lib/drmtest.h index 9c3ea5d14c..97ab6e759e 100644 --- a/lib/drmtest.h +++ b/lib/drmtest.h @@ -124,6 +124,7 @@ bool is_nouveau_device(int fd); bool is_vc4_device(int fd); bool is_xe_device(int fd); bool is_intel_device(int fd); +enum intel_driver get_intel_driver(int fd); /** * do_or_die: -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5AEC810E386 for ; Tue, 11 Jul 2023 11:20:49 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:01 +0200 Message-Id: <20230711112009.122482-10-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 09/17] lib/xe_util: Add vm bind/unbind helper for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Before calling exec we need to prepare vm to contain valid entries. Bind/unbind in xe expects single bind_op or vector of bind_ops what makes preparation of it a little bit inconvinient. Add function which iterates over list of xe_object (auxiliary structure which describes bind information for object) and performs the bind/unbind in one step. It also supports passing syncobj in/out to work in pipelined executions. Signed-off-by: Zbigniew Kempczyński -- v3: - Drop priv field in the structure --- lib/xe/xe_util.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++ lib/xe/xe_util.h | 17 +++++++ 2 files changed, 142 insertions(+) diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c index 5f0f69a8c6..7d78065a13 100644 --- a/lib/xe/xe_util.c +++ b/lib/xe/xe_util.c @@ -102,3 +102,128 @@ char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set) return name; } +#ifdef XEBINDDBG +#define bind_info igt_info +#define bind_debug igt_debug +#else +#define bind_info(...) {} +#define bind_debug(...) {} +#endif + +static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct igt_list_head *obj_list, + uint32_t *num_ops) +{ + struct drm_xe_vm_bind_op *bind_ops, *ops; + struct xe_object *obj; + uint32_t num_objects = 0, i = 0, op; + + igt_list_for_each_entry(obj, obj_list, link) + num_objects++; + + *num_ops = num_objects; + if (!num_objects) { + bind_info(" [nothing to bind]\n"); + return NULL; + } + + bind_ops = calloc(num_objects, sizeof(*bind_ops)); + igt_assert(bind_ops); + + igt_list_for_each_entry(obj, obj_list, link) { + ops = &bind_ops[i]; + + if (obj->bind_op == XE_OBJECT_BIND) { + op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC; + ops->obj = obj->handle; + } else { + op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC; + } + + ops->op = op; + ops->obj_offset = 0; + ops->addr = obj->offset; + ops->range = obj->size; + ops->region = 0; + + bind_info(" [%d]: [%6s] handle: %u, offset: %llx, size: %llx\n", + i, obj->bind_op == XE_OBJECT_BIND ? "BIND" : "UNBIND", + ops->obj, (long long)ops->addr, (long long)ops->range); + i++; + } + + return bind_ops; +} + +/** + * xe_bind_unbind_async: + * @xe: drm fd of Xe device + * @vm: vm to bind/unbind objects to/from + * @bind_engine: bind engine, 0 if default + * @obj_list: list of xe_object + * @sync_in: sync object (fence-in), 0 if there's no input dependency + * @sync_out: sync object (fence-out) to signal on bind/unbind completion, + * if 0 wait for bind/unbind completion. + * + * Function iterates over xe_object @obj_list, prepares binding operation + * and does bind/unbind in one step. Providing sync_in / sync_out allows + * working in pipelined mode. With sync_in and sync_out set to 0 function + * waits until binding operation is complete. + */ +void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine, + struct igt_list_head *obj_list, + uint32_t sync_in, uint32_t sync_out) +{ + struct drm_xe_vm_bind_op *bind_ops; + struct drm_xe_sync tabsyncs[2] = { + { .flags = DRM_XE_SYNC_SYNCOBJ, .handle = sync_in }, + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, .handle = sync_out }, + }; + struct drm_xe_sync *syncs; + uint32_t num_binds = 0; + int num_syncs; + + bind_info("[Binding to vm: %u]\n", vm); + bind_ops = xe_alloc_bind_ops(obj_list, &num_binds); + + if (!num_binds) { + if (sync_out) + syncobj_signal(xe, &sync_out, 1); + return; + } + + if (sync_in) { + syncs = tabsyncs; + num_syncs = 2; + } else { + syncs = &tabsyncs[1]; + num_syncs = 1; + } + + /* User didn't pass sync out, create it and wait for completion */ + if (!sync_out) + tabsyncs[1].handle = syncobj_create(xe, 0); + + bind_info("[Binding syncobjs: (in: %u, out: %u)]\n", + tabsyncs[0].handle, tabsyncs[1].handle); + + if (num_binds == 1) { + if ((bind_ops[0].op & 0xffff) == XE_VM_BIND_OP_MAP) + xe_vm_bind_async(xe, vm, bind_engine, bind_ops[0].obj, 0, + bind_ops[0].addr, bind_ops[0].range, + syncs, num_syncs); + else + xe_vm_unbind_async(xe, vm, bind_engine, 0, + bind_ops[0].addr, bind_ops[0].range, + syncs, num_syncs); + } else { + xe_vm_bind_array(xe, vm, bind_engine, bind_ops, + num_binds, syncs, num_syncs); + } + + if (!sync_out) { + igt_assert_eq(syncobj_wait_err(xe, &tabsyncs[1].handle, 1, INT64_MAX, 0), 0); + syncobj_destroy(xe, tabsyncs[1].handle); + } + + free(bind_ops); +} diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h index 9f56fa9898..61511dd97f 100644 --- a/lib/xe/xe_util.h +++ b/lib/xe/xe_util.h @@ -27,4 +27,21 @@ __xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions); char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set); +enum xe_bind_op { + XE_OBJECT_BIND, + XE_OBJECT_UNBIND, +}; + +struct xe_object { + uint32_t handle; + uint64_t offset; + uint64_t size; + enum xe_bind_op bind_op; + struct igt_list_head link; +}; + +void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine, + struct igt_list_head *obj_list, + uint32_t sync_in, uint32_t sync_out); + #endif /* XE_UTIL_H */ -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2CF5D10E387 for ; Tue, 11 Jul 2023 11:20:52 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:02 +0200 Message-Id: <20230711112009.122482-11-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 10/17] lib/intel_allocator: Add intel_allocator_bind() List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Synchronize allocator state to vm. This change allows xe user to execute vm-bind/unbind for allocator alloc()/free() operations which occurred since last binding/unbinding. Before doing exec user should call intel_allocator_bind() to ensure all vma's are in place. Signed-off-by: Zbigniew Kempczyński --- v2: Rewrite tracking mechanism: previous code uses bind map embedded in allocator structure. Unfortunately this wasn't good idea - for xe binding everything was fine, but it regress multiprocess/ multithreaded allocations. Main reason of this was children processes couldn't get its reference as this memory was allocated on allocator thread (separate process). Currently each child contains its own separate tracking maps for ahnd and for each ahnd bind map. v3: - Don't use priv field (we may clean bind_map apriori as failing asserts and outdated bind_map is not a problem anymore). - Use only vm on tracking ahnd (Karolina) - Add braces to avoid checkpatch complaining (Karolina) - Use igt_assert_f() instead conditional block (Karolina) --- lib/igt_core.c | 5 + lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++- lib/intel_allocator.h | 3 + 3 files changed, 265 insertions(+), 2 deletions(-) diff --git a/lib/igt_core.c b/lib/igt_core.c index 2ae2cb6883..041e4b3288 100644 --- a/lib/igt_core.c +++ b/lib/igt_core.c @@ -74,6 +74,7 @@ #include "igt_sysrq.h" #include "igt_rc.h" #include "igt_list.h" +#include "igt_map.h" #include "igt_device_scan.h" #include "igt_thread.h" #include "runnercomms.h" @@ -320,6 +321,8 @@ bool test_multi_fork_child; /* For allocator purposes */ pid_t child_pid = -1; __thread pid_t child_tid = -1; +struct igt_map *ahnd_map; +pthread_mutex_t ahnd_map_mutex; enum { /* @@ -2523,6 +2526,8 @@ bool __igt_fork(void) case 0: test_child = true; pthread_mutex_init(&print_mutex, NULL); + pthread_mutex_init(&ahnd_map_mutex, NULL); + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); child_pid = getpid(); child_tid = -1; exit_handler_count = 0; diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c index cf964ccc41..f0a9b7fb53 100644 --- a/lib/intel_allocator.c +++ b/lib/intel_allocator.c @@ -17,8 +17,8 @@ #include "intel_allocator.h" #include "intel_allocator_msgchannel.h" #include "xe/xe_query.h" +#include "xe/xe_util.h" -//#define ALLOCDBG #ifdef ALLOCDBG #define alloc_info igt_info #define alloc_debug igt_debug @@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type) #define alloc_debug(...) {} #endif +#ifdef ALLOCBINDDBG +#define bind_info igt_info +#define bind_debug igt_debug +#else +#define bind_info(...) {} +#define bind_debug(...) {} +#endif + /* * We limit allocator space to avoid hang when batch would be * pinned in the last page. @@ -64,6 +72,30 @@ struct handle_entry { struct allocator *al; }; +/* For tracking alloc()/free() for Xe */ +struct ahnd_info { + int fd; + uint64_t ahnd; + uint32_t vm; + enum intel_driver driver; + struct igt_map *bind_map; + pthread_mutex_t bind_map_mutex; +}; + +enum allocator_bind_op { + BOUND, + TO_BIND, + TO_UNBIND, +}; + +struct allocator_object { + uint32_t handle; + uint64_t offset; + uint64_t size; + + enum allocator_bind_op bind_op; +}; + struct intel_allocator * intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); struct intel_allocator * @@ -122,6 +154,13 @@ static pid_t allocator_pid = -1; extern pid_t child_pid; extern __thread pid_t child_tid; +/* + * Track alloc()/free() requires storing in local process which has + * an access to real drm fd it can work on. + */ +extern struct igt_map *ahnd_map; +extern pthread_mutex_t ahnd_map_mutex; + /* * - for parent process we have child_pid == -1 * - for child which calls intel_allocator_init() allocator_pid == child_pid @@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void) } } +static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm) +{ + struct ahnd_info *ainfo; + + pthread_mutex_lock(&ahnd_map_mutex); + ainfo = igt_map_search(ahnd_map, &ahnd); + if (!ainfo) { + ainfo = malloc(sizeof(*ainfo)); + ainfo->fd = fd; + ainfo->ahnd = ahnd; + ainfo->vm = vm; + ainfo->driver = get_intel_driver(fd); + ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32); + pthread_mutex_init(&ainfo->bind_map_mutex, NULL); + bind_debug("[TRACK AHND] pid: %d, tid: %d, create \n", + getpid(), gettid(), ainfo->fd, + (long long)ainfo->ahnd, ainfo->vm, + ainfo->driver, ahnd_map, ainfo->bind_map); + igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo); + } + + pthread_mutex_unlock(&ahnd_map_mutex); +} + +static void untrack_ahnd(uint64_t ahnd) +{ + struct ahnd_info *ainfo; + + pthread_mutex_lock(&ahnd_map_mutex); + ainfo = igt_map_search(ahnd_map, &ahnd); + if (ainfo) { + bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n", + getpid(), gettid(), (long long)ahnd); + igt_map_remove(ahnd_map, &ahnd, map_entry_free_func); + } + pthread_mutex_unlock(&ahnd_map_mutex); +} + static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, uint32_t vm, uint64_t start, uint64_t end, @@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, igt_assert(resp.open.allocator_handle); igt_assert(resp.response_type == RESP_OPEN); + /* + * Igts mostly uses ctx as id when opening the allocator (i915 legacy). + * If ctx is passed let's use it as an vm id, otherwise use vm. + */ + track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm); + return resp.open.allocator_handle; } @@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle) igt_assert(handle_request(&req, &resp) == 0); igt_assert(resp.response_type == RESP_CLOSE); + untrack_ahnd(allocator_handle); + return resp.close.is_empty; } @@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle, *endp = resp.address_range.end; } +static bool is_same(struct allocator_object *obj, + uint32_t handle, uint64_t offset, uint64_t size, + enum allocator_bind_op bind_op) +{ + return obj->handle == handle && obj->offset == offset && obj->size == size && + (obj->bind_op == bind_op || obj->bind_op == BOUND); +} + +static void track_object(uint64_t allocator_handle, uint32_t handle, + uint64_t offset, uint64_t size, + enum allocator_bind_op bind_op) +{ + struct ahnd_info *ainfo; + struct allocator_object *obj; + + bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n", + bind_op == TO_BIND ? "BIND" : "UNBIND", + getpid(), gettid(), + (long long)allocator_handle, + handle, (long long)offset, (long long)size); + + if (offset == ALLOC_INVALID_ADDRESS) { + bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n", + (long long)offset); + return; + } + + pthread_mutex_lock(&ahnd_map_mutex); + ainfo = igt_map_search(ahnd_map, &allocator_handle); + pthread_mutex_unlock(&ahnd_map_mutex); + igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n", + (long long)allocator_handle); + + if (ainfo->driver == INTEL_DRIVER_I915) + return; /* no-op for i915, at least for now */ + + pthread_mutex_lock(&ainfo->bind_map_mutex); + obj = igt_map_search(ainfo->bind_map, &handle); + if (obj) { + /* + * User may call alloc() couple of times, check object is the + * same. For free() there's simple case, just remove from + * bind_map. + */ + if (bind_op == TO_BIND) { + igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true); + } else if (bind_op == TO_UNBIND) { + if (obj->bind_op == TO_BIND) + igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func); + else if (obj->bind_op == BOUND) + obj->bind_op = bind_op; + } + } else { + /* Ignore to unbind bo which wasn't previously inserted */ + if (bind_op == TO_UNBIND) + goto out; + + obj = calloc(1, sizeof(*obj)); + obj->handle = handle; + obj->offset = offset; + obj->size = size; + obj->bind_op = bind_op; + igt_map_insert(ainfo->bind_map, &obj->handle, obj); + } +out: + pthread_mutex_unlock(&ainfo->bind_map_mutex); +} + /** * __intel_allocator_alloc: * @allocator_handle: handle to an allocator @@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, igt_assert(handle_request(&req, &resp) == 0); igt_assert(resp.response_type == RESP_ALLOC); + track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND); + return resp.alloc.offset; } @@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle) igt_assert(handle_request(&req, &resp) == 0); igt_assert(resp.response_type == RESP_FREE); + track_object(allocator_handle, handle, 0, 0, TO_UNBIND); + return resp.free.freed; } @@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle) } } +static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out) +{ + struct allocator_object *obj; + struct igt_map_entry *pos; + struct igt_list_head obj_list; + struct xe_object *entry, *tmp; + + IGT_INIT_LIST_HEAD(&obj_list); + + pthread_mutex_lock(&ainfo->bind_map_mutex); + igt_map_foreach(ainfo->bind_map, pos) { + obj = pos->data; + + if (obj->bind_op == BOUND) + continue; + + bind_info("= [vm: %u] %s => %u %lx %lx\n", + ainfo->vm, + obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND", + obj->handle, obj->offset, + obj->size); + + entry = malloc(sizeof(*entry)); + entry->handle = obj->handle; + entry->offset = obj->offset; + entry->size = obj->size; + entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND : + XE_OBJECT_UNBIND; + igt_list_add(&entry->link, &obj_list); + + /* + * We clean bind_map even before calling bind/unbind + * as all binding operations asserts in case of error. + */ + if (obj->bind_op == TO_BIND) + obj->bind_op = BOUND; + else + igt_map_remove(ainfo->bind_map, &obj->handle, + map_entry_free_func); + } + pthread_mutex_unlock(&ainfo->bind_map_mutex); + + xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out); + + igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) { + igt_list_del(&entry->link); + free(entry); + } +} + +/** + * intel_allocator_bind: + * @allocator_handle: handle to an allocator + * @sync_in: syncobj (fence-in) + * @sync_out: syncobj (fence-out) + * + * Function binds and unbinds all objects added to the allocator which weren't + * previously binded/unbinded. + * + **/ +void intel_allocator_bind(uint64_t allocator_handle, + uint32_t sync_in, uint32_t sync_out) +{ + struct ahnd_info *ainfo; + + pthread_mutex_lock(&ahnd_map_mutex); + ainfo = igt_map_search(ahnd_map, &allocator_handle); + pthread_mutex_unlock(&ahnd_map_mutex); + igt_assert(ainfo); + + /* + * We collect bind/unbind operations on alloc()/free() to do group + * operation getting @sync_in as syncobj handle (fence-in). If user + * passes 0 as @sync_out we bind/unbind synchronously. + */ + __xe_op_bind(ainfo, sync_in, sync_out); +} + static int equal_handles(const void *key1, const void *key2) { const struct handle_entry *h1 = key1, *h2 = key2; @@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators) igt_map_destroy(map, map_entry_free_func); } +static void __free_ahnd_map(void) +{ + struct igt_map_entry *pos; + struct ahnd_info *ainfo; + + if (!ahnd_map) + return; + + igt_map_foreach(ahnd_map, pos) { + ainfo = pos->data; + igt_map_destroy(ainfo->bind_map, map_entry_free_func); + } + + igt_map_destroy(ahnd_map, map_entry_free_func); +} + /** * intel_allocator_init: * @@ -1400,12 +1652,15 @@ void intel_allocator_init(void) __free_maps(handles, true); __free_maps(ctx_map, false); __free_maps(vm_map, false); + __free_ahnd_map(); atomic_init(&next_handle, 1); handles = igt_map_create(hash_handles, equal_handles); ctx_map = igt_map_create(hash_instance, equal_ctx); vm_map = igt_map_create(hash_instance, equal_vm); - igt_assert(handles && ctx_map && vm_map); + pthread_mutex_init(&ahnd_map_mutex, NULL); + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); + igt_assert(handles && ctx_map && vm_map && ahnd_map); channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE); } diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h index 3ec74f6191..f9ff7f1cc9 100644 --- a/lib/intel_allocator.h +++ b/lib/intel_allocator.h @@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle, void intel_allocator_print(uint64_t allocator_handle); +void intel_allocator_bind(uint64_t allocator_handle, + uint32_t sync_in, uint32_t sync_out); + #define ALLOC_INVALID_ADDRESS (-1ull) #define INTEL_ALLOCATOR_NONE 0 #define INTEL_ALLOCATOR_RELOC 1 -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0DE9610E37C for ; Tue, 11 Jul 2023 11:20:56 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:03 +0200 Message-Id: <20230711112009.122482-12-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 11/17] lib/intel_ctx: Add xe context information List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Most complicated part in adopting i915_blt to intel_blt - which should handle both drivers - is how to achieve pipelined execution. In term pipelined execution I mean all gpu workloads are executed without stalls. Comparing to i915 relocations and softpinning xe architecture migrates binding (this means also unbind operation) responsibility from the kernel to user via vm_bind ioctl(). To avoid stalls user has to provide in/out fences (syncobjs) between consecutive bindings/execs. Of course for many igt tests we don't need pipelined execution, just synchronous bind, then exec. But exercising the driver should also cover pipelining to verify it is possible to work without stalls. I decided to extend intel_ctx_t with all necessary for xe objects (vm, engine, syncobjs) to get flexibility in deciding how to bind, execute and wait for (synchronize) those operations. Context object along with i915 engine is already passed to blitter library so adding xe required fields doesn't break i915 but will allow xe path to get all necessary data to execute. Using intel_ctx with xe requires some code patterns caused by usage of an allocator. For xe the allocator started tracking alloc()/free() operations to do bind/unbind in one call just before execution. I've added two helpers in intel_ctx which - intel_ctx_xe_exec() and intel_ctx_xe_sync(). Depending how intel_ctx was created (with 0 or real syncobj handles as in/bind/out fences) bind and exec in intel_ctx_xe_exec() are pipelined but synchronize last operation (exec). For real syncobjs they are used to join bind + exec calls but there's no wait for exec (sync-out) completion. This allows building more cascaded bind + exec operations without stalls. To wait for a sync-out fence caller may use intel_ctx_xe_sync() which is synchronous wait on syncobj. It allows user to reset fences to prepare for next operation. Signed-off-by: Zbigniew Kempczyński --- v3: drop local __xe_exec() (Karolina) --- lib/intel_ctx.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++- lib/intel_ctx.h | 14 +++++++ 2 files changed, 111 insertions(+), 1 deletion(-) diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c index ded9c0f1e4..0c1ce6d10b 100644 --- a/lib/intel_ctx.c +++ b/lib/intel_ctx.c @@ -5,9 +5,12 @@ #include +#include "i915/gem_engine_topology.h" +#include "igt_syncobj.h" +#include "intel_allocator.h" #include "intel_ctx.h" #include "ioctl_wrappers.h" -#include "i915/gem_engine_topology.h" +#include "xe/xe_ioctl.h" /** * SECTION:intel_ctx @@ -390,3 +393,96 @@ unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine) { return intel_ctx_cfg_engine_class(&ctx->cfg, engine); } + +/** + * intel_ctx_xe: + * @fd: open i915 drm file descriptor + * @vm: vm + * @engine: engine + * + * Returns an intel_ctx_t representing the xe context. + */ +intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine, + uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out) +{ + intel_ctx_t *ctx; + + ctx = calloc(1, sizeof(*ctx)); + igt_assert(ctx); + + ctx->fd = fd; + ctx->vm = vm; + ctx->engine = engine; + ctx->sync_in = sync_in; + ctx->sync_bind = sync_bind; + ctx->sync_out = sync_out; + + return ctx; +} + +int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset) +{ + struct drm_xe_sync syncs[2] = { + { .flags = DRM_XE_SYNC_SYNCOBJ, }, + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, + }; + struct drm_xe_exec exec = { + .engine_id = ctx->engine, + .syncs = (uintptr_t)syncs, + .num_syncs = 2, + .address = bb_offset, + .num_batch_buffer = 1, + }; + uint32_t sync_in = ctx->sync_in; + uint32_t sync_bind = ctx->sync_bind ?: syncobj_create(ctx->fd, 0); + uint32_t sync_out = ctx->sync_out ?: syncobj_create(ctx->fd, 0); + int ret; + + /* Synchronize allocator state -> vm */ + intel_allocator_bind(ahnd, sync_in, sync_bind); + + /* Pipelined exec */ + syncs[0].handle = sync_bind; + syncs[1].handle = sync_out; + + ret = __xe_exec(ctx->fd, &exec); + if (ret) + goto err; + + if (!ctx->sync_bind || !ctx->sync_out) + syncobj_wait_err(ctx->fd, &sync_out, 1, INT64_MAX, 0); + +err: + if (!ctx->sync_bind) + syncobj_destroy(ctx->fd, sync_bind); + + if (!ctx->sync_out) + syncobj_destroy(ctx->fd, sync_out); + + return ret; +} + +void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset) +{ + igt_assert_eq(__intel_ctx_xe_exec(ctx, ahnd, bb_offset), 0); +} + +#define RESET_SYNCOBJ(__fd, __sync) do { \ + if (__sync) \ + syncobj_reset((__fd), &(__sync), 1); \ +} while (0) + +int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs) +{ + int ret; + + ret = syncobj_wait_err(ctx->fd, &ctx->sync_out, 1, INT64_MAX, 0); + + if (reset_syncs) { + RESET_SYNCOBJ(ctx->fd, ctx->sync_in); + RESET_SYNCOBJ(ctx->fd, ctx->sync_bind); + RESET_SYNCOBJ(ctx->fd, ctx->sync_out); + } + + return ret; +} diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h index 3cfeaae81e..59d0360ada 100644 --- a/lib/intel_ctx.h +++ b/lib/intel_ctx.h @@ -67,6 +67,14 @@ int intel_ctx_cfg_engine_class(const intel_ctx_cfg_t *cfg, unsigned int engine); typedef struct intel_ctx { uint32_t id; intel_ctx_cfg_t cfg; + + /* Xe */ + int fd; + uint32_t vm; + uint32_t engine; + uint32_t sync_in; + uint32_t sync_bind; + uint32_t sync_out; } intel_ctx_t; int __intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg, @@ -81,4 +89,10 @@ void intel_ctx_destroy(int fd, const intel_ctx_t *ctx); unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine); +intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine, + uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out); +int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset); +void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset); +int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs); + #endif -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8543110E383 for ; Tue, 11 Jul 2023 11:20:59 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:04 +0200 Message-Id: <20230711112009.122482-13-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 12/17] lib/intel_blt: Introduce blt_copy_init() helper to cache driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Instead of calling is_xe_device() and is_i915_device() multiple times in code which distincs xe and i915 paths add driver field to structures used in blitter library. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- lib/igt_fb.c | 2 +- lib/intel_blt.c | 40 +++++++++++++++++++++++++++++++--- lib/intel_blt.h | 8 ++++++- tests/i915/gem_ccs.c | 34 ++++++++++++++++------------- tests/i915/gem_exercise_blt.c | 22 ++++++++++--------- tests/i915/gem_lmem_swapping.c | 4 ++-- 6 files changed, 78 insertions(+), 32 deletions(-) diff --git a/lib/igt_fb.c b/lib/igt_fb.c index a8988274f2..1814e8db11 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -2900,7 +2900,7 @@ static void blitcopy(const struct igt_fb *dst_fb, src = blt_fb_init(src_fb, i, mem_region); dst = blt_fb_init(dst_fb, i, mem_region); - memset(&blt, 0, sizeof(blt)); + blt_copy_init(src_fb->fd, &blt); blt.color_depth = blt_get_bpp(src_fb); blt_set_copy_object(&blt.src, src); blt_set_copy_object(&blt.dst, dst); diff --git a/lib/intel_blt.c b/lib/intel_blt.c index bc28f15e8d..f2f86e4947 100644 --- a/lib/intel_blt.c +++ b/lib/intel_blt.c @@ -692,6 +692,22 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data) data->dw21.src_array_index); } +/** + * blt_copy_init: + * @fd: drm fd + * @blt: structure for initialization + * + * Function is zeroing @blt and sets fd and driver fields (INTEL_DRIVER_I915 or + * INTEL_DRIVER_XE). + */ +void blt_copy_init(int fd, struct blt_copy_data *blt) +{ + memset(blt, 0, sizeof(*blt)); + + blt->fd = fd; + blt->driver = get_intel_driver(fd); +} + /** * emit_blt_block_copy: * @fd: drm fd @@ -889,6 +905,22 @@ static void dump_bb_surf_ctrl_cmd(const struct gen12_ctrl_surf_copy_data *data) cmd[4], data->dw04.dst_address_hi, data->dw04.dst_mocs); } +/** + * blt_ctrl_surf_copy_init: + * @fd: drm fd + * @surf: structure for initialization + * + * Function is zeroing @surf and sets fd and driver fields (INTEL_DRIVER_I915 or + * INTEL_DRIVER_XE). + */ +void blt_ctrl_surf_copy_init(int fd, struct blt_ctrl_surf_copy_data *surf) +{ + memset(surf, 0, sizeof(*surf)); + + surf->fd = fd; + surf->driver = get_intel_driver(fd); +} + /** * emit_blt_ctrl_surf_copy: * @fd: drm fd @@ -1317,7 +1349,7 @@ void blt_set_batch(struct blt_copy_batch *batch, } struct blt_copy_object * -blt_create_object(int fd, uint32_t region, +blt_create_object(const struct blt_copy_data *blt, uint32_t region, uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs, enum blt_tiling_type tiling, enum blt_compression compression, @@ -1329,10 +1361,12 @@ blt_create_object(int fd, uint32_t region, uint32_t stride = tiling == T_LINEAR ? width * 4 : width; uint32_t handle; + igt_assert_f(blt->driver, "Driver isn't set, have you called blt_copy_init()?\n"); + obj = calloc(1, sizeof(*obj)); obj->size = size; - igt_assert(__gem_create_in_memory_regions(fd, &handle, + igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, &size, region) == 0); blt_set_object(obj, handle, size, region, mocs, tiling, @@ -1340,7 +1374,7 @@ blt_create_object(int fd, uint32_t region, blt_set_geom(obj, stride, 0, 0, width, height, 0, 0); if (create_mapping) - obj->ptr = gem_mmap__device_coherent(fd, handle, 0, size, + obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size, PROT_READ | PROT_WRITE); return obj; diff --git a/lib/intel_blt.h b/lib/intel_blt.h index 9c4ddc7a89..7516ce8ac7 100644 --- a/lib/intel_blt.h +++ b/lib/intel_blt.h @@ -102,6 +102,7 @@ struct blt_copy_batch { /* Common for block-copy and fast-copy */ struct blt_copy_data { int fd; + enum intel_driver driver; struct blt_copy_object src; struct blt_copy_object dst; struct blt_copy_batch bb; @@ -155,6 +156,7 @@ struct blt_ctrl_surf_copy_object { struct blt_ctrl_surf_copy_data { int fd; + enum intel_driver driver; struct blt_ctrl_surf_copy_object src; struct blt_ctrl_surf_copy_object dst; struct blt_copy_batch bb; @@ -185,6 +187,8 @@ bool blt_uses_extended_block_copy(int fd); const char *blt_tiling_name(enum blt_tiling_type tiling); +void blt_copy_init(int fd, struct blt_copy_data *blt); + uint64_t emit_blt_block_copy(int fd, uint64_t ahnd, const struct blt_copy_data *blt, @@ -205,6 +209,8 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, uint64_t bb_pos, bool emit_bbe); +void blt_ctrl_surf_copy_init(int fd, struct blt_ctrl_surf_copy_data *surf); + int blt_ctrl_surf_copy(int fd, const intel_ctx_t *ctx, const struct intel_execution_engine2 *e, @@ -230,7 +236,7 @@ void blt_set_batch(struct blt_copy_batch *batch, uint32_t handle, uint64_t size, uint32_t region); struct blt_copy_object * -blt_create_object(int fd, uint32_t region, +blt_create_object(const struct blt_copy_data *blt, uint32_t region, uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs, enum blt_tiling_type tiling, enum blt_compression compression, diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c index f9ad9267df..d9d785ed9b 100644 --- a/tests/i915/gem_ccs.c +++ b/tests/i915/gem_ccs.c @@ -167,7 +167,7 @@ static void surf_copy(int i915, ccs = gem_create(i915, ccssize); ccs2 = gem_create(i915, ccssize); - surf.fd = i915; + blt_ctrl_surf_copy_init(i915, &surf); surf.print_bb = param.print_bb; set_surf_object(&surf.src, mid->handle, mid->region, mid->size, uc_mocs, BLT_INDIRECT_ACCESS); @@ -219,7 +219,7 @@ static void surf_copy(int i915, uc_mocs, INDIRECT_ACCESS); blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf); - memset(&blt, 0, sizeof(blt)); + blt_copy_init(i915, &blt); blt.color_depth = CD_32bit; blt.print_bb = param.print_bb; blt_set_copy_object(&blt.src, mid); @@ -310,7 +310,7 @@ static int blt_block_copy3(int i915, bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment); /* First blit src -> mid */ - memset(&blt0, 0, sizeof(blt0)); + blt_copy_init(i915, &blt0); blt0.src = blt3->src; blt0.dst = blt3->mid; blt0.bb = blt3->bb; @@ -321,7 +321,7 @@ static int blt_block_copy3(int i915, bb_pos = emit_blt_block_copy(i915, ahnd, &blt0, &ext0, bb_pos, false); /* Second blit mid -> dst */ - memset(&blt0, 0, sizeof(blt0)); + blt_copy_init(i915, &blt0); blt0.src = blt3->mid; blt0.dst = blt3->dst; blt0.bb = blt3->bb; @@ -332,7 +332,7 @@ static int blt_block_copy3(int i915, bb_pos = emit_blt_block_copy(i915, ahnd, &blt0, &ext0, bb_pos, false); /* Third blit dst -> final */ - memset(&blt0, 0, sizeof(blt0)); + blt_copy_init(i915, &blt0); blt0.src = blt3->dst; blt0.dst = blt3->final; blt0.bb = blt3->bb; @@ -390,11 +390,13 @@ static void block_copy(int i915, if (!blt_uses_extended_block_copy(i915)) pext = NULL; - src = blt_create_object(i915, region1, width, height, bpp, uc_mocs, + blt_copy_init(i915, &blt); + + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, T_LINEAR, COMPRESSION_DISABLED, comp_type, true); - mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs, + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs, mid_tiling, mid_compression, comp_type, true); - dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs, + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, T_LINEAR, COMPRESSION_DISABLED, comp_type, true); igt_assert(src->size == dst->size); PRINT_SURFACE_INFO("src", src); @@ -404,7 +406,6 @@ static void block_copy(int i915, blt_surface_fill_rect(i915, src, width, height); WRITE_PNG(i915, run_id, "src", src, width, height); - memset(&blt, 0, sizeof(blt)); blt.color_depth = CD_32bit; blt.print_bb = param.print_bb; blt_set_copy_object(&blt.src, src); @@ -449,7 +450,7 @@ static void block_copy(int i915, } } - memset(&blt, 0, sizeof(blt)); + blt_copy_init(i915, &blt); blt.color_depth = CD_32bit; blt.print_bb = param.print_bb; blt_set_copy_object(&blt.src, mid); @@ -486,6 +487,7 @@ static void block_multicopy(int i915, const struct test_config *config) { struct blt_copy3_data blt3 = {}; + struct blt_copy_data blt = {}; struct blt_block_copy3_data_ext ext3 = {}, *pext3 = &ext3; struct blt_copy_object *src, *mid, *dst, *final; const uint32_t bpp = 32; @@ -505,13 +507,16 @@ static void block_multicopy(int i915, if (!blt_uses_extended_block_copy(i915)) pext3 = NULL; - src = blt_create_object(i915, region1, width, height, bpp, uc_mocs, + /* For object creation */ + blt_copy_init(i915, &blt); + + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, T_LINEAR, COMPRESSION_DISABLED, comp_type, true); - mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs, + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs, mid_tiling, mid_compression, comp_type, true); - dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs, + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, mid_tiling, COMPRESSION_DISABLED, comp_type, true); - final = blt_create_object(i915, region1, width, height, bpp, uc_mocs, + final = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, T_LINEAR, COMPRESSION_DISABLED, comp_type, true); igt_assert(src->size == dst->size); PRINT_SURFACE_INFO("src", src); @@ -521,7 +526,6 @@ static void block_multicopy(int i915, blt_surface_fill_rect(i915, src, width, height); - memset(&blt3, 0, sizeof(blt3)); blt3.color_depth = CD_32bit; blt3.print_bb = param.print_bb; blt_set_copy_object(&blt3.src, src); diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c index 0cd1820430..7355eabbe9 100644 --- a/tests/i915/gem_exercise_blt.c +++ b/tests/i915/gem_exercise_blt.c @@ -89,7 +89,7 @@ static int fast_copy_one_bb(int i915, bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); /* First blit */ - memset(&blt_tmp, 0, sizeof(blt_tmp)); + blt_copy_init(i915, &blt_tmp); blt_tmp.src = blt->src; blt_tmp.dst = blt->mid; blt_tmp.bb = blt->bb; @@ -98,7 +98,7 @@ static int fast_copy_one_bb(int i915, bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, false); /* Second blit */ - memset(&blt_tmp, 0, sizeof(blt_tmp)); + blt_copy_init(i915, &blt_tmp); blt_tmp.src = blt->mid; blt_tmp.dst = blt->dst; blt_tmp.bb = blt->bb; @@ -140,6 +140,7 @@ static void fast_copy_emit(int i915, const intel_ctx_t *ctx, uint32_t region1, uint32_t region2, enum blt_tiling_type mid_tiling) { + struct blt_copy_data bltinit = {}; struct blt_fast_copy_data blt = {}; struct blt_copy_object *src, *mid, *dst; const uint32_t bpp = 32; @@ -152,11 +153,12 @@ static void fast_copy_emit(int i915, const intel_ctx_t *ctx, igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0); - src = blt_create_object(i915, region1, width, height, bpp, 0, + blt_copy_init(i915, &bltinit); + src = blt_create_object(&bltinit, region1, width, height, bpp, 0, T_LINEAR, COMPRESSION_DISABLED, 0, true); - mid = blt_create_object(i915, region2, width, height, bpp, 0, + mid = blt_create_object(&bltinit, region2, width, height, bpp, 0, mid_tiling, COMPRESSION_DISABLED, 0, true); - dst = blt_create_object(i915, region1, width, height, bpp, 0, + dst = blt_create_object(&bltinit, region1, width, height, bpp, 0, T_LINEAR, COMPRESSION_DISABLED, 0, true); igt_assert(src->size == dst->size); @@ -212,17 +214,17 @@ static void fast_copy(int i915, const intel_ctx_t *ctx, igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0); - src = blt_create_object(i915, region1, width, height, bpp, 0, + blt_copy_init(i915, &blt); + src = blt_create_object(&blt, region1, width, height, bpp, 0, T_LINEAR, COMPRESSION_DISABLED, 0, true); - mid = blt_create_object(i915, region2, width, height, bpp, 0, + mid = blt_create_object(&blt, region2, width, height, bpp, 0, mid_tiling, COMPRESSION_DISABLED, 0, true); - dst = blt_create_object(i915, region1, width, height, bpp, 0, + dst = blt_create_object(&blt, region1, width, height, bpp, 0, T_LINEAR, COMPRESSION_DISABLED, 0, true); igt_assert(src->size == dst->size); blt_surface_fill_rect(i915, src, width, height); - memset(&blt, 0, sizeof(blt)); blt.color_depth = CD_32bit; blt.print_bb = param.print_bb; blt_set_copy_object(&blt.src, src); @@ -235,7 +237,7 @@ static void fast_copy(int i915, const intel_ctx_t *ctx, WRITE_PNG(i915, mid_tiling, "src", &blt.src, width, height); WRITE_PNG(i915, mid_tiling, "mid", &blt.dst, width, height); - memset(&blt, 0, sizeof(blt)); + blt_copy_init(i915, &blt); blt.color_depth = CD_32bit; blt.print_bb = param.print_bb; blt_set_copy_object(&blt.src, mid); diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c index 83dbebec83..2921de8f9f 100644 --- a/tests/i915/gem_lmem_swapping.c +++ b/tests/i915/gem_lmem_swapping.c @@ -308,7 +308,7 @@ init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp, buf[j] = seed++; munmap(buf, obj->size); - memset(&blt, 0, sizeof(blt)); + blt_copy_init(i915, &blt); blt.color_depth = CD_32bit; memcpy(&blt.src, tmp, sizeof(blt.src)); @@ -366,7 +366,7 @@ verify_object_ccs(int i915, const struct object *obj, cmd->handle = gem_create_from_pool(i915, &size, region); blt_set_batch(cmd, cmd->handle, size, region); - memset(&blt, 0, sizeof(blt)); + blt_copy_init(i915, &blt); blt.color_depth = CD_32bit; memcpy(&blt.src, obj->blt_obj, sizeof(blt.src)); -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78B6D10E387 for ; Tue, 11 Jul 2023 11:21:06 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:06 +0200 Message-Id: <20230711112009.122482-15-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 14/17] tests/xe_ccs: Check if flatccs is working with block-copy for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: This is ported to xe copy of i915 gem_ccs test. Ported means all driver dependent calls - like working on regions, binding and execution were replaced by xe counterparts. I wondered to add conditionals for xe in gem_ccs but this would decrease test readability so I dropped this idea. Signed-off-by: Zbigniew Kempczyński --- v3: Drop unused macro, use system_memory() instead REGION_SMEM in xe test (Karolina) --- tests/meson.build | 1 + tests/xe/xe_ccs.c | 757 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 758 insertions(+) create mode 100644 tests/xe/xe_ccs.c diff --git a/tests/meson.build b/tests/meson.build index d56e4c89da..da8653fabc 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -263,6 +263,7 @@ i915_progs = [ ] xe_progs = [ + 'xe_ccs', 'xe_create', 'xe_compute', 'xe_dma_buf_sync', diff --git a/tests/xe/xe_ccs.c b/tests/xe/xe_ccs.c new file mode 100644 index 0000000000..ee653790bf --- /dev/null +++ b/tests/xe/xe_ccs.c @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include "drm.h" +#include "igt.h" +#include "igt_syncobj.h" +#include "intel_blt.h" +#include "intel_mocs.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" +/** + * TEST: xe ccs + * Description: Exercise gen12 blitter with and without flatccs compression on Xe + * Run type: FULL + * + * SUBTEST: block-copy-compressed + * Description: Check block-copy flatccs compressed blit + * + * SUBTEST: block-copy-uncompressed + * Description: Check block-copy uncompressed blit + * + * SUBTEST: block-multicopy-compressed + * Description: Check block-multicopy flatccs compressed blit + * + * SUBTEST: block-multicopy-inplace + * Description: Check block-multicopy flatccs inplace decompression blit + * + * SUBTEST: ctrl-surf-copy + * Description: Check flatccs data can be copied from/to surface + * + * SUBTEST: ctrl-surf-copy-new-ctx + * Description: Check flatccs data are physically tagged and visible in vm + * + * SUBTEST: suspend-resume + * Description: Check flatccs data persists after suspend / resume (S0) + */ + +IGT_TEST_DESCRIPTION("Exercise gen12 blitter with and without flatccs compression on Xe"); + +static struct param { + int compression_format; + int tiling; + bool write_png; + bool print_bb; + bool print_surface_info; + int width; + int height; +} param = { + .compression_format = 0, + .tiling = -1, + .write_png = false, + .print_bb = false, + .print_surface_info = false, + .width = 512, + .height = 512, +}; + +struct test_config { + bool compression; + bool inplace; + bool surfcopy; + bool new_ctx; + bool suspend_resume; +}; + +static void set_surf_object(struct blt_ctrl_surf_copy_object *obj, + uint32_t handle, uint32_t region, uint64_t size, + uint8_t mocs, enum blt_access_type access_type) +{ + obj->handle = handle; + obj->region = region; + obj->size = size; + obj->mocs = mocs; + obj->access_type = access_type; +} + +#define PRINT_SURFACE_INFO(name, obj) do { \ + if (param.print_surface_info) \ + blt_surface_info((name), (obj)); } while (0) + +#define WRITE_PNG(fd, id, name, obj, w, h) do { \ + if (param.write_png) \ + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0) + +static int compare_nxn(const struct blt_copy_object *surf1, + const struct blt_copy_object *surf2, + int xsize, int ysize, int bx, int by) +{ + int x, y, corrupted; + uint32_t pos, px1, px2; + + corrupted = 0; + for (y = 0; y < ysize; y++) { + for (x = 0; x < xsize; x++) { + pos = bx * xsize + by * ysize * surf1->pitch / 4; + pos += x + y * surf1->pitch / 4; + px1 = surf1->ptr[pos]; + px2 = surf2->ptr[pos]; + if (px1 != px2) + corrupted++; + } + } + + return corrupted; +} + +static void dump_corruption_info(const struct blt_copy_object *surf1, + const struct blt_copy_object *surf2) +{ + const int xsize = 8, ysize = 8; + int w, h, bx, by, corrupted; + + igt_assert(surf1->x1 == surf2->x1 && surf1->x2 == surf2->x2); + igt_assert(surf1->y1 == surf2->y1 && surf1->y2 == surf2->y2); + w = surf1->x2; + h = surf1->y2; + + igt_info("dump corruption - width: %d, height: %d, sizex: %x, sizey: %x\n", + surf1->x2, surf1->y2, xsize, ysize); + + for (by = 0; by < h / ysize; by++) { + for (bx = 0; bx < w / xsize; bx++) { + corrupted = compare_nxn(surf1, surf2, xsize, ysize, bx, by); + if (corrupted == 0) + igt_info("."); + else + igt_info("%c", '0' + corrupted); + } + igt_info("\n"); + } +} + +static void surf_copy(int xe, + intel_ctx_t *ctx, + uint64_t ahnd, + const struct blt_copy_object *src, + const struct blt_copy_object *mid, + const struct blt_copy_object *dst, + int run_id, bool suspend_resume) +{ + struct blt_copy_data blt = {}; + struct blt_block_copy_data_ext ext = {}; + struct blt_ctrl_surf_copy_data surf = {}; + uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2; + uint64_t bb_size, ccssize = mid->size / CCS_RATIO; + uint32_t *ccscopy; + uint8_t uc_mocs = intel_get_uc_mocs(xe); + uint32_t sysmem = system_memory(xe); + int result; + + igt_assert(mid->compression); + ccscopy = (uint32_t *) malloc(ccssize); + ccs = xe_bo_create_flags(xe, 0, ccssize, sysmem); + ccs2 = xe_bo_create_flags(xe, 0, ccssize, sysmem); + + blt_ctrl_surf_copy_init(xe, &surf); + surf.print_bb = param.print_bb; + set_surf_object(&surf.src, mid->handle, mid->region, mid->size, + uc_mocs, BLT_INDIRECT_ACCESS); + set_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs, DIRECT_ACCESS); + bb_size = xe_get_default_alignment(xe); + bb1 = xe_bo_create_flags(xe, 0, bb_size, sysmem); + blt_set_batch(&surf.bb, bb1, bb_size, sysmem); + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); + intel_ctx_xe_sync(ctx, true); + + ccsmap = xe_bo_map(xe, ccs, surf.dst.size); + memcpy(ccscopy, ccsmap, ccssize); + + if (suspend_resume) { + char *orig, *orig2, *newsum, *newsum2; + + orig = g_compute_checksum_for_data(G_CHECKSUM_SHA1, + (void *)ccsmap, surf.dst.size); + orig2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1, + (void *)mid->ptr, mid->size); + + igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE, SUSPEND_TEST_NONE); + + set_surf_object(&surf.dst, ccs2, system_memory(xe), ccssize, + 0, DIRECT_ACCESS); + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); + intel_ctx_xe_sync(ctx, true); + + ccsmap2 = xe_bo_map(xe, ccs2, surf.dst.size); + newsum = g_compute_checksum_for_data(G_CHECKSUM_SHA1, + (void *)ccsmap2, surf.dst.size); + newsum2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1, + (void *)mid->ptr, mid->size); + + munmap(ccsmap2, ccssize); + igt_assert(!strcmp(orig, newsum)); + igt_assert(!strcmp(orig2, newsum2)); + g_free(orig); + g_free(orig2); + g_free(newsum); + g_free(newsum2); + } + + /* corrupt ccs */ + for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++) + ccsmap[i] = i; + set_surf_object(&surf.src, ccs, sysmem, ccssize, + uc_mocs, DIRECT_ACCESS); + set_surf_object(&surf.dst, mid->handle, mid->region, mid->size, + uc_mocs, INDIRECT_ACCESS); + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); + intel_ctx_xe_sync(ctx, true); + + blt_copy_init(xe, &blt); + blt.color_depth = CD_32bit; + blt.print_bb = param.print_bb; + blt_set_copy_object(&blt.src, mid); + blt_set_copy_object(&blt.dst, dst); + blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D); + blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D); + bb2 = xe_bo_create_flags(xe, 0, bb_size, sysmem); + blt_set_batch(&blt.bb, bb2, bb_size, sysmem); + blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext); + intel_ctx_xe_sync(ctx, true); + WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2); + result = memcmp(src->ptr, dst->ptr, src->size); + igt_assert(result != 0); + + /* retrieve back ccs */ + memcpy(ccsmap, ccscopy, ccssize); + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); + + blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext); + intel_ctx_xe_sync(ctx, true); + WRITE_PNG(xe, run_id, "corrected", &blt.dst, dst->x2, dst->y2); + result = memcmp(src->ptr, dst->ptr, src->size); + if (result) + dump_corruption_info(src, dst); + + munmap(ccsmap, ccssize); + gem_close(xe, ccs); + gem_close(xe, ccs2); + gem_close(xe, bb1); + gem_close(xe, bb2); + + igt_assert_f(result == 0, + "Source and destination surfaces are different after " + "restoring source ccs data\n"); +} + +struct blt_copy3_data { + int xe; + struct blt_copy_object src; + struct blt_copy_object mid; + struct blt_copy_object dst; + struct blt_copy_object final; + struct blt_copy_batch bb; + enum blt_color_depth color_depth; + + /* debug stuff */ + bool print_bb; +}; + +struct blt_block_copy3_data_ext { + struct blt_block_copy_object_ext src; + struct blt_block_copy_object_ext mid; + struct blt_block_copy_object_ext dst; + struct blt_block_copy_object_ext final; +}; + +static int blt_block_copy3(int xe, + const intel_ctx_t *ctx, + uint64_t ahnd, + const struct blt_copy3_data *blt3, + const struct blt_block_copy3_data_ext *ext3) +{ + struct blt_copy_data blt0; + struct blt_block_copy_data_ext ext0; + uint64_t bb_offset, alignment; + uint64_t bb_pos = 0; + int ret; + + igt_assert_f(ahnd, "block-copy3 supports softpin only\n"); + igt_assert_f(blt3, "block-copy3 requires data to do blit\n"); + + alignment = xe_get_default_alignment(xe); + get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment); + get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment); + get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment); + get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment); + bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment); + + /* First blit src -> mid */ + blt_copy_init(xe, &blt0); + blt0.src = blt3->src; + blt0.dst = blt3->mid; + blt0.bb = blt3->bb; + blt0.color_depth = blt3->color_depth; + blt0.print_bb = blt3->print_bb; + ext0.src = ext3->src; + ext0.dst = ext3->mid; + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false); + + /* Second blit mid -> dst */ + blt_copy_init(xe, &blt0); + blt0.src = blt3->mid; + blt0.dst = blt3->dst; + blt0.bb = blt3->bb; + blt0.color_depth = blt3->color_depth; + blt0.print_bb = blt3->print_bb; + ext0.src = ext3->mid; + ext0.dst = ext3->dst; + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false); + + /* Third blit dst -> final */ + blt_copy_init(xe, &blt0); + blt0.src = blt3->dst; + blt0.dst = blt3->final; + blt0.bb = blt3->bb; + blt0.color_depth = blt3->color_depth; + blt0.print_bb = blt3->print_bb; + ext0.src = ext3->dst; + ext0.dst = ext3->final; + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, true); + + intel_ctx_xe_exec(ctx, ahnd, bb_offset); + + return ret; +} + +static void block_copy(int xe, + intel_ctx_t *ctx, + uint32_t region1, uint32_t region2, + enum blt_tiling_type mid_tiling, + const struct test_config *config) +{ + struct blt_copy_data blt = {}; + struct blt_block_copy_data_ext ext = {}, *pext = &ext; + struct blt_copy_object *src, *mid, *dst; + const uint32_t bpp = 32; + uint64_t bb_size = xe_get_default_alignment(xe); + uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC); + uint32_t run_id = mid_tiling; + uint32_t mid_region = region2, bb; + uint32_t width = param.width, height = param.height; + enum blt_compression mid_compression = config->compression; + int mid_compression_format = param.compression_format; + enum blt_compression_type comp_type = COMPRESSION_TYPE_3D; + uint8_t uc_mocs = intel_get_uc_mocs(xe); + int result; + + bb = xe_bo_create_flags(xe, 0, bb_size, region1); + + if (!blt_uses_extended_block_copy(xe)) + pext = NULL; + + blt_copy_init(xe, &blt); + + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs, + mid_tiling, mid_compression, comp_type, true); + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); + igt_assert(src->size == dst->size); + PRINT_SURFACE_INFO("src", src); + PRINT_SURFACE_INFO("mid", mid); + PRINT_SURFACE_INFO("dst", dst); + + blt_surface_fill_rect(xe, src, width, height); + WRITE_PNG(xe, run_id, "src", src, width, height); + + blt.color_depth = CD_32bit; + blt.print_bb = param.print_bb; + blt_set_copy_object(&blt.src, src); + blt_set_copy_object(&blt.dst, mid); + blt_set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D); + blt_set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D); + blt_set_batch(&blt.bb, bb, bb_size, region1); + blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext); + intel_ctx_xe_sync(ctx, true); + + /* We expect mid != src if there's compression */ + if (mid->compression) + igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0); + + WRITE_PNG(xe, run_id, "mid", &blt.dst, width, height); + + if (config->surfcopy && pext) { + struct drm_xe_engine_class_instance inst = { + .engine_class = DRM_XE_ENGINE_CLASS_COPY, + }; + intel_ctx_t *surf_ctx = ctx; + uint64_t surf_ahnd = ahnd; + uint32_t vm, engine; + + if (config->new_ctx) { + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); + engine = xe_engine_create(xe, vm, &inst, 0); + surf_ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0); + surf_ahnd = intel_allocator_open(xe, surf_ctx->vm, + INTEL_ALLOCATOR_RELOC); + } + surf_copy(xe, surf_ctx, surf_ahnd, src, mid, dst, run_id, + config->suspend_resume); + + if (surf_ctx != ctx) { + xe_engine_destroy(xe, engine); + xe_vm_destroy(xe, vm); + free(surf_ctx); + put_ahnd(surf_ahnd); + } + } + + blt_copy_init(xe, &blt); + blt.color_depth = CD_32bit; + blt.print_bb = param.print_bb; + blt_set_copy_object(&blt.src, mid); + blt_set_copy_object(&blt.dst, dst); + blt_set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D); + blt_set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D); + if (config->inplace) { + blt_set_object(&blt.dst, mid->handle, dst->size, mid->region, 0, + T_LINEAR, COMPRESSION_DISABLED, comp_type); + blt.dst.ptr = mid->ptr; + } + + blt_set_batch(&blt.bb, bb, bb_size, region1); + blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext); + intel_ctx_xe_sync(ctx, true); + + WRITE_PNG(xe, run_id, "dst", &blt.dst, width, height); + + result = memcmp(src->ptr, blt.dst.ptr, src->size); + + /* Politely clean vm */ + put_offset(ahnd, src->handle); + put_offset(ahnd, mid->handle); + put_offset(ahnd, dst->handle); + put_offset(ahnd, bb); + intel_allocator_bind(ahnd, 0, 0); + blt_destroy_object(xe, src); + blt_destroy_object(xe, mid); + blt_destroy_object(xe, dst); + gem_close(xe, bb); + put_ahnd(ahnd); + + igt_assert_f(!result, "source and destination surfaces differs!\n"); +} + +static void block_multicopy(int xe, + intel_ctx_t *ctx, + uint32_t region1, uint32_t region2, + enum blt_tiling_type mid_tiling, + const struct test_config *config) +{ + struct blt_copy3_data blt3 = {}; + struct blt_copy_data blt = {}; + struct blt_block_copy3_data_ext ext3 = {}, *pext3 = &ext3; + struct blt_copy_object *src, *mid, *dst, *final; + const uint32_t bpp = 32; + uint64_t bb_size = xe_get_default_alignment(xe); + uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC); + uint32_t run_id = mid_tiling; + uint32_t mid_region = region2, bb; + uint32_t width = param.width, height = param.height; + enum blt_compression mid_compression = config->compression; + int mid_compression_format = param.compression_format; + enum blt_compression_type comp_type = COMPRESSION_TYPE_3D; + uint8_t uc_mocs = intel_get_uc_mocs(xe); + int result; + + bb = xe_bo_create_flags(xe, 0, bb_size, region1); + + if (!blt_uses_extended_block_copy(xe)) + pext3 = NULL; + + blt_copy_init(xe, &blt); + + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs, + mid_tiling, mid_compression, comp_type, true); + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, + mid_tiling, COMPRESSION_DISABLED, comp_type, true); + final = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); + igt_assert(src->size == dst->size); + PRINT_SURFACE_INFO("src", src); + PRINT_SURFACE_INFO("mid", mid); + PRINT_SURFACE_INFO("dst", dst); + PRINT_SURFACE_INFO("final", final); + + blt_surface_fill_rect(xe, src, width, height); + + blt3.color_depth = CD_32bit; + blt3.print_bb = param.print_bb; + blt_set_copy_object(&blt3.src, src); + blt_set_copy_object(&blt3.mid, mid); + blt_set_copy_object(&blt3.dst, dst); + blt_set_copy_object(&blt3.final, final); + + if (config->inplace) { + blt_set_object(&blt3.dst, mid->handle, dst->size, mid->region, + mid->mocs, mid_tiling, COMPRESSION_DISABLED, + comp_type); + blt3.dst.ptr = mid->ptr; + } + + blt_set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D); + blt_set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D); + blt_set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D); + blt_set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D); + blt_set_batch(&blt3.bb, bb, bb_size, region1); + + blt_block_copy3(xe, ctx, ahnd, &blt3, pext3); + intel_ctx_xe_sync(ctx, true); + + WRITE_PNG(xe, run_id, "src", &blt3.src, width, height); + if (!config->inplace) + WRITE_PNG(xe, run_id, "mid", &blt3.mid, width, height); + WRITE_PNG(xe, run_id, "dst", &blt3.dst, width, height); + WRITE_PNG(xe, run_id, "final", &blt3.final, width, height); + + result = memcmp(src->ptr, blt3.final.ptr, src->size); + + put_offset(ahnd, src->handle); + put_offset(ahnd, mid->handle); + put_offset(ahnd, dst->handle); + put_offset(ahnd, final->handle); + put_offset(ahnd, bb); + intel_allocator_bind(ahnd, 0, 0); + blt_destroy_object(xe, src); + blt_destroy_object(xe, mid); + blt_destroy_object(xe, dst); + blt_destroy_object(xe, final); + gem_close(xe, bb); + put_ahnd(ahnd); + + igt_assert_f(!result, "source and destination surfaces differs!\n"); +} + +enum copy_func { + BLOCK_COPY, + BLOCK_MULTICOPY, +}; + +static const struct { + const char *suffix; + void (*copyfn)(int fd, + intel_ctx_t *ctx, + uint32_t region1, uint32_t region2, + enum blt_tiling_type btype, + const struct test_config *config); +} copyfns[] = { + [BLOCK_COPY] = { "", block_copy }, + [BLOCK_MULTICOPY] = { "-multicopy", block_multicopy }, +}; + +static void block_copy_test(int xe, + const struct test_config *config, + struct igt_collection *set, + enum copy_func copy_function) +{ + struct drm_xe_engine_class_instance inst = { + .engine_class = DRM_XE_ENGINE_CLASS_COPY, + }; + intel_ctx_t *ctx; + struct igt_collection *regions; + uint32_t vm, engine; + int tiling; + + if (config->compression && !blt_block_copy_supports_compression(xe)) + return; + + if (config->inplace && !config->compression) + return; + + for_each_tiling(tiling) { + if (!blt_block_copy_supports_tiling(xe, tiling) || + (param.tiling >= 0 && param.tiling != tiling)) + continue; + + for_each_variation_r(regions, 2, set) { + uint32_t region1, region2; + char *regtxt; + + region1 = igt_collection_get_value(regions, 0); + region2 = igt_collection_get_value(regions, 1); + + /* Compressed surface must be in device memory */ + if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2)) + continue; + + regtxt = xe_memregion_dynamic_subtest_name(xe, regions); + + igt_dynamic_f("%s-%s-compfmt%d-%s%s", + blt_tiling_name(tiling), + config->compression ? + "compressed" : "uncompressed", + param.compression_format, regtxt, + copyfns[copy_function].suffix) { + uint32_t sync_bind, sync_out; + + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); + engine = xe_engine_create(xe, vm, &inst, 0); + sync_bind = syncobj_create(xe, 0); + sync_out = syncobj_create(xe, 0); + ctx = intel_ctx_xe(xe, vm, engine, + 0, sync_bind, sync_out); + + copyfns[copy_function].copyfn(xe, ctx, + region1, region2, + tiling, config); + + xe_engine_destroy(xe, engine); + xe_vm_destroy(xe, vm); + syncobj_destroy(xe, sync_bind); + syncobj_destroy(xe, sync_out); + free(ctx); + } + + free(regtxt); + } + } +} + +static int opt_handler(int opt, int opt_index, void *data) +{ + switch (opt) { + case 'b': + param.print_bb = true; + igt_debug("Print bb: %d\n", param.print_bb); + break; + case 'f': + param.compression_format = atoi(optarg); + igt_debug("Compression format: %d\n", param.compression_format); + igt_assert((param.compression_format & ~0x1f) == 0); + break; + case 'p': + param.write_png = true; + igt_debug("Write png: %d\n", param.write_png); + break; + case 's': + param.print_surface_info = true; + igt_debug("Print surface info: %d\n", param.print_surface_info); + break; + case 't': + param.tiling = atoi(optarg); + igt_debug("Tiling: %d\n", param.tiling); + break; + case 'W': + param.width = atoi(optarg); + igt_debug("Width: %d\n", param.width); + break; + case 'H': + param.height = atoi(optarg); + igt_debug("Height: %d\n", param.height); + break; + default: + return IGT_OPT_HANDLER_ERROR; + } + + return IGT_OPT_HANDLER_SUCCESS; +} + +const char *help_str = + " -b\tPrint bb\n" + " -f\tCompression format (0-31)\n" + " -p\tWrite PNG\n" + " -s\tPrint surface info\n" + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n" + " -W\tWidth (default 512)\n" + " -H\tHeight (default 512)" + ; + +igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL) +{ + struct igt_collection *set; + int xe; + + igt_fixture { + xe = drm_open_driver(DRIVER_XE); + igt_require(blt_has_block_copy(xe)); + + xe_device_get(xe); + + set = xe_get_memory_region_set(xe, + XE_MEM_REGION_CLASS_SYSMEM, + XE_MEM_REGION_CLASS_VRAM); + } + + igt_describe("Check block-copy uncompressed blit"); + igt_subtest_with_dynamic("block-copy-uncompressed") { + struct test_config config = {}; + + block_copy_test(xe, &config, set, BLOCK_COPY); + } + + igt_describe("Check block-copy flatccs compressed blit"); + igt_subtest_with_dynamic("block-copy-compressed") { + struct test_config config = { .compression = true }; + + block_copy_test(xe, &config, set, BLOCK_COPY); + } + + igt_describe("Check block-multicopy flatccs compressed blit"); + igt_subtest_with_dynamic("block-multicopy-compressed") { + struct test_config config = { .compression = true }; + + block_copy_test(xe, &config, set, BLOCK_MULTICOPY); + } + + igt_describe("Check block-multicopy flatccs inplace decompression blit"); + igt_subtest_with_dynamic("block-multicopy-inplace") { + struct test_config config = { .compression = true, + .inplace = true }; + + block_copy_test(xe, &config, set, BLOCK_MULTICOPY); + } + + igt_describe("Check flatccs data can be copied from/to surface"); + igt_subtest_with_dynamic("ctrl-surf-copy") { + struct test_config config = { .compression = true, + .surfcopy = true }; + + block_copy_test(xe, &config, set, BLOCK_COPY); + } + + igt_describe("Check flatccs data are physically tagged and visible" + " in different contexts"); + igt_subtest_with_dynamic("ctrl-surf-copy-new-ctx") { + struct test_config config = { .compression = true, + .surfcopy = true, + .new_ctx = true }; + + block_copy_test(xe, &config, set, BLOCK_COPY); + } + + igt_describe("Check flatccs data persists after suspend / resume (S0)"); + igt_subtest_with_dynamic("suspend-resume") { + struct test_config config = { .compression = true, + .surfcopy = true, + .suspend_resume = true }; + + block_copy_test(xe, &config, set, BLOCK_COPY); + } + + igt_fixture { + xe_device_put(xe); + close(xe); + } +} -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D66110E37E for ; Tue, 11 Jul 2023 11:21:02 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:05 +0200 Message-Id: <20230711112009.122482-14-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 13/17] lib/intel_blt: Extend blitter library to support xe driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Use already written for i915 blitter library in xe development. Add appropriate code paths which are unique for those drivers. Signed-off-by: Zbigniew Kempczyński --- v3: Extract common helpers for getting mapping and alignment (Karolina) --- lib/intel_blt.c | 235 ++++++++++++++++++++++++++++++------------------ lib/intel_blt.h | 2 +- 2 files changed, 150 insertions(+), 87 deletions(-) diff --git a/lib/intel_blt.c b/lib/intel_blt.c index f2f86e4947..5387a60ee3 100644 --- a/lib/intel_blt.c +++ b/lib/intel_blt.c @@ -9,9 +9,13 @@ #include #include #include "drm.h" -#include "igt.h" #include "i915/gem_create.h" +#include "igt.h" +#include "igt_syncobj.h" #include "intel_blt.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" #define BITRANGE(start, end) (end - start + 1) #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd)) @@ -468,24 +472,40 @@ static int __special_mode(const struct blt_copy_data *blt) return SM_NONE; } -static int __memory_type(uint32_t region) +static int __memory_type(int fd, enum intel_driver driver, uint32_t region) { - igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || - IS_SYSTEM_MEMORY_REGION(region), - "Invalid region: %x\n", region); + if (driver == INTEL_DRIVER_I915) { + igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || + IS_SYSTEM_MEMORY_REGION(region), + "Invalid region: %x\n", region); + } else { + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, region) || + XE_IS_SYSMEM_MEMORY_REGION(fd, region), + "Invalid region: %x\n", region); + } - if (IS_DEVICE_MEMORY_REGION(region)) + if (driver == INTEL_DRIVER_I915 && IS_DEVICE_MEMORY_REGION(region)) return TM_LOCAL_MEM; + else if (driver == INTEL_DRIVER_XE && XE_IS_VRAM_MEMORY_REGION(fd, region)) + return TM_LOCAL_MEM; + return TM_SYSTEM_MEM; } -static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj) +static enum blt_aux_mode __aux_mode(int fd, + enum intel_driver driver, + const struct blt_copy_object *obj) { - if (obj->compression == COMPRESSION_ENABLED) { + if (driver == INTEL_DRIVER_I915 && obj->compression == COMPRESSION_ENABLED) { igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region), "XY_BLOCK_COPY_BLT supports compression " "on device memory only\n"); return AM_AUX_CCS_E; + } else if (driver == INTEL_DRIVER_XE && obj->compression == COMPRESSION_ENABLED) { + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, obj->region), + "XY_BLOCK_COPY_BLT supports compression " + "on device memory only\n"); + return AM_AUX_CCS_E; } return AM_AUX_NONE; @@ -508,9 +528,9 @@ static void fill_data(struct gen12_block_copy_data *data, data->dw00.length = extended_command ? 20 : 10; if (__special_mode(blt) == SM_FULL_RESOLVE) - data->dw01.dst_aux_mode = __aux_mode(&blt->src); + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); else - data->dw01.dst_aux_mode = __aux_mode(&blt->dst); + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->dst); data->dw01.dst_pitch = blt->dst.pitch - 1; data->dw01.dst_mocs = blt->dst.mocs; @@ -531,13 +551,13 @@ static void fill_data(struct gen12_block_copy_data *data, data->dw06.dst_x_offset = blt->dst.x_offset; data->dw06.dst_y_offset = blt->dst.y_offset; - data->dw06.dst_target_memory = __memory_type(blt->dst.region); + data->dw06.dst_target_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); data->dw07.src_x1 = blt->src.x1; data->dw07.src_y1 = blt->src.y1; data->dw08.src_pitch = blt->src.pitch - 1; - data->dw08.src_aux_mode = __aux_mode(&blt->src); + data->dw08.src_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); data->dw08.src_mocs = blt->src.mocs; data->dw08.src_compression = blt->src.compression; data->dw08.src_tiling = __block_tiling(blt->src.tiling); @@ -550,7 +570,7 @@ static void fill_data(struct gen12_block_copy_data *data, data->dw11.src_x_offset = blt->src.x_offset; data->dw11.src_y_offset = blt->src.y_offset; - data->dw11.src_target_memory = __memory_type(blt->src.region); + data->dw11.src_target_memory = __memory_type(blt->fd, blt->driver, blt->src.region); } static void fill_data_ext(struct gen12_block_copy_data_ext *dext, @@ -692,6 +712,24 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data) data->dw21.src_array_index); } +static uint64_t get_default_alignment(int fd, enum intel_driver driver) +{ + if (driver == INTEL_DRIVER_XE) + return xe_get_default_alignment(fd); + + return gem_detect_safe_alignment(fd); +} + +static void *bo_map(int fd, uint32_t handle, uint64_t size, + enum intel_driver driver) +{ + if (driver == INTEL_DRIVER_XE) + return xe_bo_map(fd, handle, size); + + return gem_mmap__device_coherent(fd, handle, 0, size, + PROT_READ | PROT_WRITE); +} + /** * blt_copy_init: * @fd: drm fd @@ -739,7 +777,7 @@ uint64_t emit_blt_block_copy(int fd, igt_assert_f(ahnd, "block-copy supports softpin only\n"); igt_assert_f(blt, "block-copy requires data to do blit\n"); - alignment = gem_detect_safe_alignment(fd); + alignment = get_default_alignment(fd, blt->driver); src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment) + blt->src.plane_offset; dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment) @@ -748,8 +786,7 @@ uint64_t emit_blt_block_copy(int fd, fill_data(&data, blt, src_offset, dst_offset, ext); - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, - PROT_READ | PROT_WRITE); + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); igt_assert(bb_pos + sizeof(data) < blt->bb.size); memcpy(bb + bb_pos, &data, sizeof(data)); @@ -812,29 +849,35 @@ int blt_block_copy(int fd, igt_assert_f(ahnd, "block-copy supports softpin only\n"); igt_assert_f(blt, "block-copy requires data to do blit\n"); + igt_assert_neq(blt->driver, 0); - alignment = gem_detect_safe_alignment(fd); + alignment = get_default_alignment(fd, blt->driver); src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); emit_blt_block_copy(fd, ahnd, blt, ext, 0, true); - obj[0].offset = CANONICAL(dst_offset); - obj[1].offset = CANONICAL(src_offset); - obj[2].offset = CANONICAL(bb_offset); - obj[0].handle = blt->dst.handle; - obj[1].handle = blt->src.handle; - obj[2].handle = blt->bb.handle; - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - execbuf.buffer_count = 3; - execbuf.buffers_ptr = to_user_pointer(obj); - execbuf.rsvd1 = ctx ? ctx->id : 0; - execbuf.flags = e ? e->flags : I915_EXEC_BLT; - ret = __gem_execbuf(fd, &execbuf); + if (blt->driver == INTEL_DRIVER_XE) { + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); + } else { + obj[0].offset = CANONICAL(dst_offset); + obj[1].offset = CANONICAL(src_offset); + obj[2].offset = CANONICAL(bb_offset); + obj[0].handle = blt->dst.handle; + obj[1].handle = blt->src.handle; + obj[2].handle = blt->bb.handle; + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + execbuf.buffer_count = 3; + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.rsvd1 = ctx ? ctx->id : 0; + execbuf.flags = e ? e->flags : I915_EXEC_BLT; + + ret = __gem_execbuf(fd, &execbuf); + } return ret; } @@ -950,7 +993,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); data.dw00.client = 0x2; data.dw00.opcode = 0x48; @@ -973,8 +1016,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, data.dw04.dst_address_hi = dst_offset >> 32; data.dw04.dst_mocs = surf->dst.mocs; - bb = gem_mmap__device_coherent(fd, surf->bb.handle, 0, surf->bb.size, - PROT_READ | PROT_WRITE); + bb = bo_map(fd, surf->bb.handle, surf->bb.size, surf->driver); igt_assert(bb_pos + sizeof(data) < surf->bb.size); memcpy(bb + bb_pos, &data, sizeof(data)); @@ -1002,7 +1044,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, /** * blt_ctrl_surf_copy: - * @fd: drm fd + * @blt: bldrm fd * @ctx: intel_ctx_t context * @e: blitter engine for @ctx * @ahnd: allocator handle @@ -1026,32 +1068,37 @@ int blt_ctrl_surf_copy(int fd, igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); + igt_assert_neq(surf->driver, 0); - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); src_offset = get_offset(ahnd, surf->src.handle, surf->src.size, alignment); dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size, alignment); bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size, alignment); emit_blt_ctrl_surf_copy(fd, ahnd, surf, 0, true); - obj[0].offset = CANONICAL(dst_offset); - obj[1].offset = CANONICAL(src_offset); - obj[2].offset = CANONICAL(bb_offset); - obj[0].handle = surf->dst.handle; - obj[1].handle = surf->src.handle; - obj[2].handle = surf->bb.handle; - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - execbuf.buffer_count = 3; - execbuf.buffers_ptr = to_user_pointer(obj); - execbuf.flags = e ? e->flags : I915_EXEC_BLT; - execbuf.rsvd1 = ctx ? ctx->id : 0; - gem_execbuf(fd, &execbuf); - put_offset(ahnd, surf->dst.handle); - put_offset(ahnd, surf->src.handle); - put_offset(ahnd, surf->bb.handle); + if (surf->driver == INTEL_DRIVER_XE) { + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); + } else { + obj[0].offset = CANONICAL(dst_offset); + obj[1].offset = CANONICAL(src_offset); + obj[2].offset = CANONICAL(bb_offset); + obj[0].handle = surf->dst.handle; + obj[1].handle = surf->src.handle; + obj[2].handle = surf->bb.handle; + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + execbuf.buffer_count = 3; + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.flags = e ? e->flags : I915_EXEC_BLT; + execbuf.rsvd1 = ctx ? ctx->id : 0; + gem_execbuf(fd, &execbuf); + put_offset(ahnd, surf->dst.handle); + put_offset(ahnd, surf->src.handle); + put_offset(ahnd, surf->bb.handle); + } return 0; } @@ -1208,7 +1255,7 @@ uint64_t emit_blt_fast_copy(int fd, uint32_t bbe = MI_BATCH_BUFFER_END; uint32_t *bb; - alignment = gem_detect_safe_alignment(fd); + alignment = get_default_alignment(fd, blt->driver); data.dw00.client = 0x2; data.dw00.opcode = 0x42; @@ -1218,8 +1265,8 @@ uint64_t emit_blt_fast_copy(int fd, data.dw01.dst_pitch = blt->dst.pitch; data.dw01.color_depth = __fast_color_depth(blt->color_depth); - data.dw01.dst_memory = __memory_type(blt->dst.region); - data.dw01.src_memory = __memory_type(blt->src.region); + data.dw01.dst_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); + data.dw01.src_memory = __memory_type(blt->fd, blt->driver, blt->src.region); data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0; data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0; @@ -1246,8 +1293,7 @@ uint64_t emit_blt_fast_copy(int fd, data.dw08.src_address_lo = src_offset; data.dw09.src_address_hi = src_offset >> 32; - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, - PROT_READ | PROT_WRITE); + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); igt_assert(bb_pos + sizeof(data) < blt->bb.size); memcpy(bb + bb_pos, &data, sizeof(data)); @@ -1297,32 +1343,39 @@ int blt_fast_copy(int fd, uint64_t dst_offset, src_offset, bb_offset, alignment; int ret; - alignment = gem_detect_safe_alignment(fd); + igt_assert_f(ahnd, "fast-copy supports softpin only\n"); + igt_assert_f(blt, "fast-copy requires data to do fast-copy blit\n"); + igt_assert_neq(blt->driver, 0); + alignment = get_default_alignment(fd, blt->driver); src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); emit_blt_fast_copy(fd, ahnd, blt, 0, true); - obj[0].offset = CANONICAL(dst_offset); - obj[1].offset = CANONICAL(src_offset); - obj[2].offset = CANONICAL(bb_offset); - obj[0].handle = blt->dst.handle; - obj[1].handle = blt->src.handle; - obj[2].handle = blt->bb.handle; - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; - execbuf.buffer_count = 3; - execbuf.buffers_ptr = to_user_pointer(obj); - execbuf.rsvd1 = ctx ? ctx->id : 0; - execbuf.flags = e ? e->flags : I915_EXEC_BLT; - ret = __gem_execbuf(fd, &execbuf); - put_offset(ahnd, blt->dst.handle); - put_offset(ahnd, blt->src.handle); - put_offset(ahnd, blt->bb.handle); + if (blt->driver == INTEL_DRIVER_XE) { + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); + } else { + obj[0].offset = CANONICAL(dst_offset); + obj[1].offset = CANONICAL(src_offset); + obj[2].offset = CANONICAL(bb_offset); + obj[0].handle = blt->dst.handle; + obj[1].handle = blt->src.handle; + obj[2].handle = blt->bb.handle; + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; + execbuf.buffer_count = 3; + execbuf.buffers_ptr = to_user_pointer(obj); + execbuf.rsvd1 = ctx ? ctx->id : 0; + execbuf.flags = e ? e->flags : I915_EXEC_BLT; + ret = __gem_execbuf(fd, &execbuf); + put_offset(ahnd, blt->dst.handle); + put_offset(ahnd, blt->src.handle); + put_offset(ahnd, blt->bb.handle); + } return ret; } @@ -1366,16 +1419,21 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region, obj = calloc(1, sizeof(*obj)); obj->size = size; - igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, - &size, region) == 0); + + if (blt->driver == INTEL_DRIVER_XE) { + size = ALIGN(size, xe_get_default_alignment(blt->fd)); + handle = xe_bo_create_flags(blt->fd, 0, size, region); + } else { + igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, + &size, region) == 0); + } blt_set_object(obj, handle, size, region, mocs, tiling, compression, compression_type); blt_set_geom(obj, stride, 0, 0, width, height, 0, 0); if (create_mapping) - obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size, - PROT_READ | PROT_WRITE); + obj->ptr = bo_map(blt->fd, handle, size, blt->driver); return obj; } @@ -1518,14 +1576,19 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid, int format; int stride = obj->tiling ? obj->pitch * 4 : obj->pitch; char filename[FILENAME_MAX]; + bool is_xe = is_xe_device(fd); snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png", run_id, fileid, blt_tiling_name(obj->tiling), width, height, obj->compression ? "compressed" : "uncompressed"); - if (!map) - map = gem_mmap__device_coherent(fd, obj->handle, 0, - obj->size, PROT_READ); + if (!map) { + if (is_xe) + map = xe_bo_map(fd, obj->handle, obj->size); + else + map = gem_mmap__device_coherent(fd, obj->handle, 0, + obj->size, PROT_READ); + } format = CAIRO_FORMAT_RGB24; surface = cairo_image_surface_create_for_data(map, format, width, height, diff --git a/lib/intel_blt.h b/lib/intel_blt.h index 7516ce8ac7..944e2b4ae7 100644 --- a/lib/intel_blt.h +++ b/lib/intel_blt.h @@ -8,7 +8,7 @@ /** * SECTION:intel_blt - * @short_description: i915 blitter library + * @short_description: i915/xe blitter library * @title: Blitter library * @include: intel_blt.h * -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2CA9510E389 for ; Tue, 11 Jul 2023 11:21:12 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:08 +0200 Message-Id: <20230711112009.122482-17-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 16/17] tests/api-intel-allocator: Adopt to exercise allocator to Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Xe vm binding requires some cooperation from allocator side (tracking alloc()/free()) operations. This diverges the path internally inside the allocator so it is necessary to check if allocator supports properly both drivers. Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek --- tests/i915/api_intel_allocator.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/tests/i915/api_intel_allocator.c b/tests/i915/api_intel_allocator.c index 77c2d25e83..f3fcf8a341 100644 --- a/tests/i915/api_intel_allocator.c +++ b/tests/i915/api_intel_allocator.c @@ -9,6 +9,9 @@ #include "igt.h" #include "igt_aux.h" #include "intel_allocator.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" + /** * TEST: api intel allocator * Category: Infrastructure @@ -454,6 +457,7 @@ static void __simple_allocs(int fd) uint32_t handles[SIMPLE_GROUP_ALLOCS]; uint64_t ahnd; uint32_t ctx; + bool is_xe = is_xe_device(fd); int i; ctx = rand() % 2; @@ -463,7 +467,12 @@ static void __simple_allocs(int fd) uint32_t size; size = (rand() % 4 + 1) * 0x1000; - handles[i] = gem_create(fd, size); + if (is_xe) + handles[i] = xe_bo_create_flags(fd, 0, size, + system_memory(fd)); + else + handles[i] = gem_create(fd, size); + intel_allocator_alloc(ahnd, handles[i], size, 0x1000); } @@ -573,8 +582,6 @@ static void reopen(int fd) { int fd2; - igt_require_gem(fd); - fd2 = drm_reopen_driver(fd); __reopen_allocs(fd, fd2, true); @@ -587,8 +594,6 @@ static void reopen_fork(int fd) { int fd2; - igt_require_gem(fd); - intel_allocator_multiprocess_start(); fd2 = drm_reopen_driver(fd); @@ -838,7 +843,7 @@ igt_main struct allocators *a; igt_fixture { - fd = drm_open_driver(DRIVER_INTEL); + fd = drm_open_driver(DRIVER_INTEL | DRIVER_XE); atomic_init(&next_handle, 1); srandom(0xdeadbeef); } @@ -911,12 +916,16 @@ igt_main igt_subtest_f("open-vm") open_vm(fd); - igt_subtest_f("execbuf-with-allocator") + igt_subtest_f("execbuf-with-allocator") { + igt_require(is_i915_device(fd)); execbuf_with_allocator(fd); + } igt_describe("Verifies creating and executing bb from gem pool"); - igt_subtest_f("gem-pool") + igt_subtest_f("gem-pool") { + igt_require(is_i915_device(fd)); gem_pool(fd); + } igt_fixture drm_close_driver(fd); -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7E3AC10E387 for ; Tue, 11 Jul 2023 11:21:09 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:07 +0200 Message-Id: <20230711112009.122482-16-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 15/17] tests/xe_exercise_blt: Check blitter library fast-copy for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: Port this test to work on xe. Instead of adding conditional code for xe code which would decrease readability this is new test for xe. Signed-off-by: Zbigniew Kempczyński --- v3: - Explicitely release offsets and unbind (Karolina) - Use has-fast-copy instead of copied has-block-copy check (Karolina) --- tests/meson.build | 1 + tests/xe/xe_exercise_blt.c | 377 +++++++++++++++++++++++++++++++++++++ 2 files changed, 378 insertions(+) create mode 100644 tests/xe/xe_exercise_blt.c diff --git a/tests/meson.build b/tests/meson.build index da8653fabc..3eddb2fb4e 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -276,6 +276,7 @@ xe_progs = [ 'xe_exec_reset', 'xe_exec_store', 'xe_exec_threads', + 'xe_exercise_blt', 'xe_gpgpu_fill', 'xe_guc_pc', 'xe_huc_copy', diff --git a/tests/xe/xe_exercise_blt.c b/tests/xe/xe_exercise_blt.c new file mode 100644 index 0000000000..693e80d0b7 --- /dev/null +++ b/tests/xe/xe_exercise_blt.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2023 Intel Corporation + */ + +#include "igt.h" +#include "drm.h" +#include "lib/intel_chipset.h" +#include "intel_blt.h" +#include "intel_mocs.h" +#include "xe/xe_ioctl.h" +#include "xe/xe_query.h" +#include "xe/xe_util.h" + +/** + * TEST: xe exercise blt + * Description: Exercise blitter commands on Xe + * Feature: blitter + * Run type: FULL + * Test category: GEM_Legacy + * + * SUBTEST: fast-copy + * Description: + * Check fast-copy blit + * blitter + * + * SUBTEST: fast-copy-emit + * Description: + * Check multiple fast-copy in one batch + * blitter + */ + +IGT_TEST_DESCRIPTION("Exercise blitter commands on Xe"); + +static struct param { + int tiling; + bool write_png; + bool print_bb; + bool print_surface_info; + int width; + int height; +} param = { + .tiling = -1, + .write_png = false, + .print_bb = false, + .print_surface_info = false, + .width = 512, + .height = 512, +}; + +#define PRINT_SURFACE_INFO(name, obj) do { \ + if (param.print_surface_info) \ + blt_surface_info((name), (obj)); } while (0) + +#define WRITE_PNG(fd, id, name, obj, w, h) do { \ + if (param.write_png) \ + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0) + +struct blt_fast_copy_data { + int xe; + struct blt_copy_object src; + struct blt_copy_object mid; + struct blt_copy_object dst; + + struct blt_copy_batch bb; + enum blt_color_depth color_depth; + + /* debug stuff */ + bool print_bb; +}; + +static int fast_copy_one_bb(int xe, + const intel_ctx_t *ctx, + uint64_t ahnd, + const struct blt_fast_copy_data *blt) +{ + struct blt_copy_data blt_tmp; + uint64_t bb_offset, alignment; + uint64_t bb_pos = 0; + int ret = 0; + + alignment = xe_get_default_alignment(xe); + + get_offset(ahnd, blt->src.handle, blt->src.size, alignment); + get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment); + get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); + + /* First blit */ + blt_copy_init(xe, &blt_tmp); + blt_tmp.src = blt->src; + blt_tmp.dst = blt->mid; + blt_tmp.bb = blt->bb; + blt_tmp.color_depth = blt->color_depth; + blt_tmp.print_bb = blt->print_bb; + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, false); + + /* Second blit */ + blt_copy_init(xe, &blt_tmp); + blt_tmp.src = blt->mid; + blt_tmp.dst = blt->dst; + blt_tmp.bb = blt->bb; + blt_tmp.color_depth = blt->color_depth; + blt_tmp.print_bb = blt->print_bb; + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, true); + + intel_ctx_xe_exec(ctx, ahnd, bb_offset); + + return ret; +} + +static void fast_copy_emit(int xe, const intel_ctx_t *ctx, + uint32_t region1, uint32_t region2, + enum blt_tiling_type mid_tiling) +{ + struct blt_copy_data bltinit = {}; + struct blt_fast_copy_data blt = {}; + struct blt_copy_object *src, *mid, *dst; + const uint32_t bpp = 32; + uint64_t bb_size = xe_get_default_alignment(xe); + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb, width = param.width, height = param.height; + int result; + + bb = xe_bo_create_flags(xe, 0, bb_size, region1); + + blt_copy_init(xe, &bltinit); + src = blt_create_object(&bltinit, region1, width, height, bpp, 0, + T_LINEAR, COMPRESSION_DISABLED, 0, true); + mid = blt_create_object(&bltinit, region2, width, height, bpp, 0, + mid_tiling, COMPRESSION_DISABLED, 0, true); + dst = blt_create_object(&bltinit, region1, width, height, bpp, 0, + T_LINEAR, COMPRESSION_DISABLED, 0, true); + igt_assert(src->size == dst->size); + + PRINT_SURFACE_INFO("src", src); + PRINT_SURFACE_INFO("mid", mid); + PRINT_SURFACE_INFO("dst", dst); + + blt_surface_fill_rect(xe, src, width, height); + WRITE_PNG(xe, mid_tiling, "src", src, width, height); + + memset(&blt, 0, sizeof(blt)); + blt.color_depth = CD_32bit; + blt.print_bb = param.print_bb; + blt_set_copy_object(&blt.src, src); + blt_set_copy_object(&blt.mid, mid); + blt_set_copy_object(&blt.dst, dst); + blt_set_batch(&blt.bb, bb, bb_size, region1); + + fast_copy_one_bb(xe, ctx, ahnd, &blt); + + WRITE_PNG(xe, mid_tiling, "mid", &blt.mid, width, height); + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height); + + result = memcmp(src->ptr, blt.dst.ptr, src->size); + + blt_destroy_object(xe, src); + blt_destroy_object(xe, mid); + blt_destroy_object(xe, dst); + gem_close(xe, bb); + put_ahnd(ahnd); + + munmap(&bb, bb_size); + + igt_assert_f(!result, "source and destination surfaces differs!\n"); +} + +static void fast_copy(int xe, const intel_ctx_t *ctx, + uint32_t region1, uint32_t region2, + enum blt_tiling_type mid_tiling) +{ + struct blt_copy_data blt = {}; + struct blt_copy_object *src, *mid, *dst; + const uint32_t bpp = 32; + uint64_t bb_size = xe_get_default_alignment(xe); + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0, + INTEL_ALLOCATOR_SIMPLE, + ALLOC_STRATEGY_LOW_TO_HIGH, 0); + uint32_t bb; + uint32_t width = param.width, height = param.height; + int result; + + bb = xe_bo_create_flags(xe, 0, bb_size, region1); + + blt_copy_init(xe, &blt); + src = blt_create_object(&blt, region1, width, height, bpp, 0, + T_LINEAR, COMPRESSION_DISABLED, 0, true); + mid = blt_create_object(&blt, region2, width, height, bpp, 0, + mid_tiling, COMPRESSION_DISABLED, 0, true); + dst = blt_create_object(&blt, region1, width, height, bpp, 0, + T_LINEAR, COMPRESSION_DISABLED, 0, true); + igt_assert(src->size == dst->size); + + blt_surface_fill_rect(xe, src, width, height); + + blt.color_depth = CD_32bit; + blt.print_bb = param.print_bb; + blt_set_copy_object(&blt.src, src); + blt_set_copy_object(&blt.dst, mid); + blt_set_batch(&blt.bb, bb, bb_size, region1); + + blt_fast_copy(xe, ctx, NULL, ahnd, &blt); + + WRITE_PNG(xe, mid_tiling, "src", &blt.src, width, height); + WRITE_PNG(xe, mid_tiling, "mid", &blt.dst, width, height); + + blt_copy_init(xe, &blt); + blt.color_depth = CD_32bit; + blt.print_bb = param.print_bb; + blt_set_copy_object(&blt.src, mid); + blt_set_copy_object(&blt.dst, dst); + blt_set_batch(&blt.bb, bb, bb_size, region1); + + blt_fast_copy(xe, ctx, NULL, ahnd, &blt); + + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height); + + result = memcmp(src->ptr, blt.dst.ptr, src->size); + + put_offset(ahnd, src->handle); + put_offset(ahnd, mid->handle); + put_offset(ahnd, dst->handle); + put_offset(ahnd, bb); + intel_allocator_bind(ahnd, 0, 0); + blt_destroy_object(xe, src); + blt_destroy_object(xe, mid); + blt_destroy_object(xe, dst); + gem_close(xe, bb); + put_ahnd(ahnd); + + igt_assert_f(!result, "source and destination surfaces differs!\n"); +} + +enum fast_copy_func { + FAST_COPY, + FAST_COPY_EMIT +}; + +static char + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling, + enum fast_copy_func func) +{ + char *name; + uint32_t len; + + len = asprintf(&name, "%s-%s%s", blt_tiling_name(tiling), regtxt, + func == FAST_COPY_EMIT ? "-emit" : ""); + + igt_assert_f(len >= 0, "asprintf failed!\n"); + + return name; +} + +static void fast_copy_test(int xe, + struct igt_collection *set, + enum fast_copy_func func) +{ + struct drm_xe_engine_class_instance inst = { + .engine_class = DRM_XE_ENGINE_CLASS_COPY, + }; + struct igt_collection *regions; + void (*copy_func)(int xe, const intel_ctx_t *ctx, + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling); + intel_ctx_t *ctx; + int tiling; + + for_each_tiling(tiling) { + if (!blt_fast_copy_supports_tiling(xe, tiling)) + continue; + + for_each_variation_r(regions, 2, set) { + uint32_t region1, region2; + uint32_t vm, engine; + char *regtxt, *test_name; + + region1 = igt_collection_get_value(regions, 0); + region2 = igt_collection_get_value(regions, 1); + + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); + engine = xe_engine_create(xe, vm, &inst, 0); + ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0); + + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit; + regtxt = xe_memregion_dynamic_subtest_name(xe, regions); + test_name = full_subtest_str(regtxt, tiling, func); + + igt_dynamic_f("%s", test_name) { + copy_func(xe, ctx, + region1, region2, + tiling); + } + + free(regtxt); + free(test_name); + xe_engine_destroy(xe, engine); + xe_vm_destroy(xe, vm); + free(ctx); + } + } +} + +static int opt_handler(int opt, int opt_index, void *data) +{ + switch (opt) { + case 'b': + param.print_bb = true; + igt_debug("Print bb: %d\n", param.print_bb); + break; + case 'p': + param.write_png = true; + igt_debug("Write png: %d\n", param.write_png); + break; + case 's': + param.print_surface_info = true; + igt_debug("Print surface info: %d\n", param.print_surface_info); + break; + case 't': + param.tiling = atoi(optarg); + igt_debug("Tiling: %d\n", param.tiling); + break; + case 'W': + param.width = atoi(optarg); + igt_debug("Width: %d\n", param.width); + break; + case 'H': + param.height = atoi(optarg); + igt_debug("Height: %d\n", param.height); + break; + default: + return IGT_OPT_HANDLER_ERROR; + } + + return IGT_OPT_HANDLER_SUCCESS; +} + +const char *help_str = + " -b\tPrint bb\n" + " -p\tWrite PNG\n" + " -s\tPrint surface info\n" + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n" + " -W\tWidth (default 512)\n" + " -H\tHeight (default 512)" + ; + +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL) +{ + struct igt_collection *set; + int xe; + + igt_fixture { + xe = drm_open_driver(DRIVER_XE); + igt_require(blt_has_fast_copy(xe)); + + xe_device_get(xe); + + set = xe_get_memory_region_set(xe, + XE_MEM_REGION_CLASS_SYSMEM, + XE_MEM_REGION_CLASS_VRAM); + } + + igt_describe("Check fast-copy blit"); + igt_subtest_with_dynamic("fast-copy") { + fast_copy_test(xe, set, FAST_COPY); + } + + igt_describe("Check multiple fast-copy in one batch"); + igt_subtest_with_dynamic("fast-copy-emit") { + fast_copy_test(xe, set, FAST_COPY_EMIT); + } + + igt_fixture { + drm_close_driver(xe); + } +} -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Patchwork To: =?utf-8?q?Zbigniew_Kempczy=C5=84ski?= Date: Tue, 11 Jul 2023 11:40:44 -0000 Message-ID: <168907564445.18664.5700557395563959593@emeril.freedesktop.org> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> Subject: [igt-dev] =?utf-8?q?=E2=9C=97_GitLab=2EPipeline=3A_warning_for_E?= =?utf-8?q?xtend_intel=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: igt-dev@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: == Series Details == Series: Extend intel_blt to work on Xe (rev3) URL : https://patchwork.freedesktop.org/series/120162/ State : warning == Summary == Pipeline status: FAILED. see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/932186 for the overview. build-containers:build-debian has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/45263081): time="2023-07-11T11:38:24Z" level=fatal msg="Invalid status code returned when fetching blob 500 (Internal Server Error)" Building! STEP 1: FROM debian:buster Getting image source signatures Copying blob sha256:8eb6dba554cffc072c7a6c696c8a23fc311e543399d84ab3ebc55c07ab54414f Copying config sha256:1de12428f6f470169eba22c18e53addae00d60e92ebe96b2c3bdd99c17c34010 Writing manifest to image destination Storing signatures STEP 2: RUN apt-get update error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-07-11T11:38:32Z" level=warning msg="signal: killed" time="2023-07-11T11:38:32Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n" container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\"" : exit status 1 Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1 section_end:1689075513:step_script section_start:1689075513:cleanup_file_variables Cleaning up project directory and file based variables section_end:1689075516:cleanup_file_variables ERROR: Job failed: exit code 1 build-containers:build-debian-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/45263083): "DockerVersion": "", "Labels": {}, "Architecture": "amd64", "Os": "linux", "Layers": [ "sha256:a1c4b97398ec8bc7b17c52a01ef6941dc58811cb43f945b093db7a131586297a" ] } Skipping, already built Getting image source signatures Copying blob sha256:a1c4b97398ec8bc7b17c52a01ef6941dc58811cb43f945b093db7a131586297a Copying config sha256:7360075a71dacfc66f0b49b3271b9a459904dbe51c5760efac48fe52da27946c Writing manifest to image destination time="2023-07-11T11:38:23Z" level=fatal msg="Error writing manifest: Error uploading manifest commit-72ee64f2d536b357e190a6a85a90cdcebc7ed1e8 to registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-arm64: received unexpected HTTP status: 500 Internal Server Error" section_end:1689075504:step_script section_start:1689075504:cleanup_file_variables Cleaning up project directory and file based variables section_end:1689075504:cleanup_file_variables ERROR: Job failed: exit code 1 build-containers:build-debian-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/45263082): "intel-IGT_5164" ], "Created": "2019-11-20T12:54:52.073706506Z", "DockerVersion": "", "Labels": {}, "Architecture": "amd64", "Os": "linux", "Layers": [ "sha256:45252bb38c9c74dfe76c4b3808269db61d3b2aebe5e26bf7fcd85e48b93e16f9" ] } Skipping, already built Getting image source signatures time="2023-07-11T11:38:22Z" level=fatal msg="Error trying to reuse blob sha256:45252bb38c9c74dfe76c4b3808269db61d3b2aebe5e26bf7fcd85e48b93e16f9 at destination: failed to read from destination repository gfx-ci/igt-ci-tags/build-debian-armhf: 500 (Internal Server Error)" section_end:1689075503:step_script section_start:1689075503:cleanup_file_variables Cleaning up project directory and file based variables section_end:1689075504:cleanup_file_variables ERROR: Job failed: exit code 1 build-containers:build-debian-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/45263084): "DockerVersion": "", "Labels": {}, "Architecture": "amd64", "Os": "linux", "Layers": [ "sha256:04854e5e3796b945522a085073b5a49cadad51bd1c5414c91654fa3d63d8db4d" ] } Skipping, already built Getting image source signatures Copying blob sha256:04854e5e3796b945522a085073b5a49cadad51bd1c5414c91654fa3d63d8db4d Copying config sha256:cc55efdc667be826910d414a562c76ce1130a9c15255a0dd115431bc42f83448 Writing manifest to image destination time="2023-07-11T11:38:23Z" level=fatal msg="Error writing manifest: Error uploading manifest commit-72ee64f2d536b357e190a6a85a90cdcebc7ed1e8 to registry.freedesktop.org/gfx-ci/igt-ci-tags/build-debian-mips: received unexpected HTTP status: 500 Internal Server Error" section_end:1689075504:step_script section_start:1689075504:cleanup_file_variables Cleaning up project directory and file based variables section_end:1689075504:cleanup_file_variables ERROR: Job failed: exit code 1 build-containers:build-fedora has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/45263085): time="2023-07-11T11:38:20Z" level=fatal msg="Error reading manifest dockerfile-d55a9096f48b128e63002d049c1e9ea16a6c5bee in registry.freedesktop.org/gfx-ci/igt-ci-tags/build-fedora: received unexpected HTTP status: 500 Internal Server Error" Building! STEP 1: FROM fedora:31 Getting image source signatures Copying blob sha256:854946d575a439a894349addd141568875d7c1e673d3286b08250f3dde002e6a Copying config sha256:7e94ed77b448a8d2ff08b92d3ca743e4e862c744892d6886c73487581eb5863a Writing manifest to image destination Storing signatures STEP 2: RUN dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils error running container: error creating container for [/bin/sh -c dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils]: time="2023-07-11T11:38:26Z" level=warning msg="signal: killed" time="2023-07-11T11:38:26Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n" container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\"" : exit status 1 Error: error building at STEP "RUN dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils": error while running runtime: exit status 1 section_end:1689075506:step_script section_start:1689075506:cleanup_file_variables Cleaning up project directory and file based variables section_end:1689075507:cleanup_file_variables ERROR: Job failed: exit code 1 == Logs == For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/932186 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id BB31210E389 for ; Tue, 11 Jul 2023 11:21:16 +0000 (UTC) From: =?UTF-8?q?Zbigniew=20Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Date: Tue, 11 Jul 2023 13:20:09 +0200 Message-Id: <20230711112009.122482-18-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [igt-dev] [PATCH i-g-t v3 17/17] tests/gem_ccs: Avoid writing png twice List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: As Karolina noticed we write source png twice what's just takes time as source surface is not touched. Drop one png write. Signed-off-by: Zbigniew Kempczyński Cc: Karolina Stolarek --- tests/i915/gem_ccs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c index d9d785ed9b..a1302e0a4d 100644 --- a/tests/i915/gem_ccs.c +++ b/tests/i915/gem_ccs.c @@ -421,7 +421,6 @@ static void block_copy(int i915, if (mid->compression) igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0); - WRITE_PNG(i915, run_id, "src", &blt.src, width, height); WRITE_PNG(i915, run_id, "mid", &blt.dst, width, height); if (config->surfcopy && pext) { -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Content-Type: multipart/alternative; boundary="===============3213463174538870472==" MIME-Version: 1.0 From: Patchwork To: =?utf-8?q?Zbigniew_Kempczy=C5=84ski?= Date: Tue, 11 Jul 2023 12:10:54 -0000 Message-ID: <168907745413.18664.17217949000430337174@emeril.freedesktop.org> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> Subject: [igt-dev] =?utf-8?b?4pyTIEZpLkNJLkJBVDogc3VjY2VzcyBmb3IgRXh0ZW5k?= =?utf-8?q?_intel=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: igt-dev@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: --===============3213463174538870472== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit == Series Details == Series: Extend intel_blt to work on Xe (rev3) URL : https://patchwork.freedesktop.org/series/120162/ State : success == Summary == CI Bug Log - changes from CI_DRM_13369 -> IGTPW_9383 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html Participating hosts (40 -> 40) ------------------------------ Additional (1): fi-pnv-d510 Missing (1): fi-snb-2520m Known issues ------------ Here are the changes found in IGTPW_9383 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - fi-rkl-11600: [PASS][1] -> [FAIL][2] ([i915#7940]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html - fi-tgl-1115g4: [PASS][3] -> [FAIL][4] ([i915#7940]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live@gem_contexts: - bat-mtlp-8: [PASS][5] -> [ABORT][6] ([i915#8671] / [i915#8704]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-mtlp-8/igt@i915_selftest@live@gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-mtlp-8/igt@i915_selftest@live@gem_contexts.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][7] -> [DMESG-FAIL][8] ([i915#8497]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-mtlp-8/igt@i915_selftest@live@requests.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-mtlp-8/igt@i915_selftest@live@requests.html - bat-mtlp-6: [PASS][9] -> [DMESG-FAIL][10] ([i915#8497]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-mtlp-6/igt@i915_selftest@live@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-mtlp-6/igt@i915_selftest@live@requests.html * igt@i915_selftest@live@slpc: - bat-mtlp-6: [PASS][11] -> [DMESG-WARN][12] ([i915#6367]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-mtlp-6/igt@i915_selftest@live@slpc.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-mtlp-6/igt@i915_selftest@live@slpc.html - bat-rpls-1: [PASS][13] -> [DMESG-WARN][14] ([i915#6367]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-rpls-1/igt@i915_selftest@live@slpc.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-rpls-1/igt@i915_selftest@live@slpc.html * igt@i915_suspend@basic-s3-without-i915: - fi-pnv-d510: NOTRUN -> [ABORT][15] ([i915#8844]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-pnv-d510/igt@i915_suspend@basic-s3-without-i915.html - bat-rpls-2: [PASS][16] -> [ABORT][17] ([i915#6687] / [i915#7978] / [i915#8668]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: - bat-rplp-1: [PASS][18] -> [ABORT][19] ([i915#8442] / [i915#8668]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510: NOTRUN -> [SKIP][20] ([fdo#109271]) +37 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-pnv-d510/igt@kms_psr@primary_page_flip.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s0@smem: - bat-dg1-7: [FAIL][21] ([fdo#103375] / [i915#6121] / [i915#8011]) -> [PASS][22] +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-dg1-7/igt@gem_exec_suspend@basic-s0@smem.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-dg1-7/igt@gem_exec_suspend@basic-s0@smem.html * igt@gem_exec_suspend@basic-s3@smem: - bat-dg1-7: [FAIL][23] ([fdo#103375] / [i915#6121]) -> [PASS][24] +1 similar issue [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-dg1-7/igt@gem_exec_suspend@basic-s3@smem.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-dg1-7/igt@gem_exec_suspend@basic-s3@smem.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][25] ([i915#5334]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_mocs: - bat-mtlp-8: [DMESG-FAIL][27] ([i915#7059]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-mtlp-8/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [DMESG-FAIL][29] ([i915#8723]) -> [PASS][30] [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/fi-skl-guc/igt@i915_selftest@live@hangcheck.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-skl-guc/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][31] ([i915#7699]) -> [PASS][32] [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-dg2-11/igt@i915_selftest@live@migrate.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-dg2-11/igt@i915_selftest@live@migrate.html * igt@i915_selftest@live@slpc: - bat-rpls-2: [DMESG-WARN][33] ([i915#6367]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-rpls-2/igt@i915_selftest@live@slpc.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-rpls-2/igt@i915_selftest@live@slpc.html #### Warnings #### * igt@core_auth@basic-auth: - bat-adlp-11: [ABORT][35] ([i915#4423] / [i915#8011]) -> [ABORT][36] ([i915#8011]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/bat-adlp-11/igt@core_auth@basic-auth.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/bat-adlp-11/igt@core_auth@basic-auth.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [SKIP][37] ([fdo#109271]) -> [FAIL][38] ([i915#7940]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121 [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367 [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940 [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442 [i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8671]: https://gitlab.freedesktop.org/drm/intel/issues/8671 [i915#8704]: https://gitlab.freedesktop.org/drm/intel/issues/8704 [i915#8723]: https://gitlab.freedesktop.org/drm/intel/issues/8723 [i915#8844]: https://gitlab.freedesktop.org/drm/intel/issues/8844 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7380 -> IGTPW_9383 CI-20190529: 20190529 CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Testlist changes ---------------- +igt@xe_ccs@block-copy-compressed +igt@xe_ccs@block-copy-uncompressed +igt@xe_ccs@block-multicopy-compressed +igt@xe_ccs@block-multicopy-inplace +igt@xe_ccs@ctrl-surf-copy +igt@xe_ccs@ctrl-surf-copy-new-ctx +igt@xe_ccs@suspend-resume +igt@xe_exercise_blt@fast-copy +igt@xe_exercise_blt@fast-copy-emit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html --===============3213463174538870472== Content-Type: text/html; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Project List - Patchwork Patch Details
Series:Extend intel_blt to work on Xe (rev3)
URL:https://patchwork.freedesktop.org/series/120162/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html

CI Bug Log - changes from CI_DRM_13369 -> IGTPW_9383

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html

Participating hosts (40 -> 40)

Additional (1): fi-pnv-d510
Missing (1): fi-snb-2520m

Known issues

Here are the changes found in IGTPW_9383 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

  • CI: CI-20190529 -> None
  • IGT: IGT_7380 -> IGTPW_9383

CI-20190529: 20190529
CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html
IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

Testlist changes

+igt@xe_ccs@block-copy-compressed
+igt@xe_ccs@block-copy-uncompressed
+igt@xe_ccs@block-multicopy-compressed
+igt@xe_ccs@block-multicopy-inplace
+igt@xe_ccs@ctrl-surf-copy
+igt@xe_ccs@ctrl-surf-copy-new-ctx
+igt@xe_ccs@suspend-resume
+igt@xe_exercise_blt@fast-copy
+igt@xe_exercise_blt@fast-copy-emit

--===============3213463174538870472==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Content-Type: multipart/alternative; boundary="===============4120151199789869305==" MIME-Version: 1.0 From: Patchwork To: =?utf-8?q?Zbigniew_Kempczy=C5=84ski?= Date: Tue, 11 Jul 2023 14:52:12 -0000 Message-ID: <168908713268.18666.15567798926028643785@emeril.freedesktop.org> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> Subject: [igt-dev] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRXh0ZW5k?= =?utf-8?q?_intel=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: igt-dev@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: --===============4120151199789869305== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit == Series Details == Series: Extend intel_blt to work on Xe (rev3) URL : https://patchwork.freedesktop.org/series/120162/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13369_full -> IGTPW_9383_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with IGTPW_9383_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_9383_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in IGTPW_9383_full: ### IGT changes ### #### Possible regressions #### * igt@prime_vgem@fence-wait@ccs0: - shard-mtlp: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@prime_vgem@fence-wait@ccs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@prime_vgem@fence-wait@ccs0.html * igt@prime_vgem@fence-wait@vecs0: - shard-mtlp: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@prime_vgem@fence-wait@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@prime_vgem@fence-wait@vecs0.html * igt@vgem_basic@sysfs: - shard-snb: [PASS][5] -> [ABORT][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-snb7/igt@vgem_basic@sysfs.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb2/igt@vgem_basic@sysfs.html Known issues ------------ Here are the changes found in IGTPW_9383_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@crc32: - shard-tglu: NOTRUN -> [SKIP][7] ([i915#6230]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@api_intel_bb@crc32.html * igt@device_reset@unbind-cold-reset-rebind: - shard-rkl: NOTRUN -> [SKIP][8] ([i915#7701]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@device_reset@unbind-cold-reset-rebind.html - shard-dg2: NOTRUN -> [SKIP][9] ([i915#7701]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@device_reset@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#8414]) +19 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@drm_fdinfo@busy-hang@bcs0.html * igt@drm_fdinfo@most-busy-idle-check-all@rcs0: - shard-rkl: [PASS][11] -> [FAIL][12] ([i915#7742]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][13] ([i915#8414]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@drm_fdinfo@virtual-busy-all.html * igt@gem_bad_reloc@negative-reloc-bltcopy: - shard-mtlp: NOTRUN -> [SKIP][14] ([i915#3281]) +5 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@gem_bad_reloc@negative-reloc-bltcopy.html * igt@gem_basic@multigpu-create-close: - shard-rkl: NOTRUN -> [SKIP][15] ([i915#7697]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@gem_basic@multigpu-create-close.html * igt@gem_ccs@block-copy-compressed: - shard-tglu: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#5325]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@gem_ccs@block-copy-compressed.html * igt@gem_ccs@ctrl-surf-copy-new-ctx: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#5325]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@gem_ccs@ctrl-surf-copy-new-ctx.html * igt@gem_close_race@multigpu-basic-process: - shard-dg2: NOTRUN -> [SKIP][18] ([i915#7697]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@gem_close_race@multigpu-basic-process.html * igt@gem_create@create-ext-cpu-access-big: - shard-tglu: NOTRUN -> [SKIP][19] ([i915#6335]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][20] -> [FAIL][21] ([i915#6268]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][22] ([fdo#109314]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-11/igt@gem_ctx_param@set-priority-not-supported.html - shard-rkl: NOTRUN -> [SKIP][23] ([fdo#109314]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@gem_ctx_param@set-priority-not-supported.html * igt@gem_ctx_persistence@saturated-hostile@vecs0: - shard-mtlp: [PASS][24] -> [FAIL][25] ([i915#7816]) +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@gem_ctx_persistence@saturated-hostile@vecs0.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@gem_ctx_persistence@saturated-hostile@vecs0.html * igt@gem_eio@in-flight-contexts-1us: - shard-mtlp: [PASS][26] -> [ABORT][27] ([i915#8503]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@gem_eio@in-flight-contexts-1us.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@gem_eio@in-flight-contexts-1us.html * igt@gem_eio@kms: - shard-dg2: [PASS][28] -> [INCOMPLETE][29] ([i915#7892]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-8/igt@gem_eio@kms.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@gem_eio@kms.html * igt@gem_exec_balancer@bonded-true-hang: - shard-dg2: NOTRUN -> [SKIP][30] ([i915#4812]) +2 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@gem_exec_balancer@bonded-true-hang.html * igt@gem_exec_fair@basic-none@bcs0: - shard-tglu: NOTRUN -> [FAIL][31] ([i915#2842]) +4 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@gem_exec_fair@basic-none@bcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-glk: [PASS][32] -> [FAIL][33] ([i915#2842]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk7/igt@gem_exec_fair@basic-pace@vcs0.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-throttle: - shard-dg2: NOTRUN -> [SKIP][34] ([i915#3539]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-2/igt@gem_exec_fair@basic-throttle.html * igt@gem_exec_fence@submit67: - shard-mtlp: NOTRUN -> [SKIP][35] ([i915#4812]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_exec_fence@submit67.html * igt@gem_exec_params@secure-non-root: - shard-tglu: NOTRUN -> [SKIP][36] ([fdo#112283]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@gem_exec_params@secure-non-root.html * igt@gem_exec_reloc@basic-write-gtt-active: - shard-dg2: NOTRUN -> [SKIP][37] ([i915#3281]) +2 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@gem_exec_reloc@basic-write-gtt-active.html - shard-rkl: NOTRUN -> [SKIP][38] ([i915#3281]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@gem_exec_reloc@basic-write-gtt-active.html * igt@gem_exec_whisper@basic-forked: - shard-mtlp: NOTRUN -> [FAIL][39] ([i915#6363]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@gem_exec_whisper@basic-forked.html * igt@gem_exec_whisper@basic-forked-all: - shard-mtlp: [PASS][40] -> [FAIL][41] ([i915#6363]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@gem_exec_whisper@basic-forked-all.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@gem_exec_whisper@basic-forked-all.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-tglu: NOTRUN -> [SKIP][42] ([i915#4613]) +2 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@gem_lmem_swapping@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#4613]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl1/igt@gem_lmem_swapping@parallel-multi.html * igt@gem_lmem_swapping@parallel-random: - shard-mtlp: NOTRUN -> [SKIP][44] ([i915#4613]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@gem_lmem_swapping@parallel-random.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg2: [PASS][45] -> [TIMEOUT][46] ([i915#5493]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@gem_media_vme: - shard-tglu: NOTRUN -> [SKIP][47] ([i915#284]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@gem_media_vme.html * igt@gem_mmap_wc@write: - shard-mtlp: NOTRUN -> [SKIP][48] ([i915#4083]) +1 similar issue [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@gem_mmap_wc@write.html - shard-dg2: NOTRUN -> [SKIP][49] ([i915#4083]) +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@gem_mmap_wc@write.html * igt@gem_partial_pwrite_pread@reads: - shard-mtlp: NOTRUN -> [SKIP][50] ([i915#3282]) +3 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_partial_pwrite_pread@reads.html * igt@gem_partial_pwrite_pread@writes-after-reads: - shard-rkl: NOTRUN -> [SKIP][51] ([i915#3282]) +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@gem_partial_pwrite_pread@writes-after-reads.html * igt@gem_pxp@create-regular-buffer: - shard-mtlp: NOTRUN -> [SKIP][52] ([i915#4270]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@gem_pxp@create-regular-buffer.html * igt@gem_pxp@fail-invalid-protected-context: - shard-tglu: NOTRUN -> [SKIP][53] ([i915#4270]) +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@gem_pxp@fail-invalid-protected-context.html * igt@gem_readwrite@beyond-eob: - shard-dg2: NOTRUN -> [SKIP][54] ([i915#3282]) +3 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@gem_readwrite@beyond-eob.html * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs: - shard-mtlp: NOTRUN -> [SKIP][55] ([i915#8428]) +3 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html * igt@gem_set_tiling_vs_pwrite: - shard-dg2: NOTRUN -> [SKIP][56] ([i915#4079]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@gem_set_tiling_vs_pwrite.html * igt@gem_tiled_fence_blits@basic: - shard-dg2: NOTRUN -> [SKIP][57] ([i915#4077]) +3 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - shard-mtlp: NOTRUN -> [SKIP][58] ([i915#4079]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@gem_tiled_pread_basic.html * igt@gem_userptr_blits@coherency-unsync: - shard-mtlp: NOTRUN -> [SKIP][59] ([i915#3297]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_userptr_blits@coherency-unsync.html * igt@gem_userptr_blits@invalid-mmap-offset-unsync: - shard-dg2: NOTRUN -> [SKIP][60] ([i915#3297]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html - shard-rkl: NOTRUN -> [SKIP][61] ([i915#3297]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-dg2: NOTRUN -> [SKIP][62] ([i915#3297] / [i915#4880]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_userptr_blits@nohangcheck: - shard-mtlp: [PASS][63] -> [FAIL][64] ([i915#7916]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@gem_userptr_blits@nohangcheck.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@gem_userptr_blits@nohangcheck.html * igt@gen7_exec_parse@load-register-reg: - shard-dg2: NOTRUN -> [SKIP][65] ([fdo#109289]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@gen7_exec_parse@load-register-reg.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-mtlp: NOTRUN -> [SKIP][66] ([fdo#109289]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@gen7_exec_parse@oacontrol-tracking.html * igt@gen9_exec_parse@bb-large: - shard-dg2: NOTRUN -> [SKIP][67] ([i915#2856]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@gen9_exec_parse@bb-large.html - shard-rkl: NOTRUN -> [SKIP][68] ([i915#2527]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@gen9_exec_parse@bb-large.html * igt@i915_hangman@gt-engine-error@vcs0: - shard-mtlp: [PASS][69] -> [FAIL][70] ([i915#7069]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@i915_hangman@gt-engine-error@vcs0.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@i915_hangman@gt-engine-error@vcs0.html * igt@i915_module_load@load: - shard-rkl: NOTRUN -> [SKIP][71] ([i915#6227]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@i915_module_load@load.html * igt@i915_pm_backlight@bad-brightness: - shard-dg2: NOTRUN -> [SKIP][72] ([i915#5354] / [i915#7561]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@i915_pm_backlight@bad-brightness.html * igt@i915_pm_dc@dc5-psr: - shard-tglu: NOTRUN -> [SKIP][73] ([i915#658]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-3/igt@i915_pm_dc@dc5-psr.html * igt@i915_pm_dc@dc9-dpms: - shard-apl: [PASS][74] -> [SKIP][75] ([fdo#109271]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl3/igt@i915_pm_dc@dc9-dpms.html [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl7/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_lpsp@screens-disabled: - shard-mtlp: NOTRUN -> [SKIP][76] ([i915#8430]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@i915_pm_lpsp@screens-disabled.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-dg2: [PASS][77] -> [SKIP][78] ([i915#1397]) +1 similar issue [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress.html * igt@i915_pm_rpm@pc8-residency: - shard-mtlp: NOTRUN -> [SKIP][79] ([fdo#109293]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@i915_pm_rpm@pc8-residency.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-tglu: NOTRUN -> [FAIL][80] ([i915#7940]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@i915_pm_rpm@system-suspend-execbuf.html * igt@i915_suspend@basic-s3-without-i915: - shard-dg2: [PASS][81] -> [FAIL][82] ([fdo#103375] / [i915#6121]) +2 similar issues [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-2/igt@i915_suspend@basic-s3-without-i915.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@i915_suspend@basic-s3-without-i915.html - shard-tglu: NOTRUN -> [INCOMPLETE][83] ([i915#7443] / [i915#8102]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-3/igt@i915_suspend@basic-s3-without-i915.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][84] -> [ABORT][85] ([i915#180] / [i915#8213]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl4/igt@i915_suspend@debugfs-reader.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl7/igt@i915_suspend@debugfs-reader.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-snb: NOTRUN -> [DMESG-WARN][86] ([i915#8841]) +4 similar issues [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb4/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - shard-mtlp: NOTRUN -> [SKIP][87] ([i915#4212]) [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - shard-dg2: NOTRUN -> [SKIP][88] ([i915#4215] / [i915#5190]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_async_flips@crc@pipe-a-hdmi-a-3: - shard-dg2: NOTRUN -> [FAIL][89] ([i915#8247]) +3 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html * igt@kms_big_fb@4-tiled-16bpp-rotate-90: - shard-mtlp: NOTRUN -> [SKIP][90] ([fdo#111614]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html * igt@kms_big_fb@4-tiled-8bpp-rotate-270: - shard-dg2: NOTRUN -> [SKIP][91] ([fdo#111614]) +1 similar issue [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-mtlp: [PASS][92] -> [FAIL][93] ([i915#3743]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-tglu: NOTRUN -> [SKIP][94] ([fdo#111615] / [i915#5286]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-rkl: NOTRUN -> [SKIP][95] ([i915#5286]) +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html - shard-mtlp: [PASS][96] -> [FAIL][97] ([i915#5138]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][98] ([fdo#111614] / [i915#3638]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-mtlp: NOTRUN -> [FAIL][99] ([i915#3743]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@y-tiled-8bpp-rotate-90: - shard-tglu: NOTRUN -> [SKIP][100] ([fdo#111614]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][101] ([fdo#110723]) +2 similar issues [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-dg2: NOTRUN -> [SKIP][102] ([i915#5190]) +5 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html - shard-tglu: NOTRUN -> [SKIP][103] ([fdo#111615]) +1 similar issue [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html - shard-mtlp: NOTRUN -> [SKIP][104] ([i915#6187]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-mtlp: NOTRUN -> [SKIP][105] ([fdo#111615]) +4 similar issues [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: - shard-dg2: NOTRUN -> [SKIP][106] ([i915#4538] / [i915#5190]) +3 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-mtlp: NOTRUN -> [SKIP][107] ([i915#3886] / [i915#6095]) +5 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc: - shard-rkl: NOTRUN -> [SKIP][108] ([i915#5354] / [i915#6095]) +4 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs: - shard-dg2: NOTRUN -> [SKIP][109] ([i915#3689] / [i915#5354]) +12 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc: - shard-tglu: NOTRUN -> [SKIP][110] ([i915#5354] / [i915#6095]) +8 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-3/igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-rkl: NOTRUN -> [SKIP][111] ([i915#3886] / [i915#5354] / [i915#6095]) [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-tglu: NOTRUN -> [SKIP][112] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +2 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-7/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs: - shard-rkl: NOTRUN -> [SKIP][113] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs: - shard-tglu: NOTRUN -> [SKIP][114] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-5/igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs: - shard-dg2: NOTRUN -> [SKIP][115] ([i915#5354]) +18 similar issues [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html - shard-rkl: NOTRUN -> [SKIP][116] ([i915#5354]) +8 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-dg2: NOTRUN -> [SKIP][117] ([i915#3689] / [i915#3886] / [i915#5354]) +3 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc: - shard-tglu: NOTRUN -> [SKIP][118] ([i915#3689] / [i915#5354] / [i915#6095]) +9 similar issues [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-5/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: - shard-mtlp: NOTRUN -> [SKIP][119] ([i915#6095]) +16 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html * igt@kms_chamelium_audio@dp-audio: - shard-tglu: NOTRUN -> [SKIP][120] ([i915#7828]) +3 similar issues [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_chamelium_audio@dp-audio.html - shard-mtlp: NOTRUN -> [SKIP][121] ([i915#7828]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@kms_chamelium_audio@dp-audio.html * igt@kms_chamelium_color@ctm-0-50: - shard-tglu: NOTRUN -> [SKIP][122] ([fdo#111827]) +1 similar issue [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-6/igt@kms_chamelium_color@ctm-0-50.html * igt@kms_chamelium_color@ctm-0-75: - shard-mtlp: NOTRUN -> [SKIP][123] ([fdo#111827]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@kms_chamelium_color@ctm-0-75.html * igt@kms_chamelium_color@ctm-blue-to-red: - shard-dg2: NOTRUN -> [SKIP][124] ([fdo#111827]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_chamelium_color@ctm-blue-to-red.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: - shard-rkl: NOTRUN -> [SKIP][125] ([i915#7828]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html * igt@kms_chamelium_frames@hdmi-cmp-planar-formats: - shard-dg2: NOTRUN -> [SKIP][126] ([i915#7828]) +1 similar issue [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html * igt@kms_content_protection@legacy: - shard-dg2: NOTRUN -> [SKIP][127] ([i915#7118]) +2 similar issues [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-2/igt@kms_content_protection@legacy.html * igt@kms_content_protection@mei_interface: - shard-mtlp: NOTRUN -> [SKIP][128] ([i915#8063]) [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@uevent: - shard-rkl: NOTRUN -> [SKIP][129] ([i915#7118]) [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@cursor-onscreen-512x170: - shard-rkl: NOTRUN -> [SKIP][130] ([fdo#109279] / [i915#3359]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-512x170.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-tglu: NOTRUN -> [SKIP][131] ([i915#3359]) +1 similar issue [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_crc@cursor-random-32x10: - shard-mtlp: NOTRUN -> [SKIP][132] ([i915#8814]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_cursor_crc@cursor-random-32x10.html * igt@kms_cursor_crc@cursor-random-512x512: - shard-mtlp: NOTRUN -> [SKIP][133] ([i915#3359]) [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-512x512.html * igt@kms_cursor_crc@cursor-sliding-512x512: - shard-dg2: NOTRUN -> [SKIP][134] ([i915#3359]) +2 similar issues [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_cursor_crc@cursor-sliding-512x512.html - shard-rkl: NOTRUN -> [SKIP][135] ([i915#3359]) +1 similar issue [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-512x512.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-mtlp: NOTRUN -> [SKIP][136] ([i915#3546]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@cursora-vs-flipb-legacy: - shard-tglu: NOTRUN -> [SKIP][137] ([fdo#109274]) +3 similar issues [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-9/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-dg2: NOTRUN -> [SKIP][138] ([fdo#109274] / [i915#5354]) +1 similar issue [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html - shard-rkl: NOTRUN -> [SKIP][139] ([fdo#111825]) +1 similar issue [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-dg2: NOTRUN -> [SKIP][140] ([fdo#109274] / [fdo#111767] / [i915#5354]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html - shard-rkl: NOTRUN -> [SKIP][141] ([fdo#111767] / [fdo#111825]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][142] -> [FAIL][143] ([i915#2346]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html - shard-glk: [PASS][144] -> [FAIL][145] ([i915#2346]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][146] ([i915#3804]) [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html * igt@kms_dp_aux_dev: - shard-tglu: NOTRUN -> [SKIP][147] ([i915#1257]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@kms_dp_aux_dev.html * igt@kms_dsc@dsc-with-bpc-formats: - shard-tglu: NOTRUN -> [SKIP][148] ([i915#3555] / [i915#3840]) [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-9/igt@kms_dsc@dsc-with-bpc-formats.html * igt@kms_dsc@dsc-with-output-formats: - shard-mtlp: NOTRUN -> [SKIP][149] ([i915#3840]) [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_dsc@dsc-with-output-formats.html * igt@kms_fbcon_fbt@psr: - shard-dg2: NOTRUN -> [SKIP][150] ([i915#3469]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@kms_fbcon_fbt@psr.html - shard-rkl: NOTRUN -> [SKIP][151] ([fdo#110189] / [i915#3955]) [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_fbcon_fbt@psr.html * igt@kms_flip@2x-blocking-absolute-wf_vblank: - shard-tglu: NOTRUN -> [SKIP][152] ([fdo#109274] / [i915#3637]) +2 similar issues [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_flip@2x-blocking-absolute-wf_vblank.html * igt@kms_flip@2x-flip-vs-blocking-wf-vblank: - shard-snb: NOTRUN -> [SKIP][153] ([fdo#109271] / [fdo#111767]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html * igt@kms_flip@2x-flip-vs-fences-interruptible: - shard-mtlp: NOTRUN -> [SKIP][154] ([i915#8381]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_flip@2x-flip-vs-fences-interruptible.html * igt@kms_flip@2x-plain-flip-fb-recreate: - shard-apl: NOTRUN -> [SKIP][155] ([fdo#109271]) +24 similar issues [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl6/igt@kms_flip@2x-plain-flip-fb-recreate.html * igt@kms_flip@2x-plain-flip-interruptible: - shard-mtlp: NOTRUN -> [SKIP][156] ([i915#3637]) [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_flip@2x-plain-flip-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check-interruptible: - shard-dg2: NOTRUN -> [SKIP][157] ([fdo#109274]) [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-8/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][158] ([i915#2672]) [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][159] ([i915#2672]) +1 similar issue [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][160] ([i915#8810]) [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html * igt@kms_force_connector_basic@prune-stale-modes: - shard-mtlp: NOTRUN -> [SKIP][161] ([i915#5274]) [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_force_connector_basic@prune-stale-modes.html - shard-dg2: NOTRUN -> [SKIP][162] ([i915#5274]) [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][163] ([i915#8708]) +1 similar issue [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: - shard-dg2: [PASS][164] -> [FAIL][165] ([i915#6880]) [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-rkl: NOTRUN -> [SKIP][166] ([i915#3023]) +4 similar issues [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc: - shard-dg2: NOTRUN -> [SKIP][167] ([i915#8708]) +5 similar issues [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html - shard-rkl: NOTRUN -> [SKIP][168] ([fdo#111825] / [i915#1825]) +8 similar issues [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite: - shard-tglu: NOTRUN -> [SKIP][169] ([fdo#109280]) +14 similar issues [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4: - shard-tglu: NOTRUN -> [SKIP][170] ([i915#5439]) [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu: - shard-tglu: NOTRUN -> [SKIP][171] ([fdo#110189]) +12 similar issues [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render: - shard-dg2: NOTRUN -> [SKIP][172] ([i915#3458]) +3 similar issues [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu: - shard-mtlp: NOTRUN -> [SKIP][173] ([i915#1825]) +10 similar issues [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html * igt@kms_hdr@bpc-switch: - shard-tglu: NOTRUN -> [SKIP][174] ([i915#3555] / [i915#8228]) [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-7/igt@kms_hdr@bpc-switch.html * igt@kms_hdr@bpc-switch-suspend: - shard-rkl: NOTRUN -> [SKIP][175] ([i915#3555] / [i915#8228]) [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_hdr@static-toggle: - shard-dg2: NOTRUN -> [SKIP][176] ([i915#3555] / [i915#8228]) +1 similar issue [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_hdr@static-toggle.html * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c: - shard-tglu: NOTRUN -> [SKIP][177] ([fdo#109289]) +1 similar issue [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-7/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html * igt@kms_plane_scaling@intel-max-src-size: - shard-dg2: NOTRUN -> [SKIP][178] ([i915#6953]) [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_plane_scaling@intel-max-src-size.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1: - shard-snb: NOTRUN -> [SKIP][179] ([fdo#109271]) +101 similar issues [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1.html * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][180] ([i915#5176]) +15 similar issues [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][181] ([i915#5176]) +7 similar issues [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2.html * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][182] ([i915#5235]) +15 similar issues [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1: - shard-mtlp: NOTRUN -> [SKIP][183] ([i915#5235]) +3 similar issues [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][184] ([i915#5235]) +3 similar issues [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html * igt@kms_psr2_sf@cursor-plane-move-continuous-sf: - shard-apl: NOTRUN -> [SKIP][185] ([fdo#109271] / [i915#658]) [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl6/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-dg2: NOTRUN -> [SKIP][186] ([i915#658]) +1 similar issue [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html - shard-mtlp: NOTRUN -> [SKIP][187] ([i915#4348]) [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-tglu: NOTRUN -> [SKIP][188] ([fdo#109642] / [fdo#111068] / [i915#658]) +1 similar issue [188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@primary_mmap_cpu: - shard-dg2: NOTRUN -> [SKIP][189] ([i915#1072]) +4 similar issues [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@kms_psr@primary_mmap_cpu.html - shard-rkl: NOTRUN -> [SKIP][190] ([i915#1072]) +2 similar issues [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_psr@primary_mmap_cpu.html * igt@kms_psr@psr2_cursor_blt: - shard-mtlp: [PASS][191] -> [FAIL][192] ([i915#8726]) [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@kms_psr@psr2_cursor_blt.html [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@kms_psr@psr2_cursor_blt.html * igt@kms_psr@psr2_cursor_mmap_gtt: - shard-mtlp: NOTRUN -> [SKIP][193] ([i915#4077]) +2 similar issues [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_psr@psr2_cursor_mmap_gtt.html * igt@kms_rmfb@close-fd@pipe-a-edp-1: - shard-mtlp: [PASS][194] -> [DMESG-WARN][195] ([i915#1982]) [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-1/igt@kms_rmfb@close-fd@pipe-a-edp-1.html [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_rmfb@close-fd@pipe-a-edp-1.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270: - shard-mtlp: NOTRUN -> [SKIP][196] ([i915#4235]) [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html * igt@kms_scaling_modes@scaling-mode-full: - shard-tglu: NOTRUN -> [SKIP][197] ([i915#3555]) +2 similar issues [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_scaling_modes@scaling-mode-full.html * igt@kms_tiled_display@basic-test-pattern: - shard-tglu: NOTRUN -> [SKIP][198] ([i915#8623]) [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_tiled_display@basic-test-pattern.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-mtlp: NOTRUN -> [SKIP][199] ([i915#8623]) [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_vblank@pipe-c-query-forked-busy: - shard-rkl: NOTRUN -> [SKIP][200] ([i915#4070] / [i915#6768]) [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_vblank@pipe-c-query-forked-busy.html * igt@kms_vblank@pipe-d-wait-idle: - shard-rkl: NOTRUN -> [SKIP][201] ([i915#4070] / [i915#533] / [i915#6768]) [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_vblank@pipe-d-wait-idle.html * igt@kms_writeback@writeback-pixel-formats: - shard-tglu: NOTRUN -> [SKIP][202] ([i915#2437]) [202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-6/igt@kms_writeback@writeback-pixel-formats.html * igt@perf@oa-exponents@0-rcs0: - shard-glk: [PASS][203] -> [ABORT][204] ([i915#5213] / [i915#7941]) [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@perf@oa-exponents@0-rcs0.html [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk6/igt@perf@oa-exponents@0-rcs0.html * igt@perf_pmu@event-wait@rcs0: - shard-mtlp: NOTRUN -> [SKIP][205] ([i915#8807]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@perf_pmu@event-wait@rcs0.html * igt@perf_pmu@rc6@other-idle-gt0: - shard-dg2: NOTRUN -> [SKIP][206] ([i915#8516]) [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-8/igt@perf_pmu@rc6@other-idle-gt0.html - shard-tglu: NOTRUN -> [SKIP][207] ([i915#8516]) [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@perf_pmu@rc6@other-idle-gt0.html * igt@perf_pmu@render-node-busy-idle@ccs0: - shard-mtlp: [PASS][208] -> [FAIL][209] ([i915#4349]) +7 similar issues [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@perf_pmu@render-node-busy-idle@ccs0.html [209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@perf_pmu@render-node-busy-idle@ccs0.html * igt@prime_vgem@basic-gtt: - shard-mtlp: NOTRUN -> [SKIP][210] ([i915#3708] / [i915#4077]) [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@prime_vgem@basic-gtt.html * igt@sysfs_heartbeat_interval@nopreempt@bcs0: - shard-mtlp: [PASS][211] -> [FAIL][212] ([i915#6015]) +1 similar issue [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html * igt@sysfs_preempt_timeout@timeout@vecs0: - shard-mtlp: [PASS][213] -> [ABORT][214] ([i915#8521]) [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@sysfs_preempt_timeout@timeout@vecs0.html * igt@v3d/v3d_perfmon@create-perfmon-exceed: - shard-mtlp: NOTRUN -> [SKIP][215] ([i915#2575]) +5 similar issues [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@v3d/v3d_perfmon@create-perfmon-exceed.html * igt@v3d/v3d_submit_cl@valid-submission: - shard-tglu: NOTRUN -> [SKIP][216] ([fdo#109315] / [i915#2575]) +4 similar issues [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@v3d/v3d_submit_cl@valid-submission.html * igt@v3d/v3d_submit_csd@bad-multisync-in-sync: - shard-dg2: NOTRUN -> [SKIP][217] ([i915#2575]) +2 similar issues [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html - shard-rkl: NOTRUN -> [SKIP][218] ([fdo#109315]) +2 similar issues [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html * igt@vc4/vc4_mmap@mmap-bo: - shard-dg2: NOTRUN -> [SKIP][219] ([i915#7711]) +3 similar issues [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@vc4/vc4_mmap@mmap-bo.html - shard-rkl: NOTRUN -> [SKIP][220] ([i915#7711]) +2 similar issues [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@vc4/vc4_mmap@mmap-bo.html * igt@vc4/vc4_perfmon@create-perfmon-exceed: - shard-mtlp: NOTRUN -> [SKIP][221] ([i915#7711]) +3 similar issues [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@vc4/vc4_perfmon@create-perfmon-exceed.html * igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged: - shard-tglu: NOTRUN -> [SKIP][222] ([i915#2575]) +4 similar issues [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged.html * igt@vgem_basic@bad-pad: - shard-mtlp: [PASS][223] -> [DMESG-WARN][224] ([i915#2017]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@vgem_basic@bad-pad.html [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@vgem_basic@bad-pad.html #### Possible fixes #### * igt@gem_create@hog-create@smem0: - shard-dg2: [FAIL][225] ([i915#5892] / [i915#8758]) -> [PASS][226] [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@gem_create@hog-create@smem0.html [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@gem_create@hog-create@smem0.html * igt@gem_eio@hibernate: - {shard-dg1}: [ABORT][227] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][228] [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-14/igt@gem_eio@hibernate.html [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-16/igt@gem_eio@hibernate.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][229] ([i915#2842]) -> [PASS][230] [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-rkl: [FAIL][231] ([i915#2842]) -> [PASS][232] +3 similar issues [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-4/igt@gem_exec_fair@basic-throttle@rcs0.html [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-mtlp: [ABORT][233] ([i915#8131]) -> [PASS][234] [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-forked-all.html [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-mtlp: [FAIL][235] ([i915#6363]) -> [PASS][236] [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@gem_exec_whisper@basic-fds-priority-all.html [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@gem_exec_whisper@basic-fds-priority-all.html * igt@gem_lmem_swapping@smem-oom@lmem0: - {shard-dg1}: [DMESG-WARN][237] ([i915#4936] / [i915#5493]) -> [PASS][238] [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@i915_hangman@engine-engine-hang@vcs0: - shard-mtlp: [FAIL][239] ([i915#7069]) -> [PASS][240] [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@i915_hangman@engine-engine-hang@vcs0.html [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@i915_hangman@engine-engine-hang@vcs0.html * igt@i915_module_load@reload-with-fault-injection: - shard-mtlp: [ABORT][241] ([i915#8489] / [i915#8668]) -> [PASS][242] [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_dc@dc9-dpms: - shard-tglu: [SKIP][243] ([i915#4281]) -> [PASS][244] [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - {shard-dg1}: [FAIL][245] ([i915#3591]) -> [PASS][246] +1 similar issue [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_pm_rpm@cursor-dpms: - shard-tglu: [FAIL][247] ([i915#7940]) -> [PASS][248] +1 similar issue [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-4/igt@i915_pm_rpm@cursor-dpms.html [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@i915_pm_rpm@cursor-dpms.html * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - {shard-dg1}: [SKIP][249] ([i915#1397]) -> [PASS][250] [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-15/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-19/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-rkl: [SKIP][251] ([i915#1397]) -> [PASS][252] +1 similar issue [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-dg2: [SKIP][253] ([i915#1397]) -> [PASS][254] +2 similar issues [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html * igt@i915_selftest@live@gt_mocs: - shard-mtlp: [DMESG-FAIL][255] ([i915#7059]) -> [PASS][256] [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@i915_selftest@live@gt_mocs.html [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@hangcheck: - shard-dg2: [ABORT][257] ([i915#7913]) -> [PASS][258] [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-7/igt@i915_selftest@live@hangcheck.html [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@workarounds: - shard-mtlp: [DMESG-FAIL][259] ([i915#6763]) -> [PASS][260] [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@i915_selftest@live@workarounds.html [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@i915_selftest@live@workarounds.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-mtlp: [FAIL][261] ([i915#3743]) -> [PASS][262] [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][263] ([i915#72]) -> [PASS][264] [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-mtlp: [FAIL][265] ([i915#8248]) -> [PASS][266] [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [FAIL][267] ([i915#2346]) -> [PASS][268] [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4: - {shard-dg1}: [FAIL][269] ([i915#79]) -> [PASS][270] [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-17/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4.html [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-17/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: [ABORT][271] ([i915#180]) -> [PASS][272] [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: - shard-dg2: [FAIL][273] ([i915#6880]) -> [PASS][274] +1 similar issue [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2: - shard-rkl: [FAIL][275] ([i915#8292]) -> [PASS][276] [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html * igt@kms_sysfs_edid_timing: - shard-dg2: [FAIL][277] ([IGT#2]) -> [PASS][278] [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-5/igt@kms_sysfs_edid_timing.html [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-11/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-dg2: [FAIL][279] ([fdo#103375] / [i915#6121]) -> [PASS][280] [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@perf_pmu@busy-double-start@ccs0: - shard-mtlp: [FAIL][281] ([i915#4349]) -> [PASS][282] [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-4/igt@perf_pmu@busy-double-start@ccs0.html [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@perf_pmu@busy-double-start@ccs0.html * igt@perf_pmu@most-busy-idle-check-all@bcs0: - shard-mtlp: [FAIL][283] ([i915#5234]) -> [PASS][284] +1 similar issue [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@perf_pmu@most-busy-idle-check-all@bcs0.html [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@perf_pmu@most-busy-idle-check-all@bcs0.html * igt@perf_pmu@most-busy-idle-check-all@rcs0: - shard-dg2: [FAIL][285] ([i915#5234]) -> [PASS][286] [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-5/igt@perf_pmu@most-busy-idle-check-all@rcs0.html [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html - {shard-dg1}: [FAIL][287] ([i915#5234]) -> [PASS][288] [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-13/igt@perf_pmu@most-busy-idle-check-all@rcs0.html [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-18/igt@perf_pmu@most-busy-idle-check-all@rcs0.html * igt@sysfs_timeslice_duration@timeout@vecs0: - shard-mtlp: [ABORT][289] ([i915#8521]) -> [PASS][290] [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-2/igt@sysfs_timeslice_duration@timeout@vecs0.html [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@sysfs_timeslice_duration@timeout@vecs0.html #### Warnings #### * igt@gem_exec_suspend@basic-s0@smem: - shard-snb: [DMESG-FAIL][291] ([fdo#103375]) -> [DMESG-WARN][292] ([i915#8841]) [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-snb7/igt@gem_exec_suspend@basic-s0@smem.html [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb4/igt@gem_exec_suspend@basic-s0@smem.html * igt@i915_pm_rc6_residency@rc6-idle@bcs0: - shard-tglu: [FAIL][293] ([i915#2681] / [i915#3591]) -> [WARN][294] ([i915#2681]) [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-tglu: [WARN][295] ([i915#2681]) -> [FAIL][296] ([i915#2681] / [i915#3591]) [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_suspend@basic-s2idle-without-i915: - shard-snb: [DMESG-WARN][297] ([i915#8841]) -> [ABORT][298] ([i915#4528] / [i915#8213]) [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-snb7/igt@i915_suspend@basic-s2idle-without-i915.html [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb4/igt@i915_suspend@basic-s2idle-without-i915.html * igt@kms_content_protection@mei_interface: - shard-dg2: [SKIP][299] ([i915#7118] / [i915#7162]) -> [SKIP][300] ([i915#7118]) [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@kms_content_protection@mei_interface.html [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_content_protection@mei_interface.html - shard-rkl: [SKIP][301] ([fdo#109300]) -> [SKIP][302] ([i915#7118]) [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-1/igt@kms_content_protection@mei_interface.html [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-6/igt@kms_content_protection@mei_interface.html - shard-tglu: [SKIP][303] ([fdo#109300]) -> [SKIP][304] ([i915#6944] / [i915#7116] / [i915#7118]) [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-7/igt@kms_content_protection@mei_interface.html [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@kms_content_protection@mei_interface.html * igt@kms_force_connector_basic@force-load-detect: - shard-rkl: [SKIP][305] ([fdo#109285] / [i915#4098]) -> [SKIP][306] ([fdo#109285]) [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem: - shard-dg2: [CRASH][307] ([i915#7331]) -> [INCOMPLETE][308] ([i915#5493]) [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936 [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892 [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121 [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6363]: https://gitlab.freedesktop.org/drm/intel/issues/6363 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331 [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7816]: https://gitlab.freedesktop.org/drm/intel/issues/7816 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916 [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940 [i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8063]: https://gitlab.freedesktop.org/drm/intel/issues/8063 [i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102 [i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228 [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247 [i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248 [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292 [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428 [i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430 [i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489 [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502 [i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503 [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516 [i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521 [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623 [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708 [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709 [i915#8726]: https://gitlab.freedesktop.org/drm/intel/issues/8726 [i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758 [i915#8807]: https://gitlab.freedesktop.org/drm/intel/issues/8807 [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810 [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814 [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7380 -> IGTPW_9383 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html --===============4120151199789869305== Content-Type: text/html; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Project List - Patchwork Patch Details
Series:Extend intel_blt to work on Xe (rev3)
URL:https://patchwork.freedesktop.org/series/120162/
State:failure
Details:https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html

CI Bug Log - changes from CI_DRM_13369_full -> IGTPW_9383_full

Summary

FAILURE

Serious unknown changes coming with IGTPW_9383_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in IGTPW_9383_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html

Participating hosts (9 -> 9)

No changes in participating hosts

Possible new issues

Here are the unknown changes that may have been introduced in IGTPW_9383_full:

IGT changes

Possible regressions

  • igt@prime_vgem@fence-wait@ccs0:

  • igt@prime_vgem@fence-wait@vecs0:

  • igt@vgem_basic@sysfs:

Known issues

Here are the changes found in IGTPW_9383_full that come from known issues:

IGT changes

Issues hit

  • igt@api_intel_bb@crc32:

  • igt@device_reset@unbind-cold-reset-rebind:

  • igt@drm_fdinfo@busy-hang@bcs0:

  • igt@drm_fdinfo@most-busy-idle-check-all@rcs0:

  • igt@drm_fdinfo@virtual-busy-all:

  • igt@gem_bad_reloc@negative-reloc-bltcopy:

  • igt@gem_basic@multigpu-create-close:

  • igt@gem_ccs@block-copy-compressed:

  • igt@gem_ccs@ctrl-surf-copy-new-ctx:

  • igt@gem_close_race@multigpu-basic-process:

  • igt@gem_create@create-ext-cpu-access-big:

  • igt@gem_ctx_exec@basic-nohangcheck:

  • igt@gem_ctx_param@set-priority-not-supported:

  • igt@gem_ctx_persistence@saturated-hostile@vecs0:

  • igt@gem_eio@in-flight-contexts-1us:

  • igt@gem_eio@kms:

  • igt@gem_exec_balancer@bonded-true-hang:

  • igt@gem_exec_fair@basic-none@bcs0:

  • igt@gem_exec_fair@basic-pace@vcs0:

  • igt@gem_exec_fair@basic-throttle:

  • igt@gem_exec_fence@submit67:

  • igt@gem_exec_params@secure-non-root:

  • igt@gem_exec_reloc@basic-write-gtt-active:

  • igt@gem_exec_whisper@basic-forked:

  • igt@gem_exec_whisper@basic-forked-all:

  • igt@gem_lmem_swapping@heavy-verify-random-ccs:

  • igt@gem_lmem_swapping@parallel-multi:

  • igt@gem_lmem_swapping@parallel-random:

  • igt@gem_lmem_swapping@smem-oom@lmem0:

  • igt@gem_media_vme:

  • igt@gem_mmap_wc@write:

  • igt@gem_partial_pwrite_pread@reads:

  • igt@gem_partial_pwrite_pread@writes-after-reads:

  • igt@gem_pxp@create-regular-buffer:

  • igt@gem_pxp@fail-invalid-protected-context:

  • igt@gem_readwrite@beyond-eob:

  • igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:

  • igt@gem_set_tiling_vs_pwrite:

  • igt@gem_tiled_fence_blits@basic:

  • igt@gem_tiled_pread_basic:

  • igt@gem_userptr_blits@coherency-unsync:

  • igt@gem_userptr_blits@invalid-mmap-offset-unsync:

  • igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:

  • igt@gem_userptr_blits@nohangcheck:

  • igt@gen7_exec_parse@load-register-reg:

  • igt@gen7_exec_parse@oacontrol-tracking:

  • igt@gen9_exec_parse@bb-large:

  • igt@i915_hangman@gt-engine-error@vcs0:

  • igt@i915_module_load@load:

  • igt@i915_pm_backlight@bad-brightness:

  • igt@i915_pm_dc@dc5-psr:

  • igt@i915_pm_dc@dc9-dpms:

  • igt@i915_pm_lpsp@screens-disabled:

  • igt@i915_pm_rpm@modeset-non-lpsp-stress:

  • igt@i915_pm_rpm@pc8-residency:

  • igt@i915_pm_rpm@system-suspend-execbuf:

  • igt@i915_suspend@basic-s3-without-i915:

  • igt@i915_suspend@debugfs-reader:

  • igt@i915_suspend@fence-restore-tiled2untiled:

  • igt@kms_addfb_basic@addfb25-x-tiled-legacy:

  • igt@kms_addfb_basic@basic-y-tiled-legacy:

  • igt@kms_async_flips@crc@pipe-a-hdmi-a-3:

  • igt@kms_big_fb@4-tiled-16bpp-rotate-90:

  • igt@kms_big_fb@4-tiled-8bpp-rotate-270:

  • igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:

  • igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:

  • igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:

  • igt@kms_big_fb@x-tiled-32bpp-rotate-90:

  • igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:

  • igt@kms_big_fb@y-tiled-8bpp-rotate-90:

  • igt@kms_big_fb@yf-tiled-64bpp-rotate-90:

  • igt@kms_big_fb@yf-tiled-addfb-size-overflow:

  • igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:

  • igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:

  • igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:

  • igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:

  • igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:

  • igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:

  • igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:

  • igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:

  • igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:

  • igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs:

  • igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs:

  • igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:

  • igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:

  • igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:

  • igt@kms_chamelium_audio@dp-audio:

  • igt@kms_chamelium_color@ctm-0-50:

  • igt@kms_chamelium_color@ctm-0-75:

  • igt@kms_chamelium_color@ctm-blue-to-red:

  • igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:

  • igt@kms_chamelium_frames@hdmi-cmp-planar-formats:

  • igt@kms_content_protection@legacy:

  • igt@kms_content_protection@mei_interface:

  • igt@kms_content_protection@uevent:

  • igt@kms_cursor_crc@cursor-onscreen-512x170:

  • igt@kms_cursor_crc@cursor-onscreen-512x512:

  • igt@kms_cursor_crc@cursor-random-32x10:

  • igt@kms_cursor_crc@cursor-random-512x512:

  • igt@kms_cursor_crc@cursor-sliding-512x512:

  • igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:

  • igt@kms_cursor_legacy@cursora-vs-flipb-legacy:

  • igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:

  • igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:

  • igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:

  • igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:

  • igt@kms_dp_aux_dev:

  • igt@kms_dsc@dsc-with-bpc-formats:

  • igt@kms_dsc@dsc-with-output-formats:

  • igt@kms_fbcon_fbt@psr:

  • igt@kms_flip@2x-blocking-absolute-wf_vblank:

  • igt@kms_flip@2x-flip-vs-blocking-wf-vblank:

  • igt@kms_flip@2x-flip-vs-fences-interruptible:

  • igt@kms_flip@2x-plain-flip-fb-recreate:

  • igt@kms_flip@2x-plain-flip-interruptible:

  • igt@kms_flip@2x-wf_vblank-ts-check-interruptible:

  • igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:

  • igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:

  • igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:

  • igt@kms_force_connector_basic@prune-stale-modes:

  • igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:

  • igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:

  • igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:

  • igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:

  • igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:

  • igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:

  • igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:

  • igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:

  • igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:

  • igt@kms_hdr@bpc-switch:

  • igt@kms_hdr@bpc-switch-suspend:

  • igt@kms_hdr@static-toggle:

  • igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:

  • igt@kms_plane_scaling@intel-max-src-size:

  • igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:

  • igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1:

  • igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2:

  • igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:

  • igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1:

  • igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:

  • igt@kms_psr2_sf@cursor-plane-move-continuous-sf:

  • igt@kms_psr2_su@frontbuffer-xrgb8888:

  • igt@kms_psr2_su@page_flip-xrgb8888:

  • igt@kms_psr@primary_mmap_cpu:

  • igt@kms_psr@psr2_cursor_blt:

  • igt@kms_psr@psr2_cursor_mmap_gtt:

  • igt@kms_rmfb@close-fd@pipe-a-edp-1:

  • igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:

  • igt@kms_scaling_modes@scaling-mode-full:

  • igt@kms_tiled_display@basic-test-pattern:

  • igt@kms_tiled_display@basic-test-pattern-with-chamelium:

  • igt@kms_vblank@pipe-c-query-forked-busy:

  • igt@kms_vblank@pipe-d-wait-idle:

  • igt@kms_writeback@writeback-pixel-formats:

  • igt@perf@oa-exponents@0-rcs0:

  • igt@perf_pmu@event-wait@rcs0:

  • igt@perf_pmu@rc6@other-idle-gt0:

  • igt@perf_pmu@render-node-busy-idle@ccs0:

  • igt@prime_vgem@basic-gtt:

  • igt@sysfs_heartbeat_interval@nopreempt@bcs0:

  • igt@sysfs_preempt_timeout@timeout@vecs0:

  • igt@v3d/v3d_perfmon@create-perfmon-exceed:

  • igt@v3d/v3d_submit_cl@valid-submission:

  • igt@v3d/v3d_submit_csd@bad-multisync-in-sync:

  • igt@vc4/vc4_mmap@mmap-bo:

  • igt@vc4/vc4_perfmon@create-perfmon-exceed:

  • igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged:

  • igt@vgem_basic@bad-pad:

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

  • CI: CI-20190529 -> None
  • IGT: IGT_7380 -> IGTPW_9383
  • Piglit: piglit_4509 -> None

CI-20190529: 20190529
CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html
IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

--===============4120151199789869305==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id A8F6610E49F for ; Wed, 12 Jul 2023 07:27:51 +0000 (UTC) Message-ID: Date: Wed, 12 Jul 2023 09:27:34 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-3-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-3-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 02/17] lib/intel_allocator: Drop aliasing allocator handle api List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:19, Zbigniew Kempczyński wrote: > There's no real user of this api, lets drop it. > > Signed-off-by: Zbigniew Kempczyński > -- > v3: Remove also ipc message passing for open-as (Karolina) > --- > lib/intel_allocator.c | 73 -------------------------------- > lib/intel_allocator.h | 1 - > lib/intel_allocator_msgchannel.h | 8 +--- > 3 files changed, 1 insertion(+), 81 deletions(-) > Reviewed-by: Karolina Stolarek > diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c > index 8161221dbf..09f665fbb9 100644 > --- a/lib/intel_allocator.c > +++ b/lib/intel_allocator.c > @@ -25,7 +25,6 @@ > static const char *reqtype_str[] = { > [REQ_STOP] = "stop", > [REQ_OPEN] = "open", > - [REQ_OPEN_AS] = "open as", > [REQ_CLOSE] = "close", > [REQ_ADDRESS_RANGE] = "address range", > [REQ_ALLOC] = "alloc", > @@ -376,19 +375,6 @@ static struct allocator *allocator_open(int fd, uint32_t ctx, uint32_t vm, > return al; > } > > -static struct allocator *allocator_open_as(struct allocator *base, > - uint32_t new_vm, uint64_t *ahndp) > -{ > - struct allocator *al; > - > - igt_assert(ahndp); > - al = __allocator_create(base->fd, base->ctx, new_vm, base->ial); > - __allocator_get(al); > - *ahndp = __handle_create(al); > - > - return al; > -} > - > static bool allocator_close(uint64_t ahnd) > { > struct allocator *al; > @@ -512,47 +498,6 @@ static int handle_request(struct alloc_req *req, struct alloc_resp *resp) > refcnt - 1, refcnt, ret - 1, ret); > break; > > - case REQ_OPEN_AS: > - /* lock first to avoid concurrent close */ > - pthread_mutex_lock(&map_mutex); > - > - al = __allocator_find_by_handle(req->allocator_handle); > - resp->response_type = RESP_OPEN_AS; > - > - if (!al) { > - alloc_info(" [tid: %ld] ahnd: %" PRIx64 > - " -> no handle\n", > - (long) req->tid, req->allocator_handle); > - pthread_mutex_unlock(&map_mutex); > - break; > - } > - > - if (!al->vm) { > - alloc_info(" [tid: %ld] ahnd: %" PRIx64 > - " -> only open as for is possible\n", > - (long) req->tid, req->allocator_handle); > - pthread_mutex_unlock(&map_mutex); > - break; > - } > - > - > - al = allocator_open_as(al, req->open_as.new_vm, &ahnd); > - refcnt = atomic_load(&al->refcount); > - ret = atomic_load(&al->ial->refcount); > - pthread_mutex_unlock(&map_mutex); > - > - resp->response_type = RESP_OPEN_AS; > - resp->open.allocator_handle = ahnd; > - > - alloc_info(" [tid: %ld] fd: %d, ahnd: %" PRIx64 > - ", ctx: %u, vm: %u" > - ", alloc_type: %u, al->refcnt: %ld->%ld" > - ", refcnt: %d->%d\n", > - (long) req->tid, al->fd, ahnd, > - al->ctx, al->vm, al->ial->type, > - refcnt - 1, refcnt, ret - 1, ret); > - break; > - > case REQ_CLOSE: > pthread_mutex_lock(&map_mutex); > al = __allocator_find_by_handle(req->allocator_handle); > @@ -1037,24 +982,6 @@ uint64_t intel_allocator_open_vm(int fd, uint32_t vm, uint8_t allocator_type) > ALLOC_STRATEGY_HIGH_TO_LOW, 0); > } > > -uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm) > -{ > - struct alloc_req req = { .request_type = REQ_OPEN_AS, > - .allocator_handle = allocator_handle, > - .open_as.new_vm = new_vm }; > - struct alloc_resp resp; > - > - /* Get child_tid only once at open() */ > - if (child_tid == -1) > - child_tid = gettid(); > - > - igt_assert(handle_request(&req, &resp) == 0); > - igt_assert(resp.open_as.allocator_handle); > - igt_assert(resp.response_type == RESP_OPEN_AS); > - > - return resp.open.allocator_handle; > -} > - > /** > * intel_allocator_close: > * @allocator_handle: handle to the allocator that will be closed > diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h > index a6bf573e9d..3ec74f6191 100644 > --- a/lib/intel_allocator.h > +++ b/lib/intel_allocator.h > @@ -182,7 +182,6 @@ uint64_t intel_allocator_open_vm_full(int fd, uint32_t vm, > enum allocator_strategy strategy, > uint64_t default_alignment); > > -uint64_t intel_allocator_open_vm_as(uint64_t allocator_handle, uint32_t new_vm); > bool intel_allocator_close(uint64_t allocator_handle); > void intel_allocator_get_address_range(uint64_t allocator_handle, > uint64_t *startp, uint64_t *endp); > diff --git a/lib/intel_allocator_msgchannel.h b/lib/intel_allocator_msgchannel.h > index cefbf4ce33..ba38530fd1 100644 > --- a/lib/intel_allocator_msgchannel.h > +++ b/lib/intel_allocator_msgchannel.h > @@ -13,7 +13,6 @@ > enum reqtype { > REQ_STOP, > REQ_OPEN, > - REQ_OPEN_AS, > REQ_CLOSE, > REQ_ADDRESS_RANGE, > REQ_ALLOC, > @@ -27,7 +26,6 @@ enum reqtype { > > enum resptype { > RESP_OPEN, > - RESP_OPEN_AS, > RESP_CLOSE, > RESP_ADDRESS_RANGE, > RESP_ALLOC, > @@ -58,10 +56,6 @@ struct alloc_req { > uint64_t default_alignment; > } open; > > - struct { > - uint32_t new_vm; > - } open_as; > - > struct { > uint32_t handle; > uint64_t size; > @@ -100,7 +94,7 @@ struct alloc_resp { > union { > struct { > uint64_t allocator_handle; > - } open, open_as; > + } open; > > struct { > bool is_empty; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F02610E49F for ; Wed, 12 Jul 2023 07:33:41 +0000 (UTC) Message-ID: <02ceddc0-2934-d9ae-ad82-180989f8c9b1@intel.com> Date: Wed, 12 Jul 2023 09:33:25 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-5-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-5-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 04/17] lib/xe_ioctl: Export non-assert xe_exec function List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:19, Zbigniew Kempczyński wrote: > Export __xe_exec() helper to allow caller to handle the error > individually. > > Signed-off-by: Zbigniew Kempczyński > --- > lib/xe/xe_ioctl.c | 2 +- > lib/xe/xe_ioctl.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) That change is fine by me, but if you're really keen, you can check it with others. But for now: Reviewed-by: Karolina Stolarek > > diff --git a/lib/xe/xe_ioctl.c b/lib/xe/xe_ioctl.c > index 9ead7307c4..0b5c7a4fce 100644 > --- a/lib/xe/xe_ioctl.c > +++ b/lib/xe/xe_ioctl.c > @@ -357,7 +357,7 @@ void *xe_bo_mmap_ext(int fd, uint32_t bo, size_t size, int prot) > return __xe_bo_map(fd, bo, size, prot); > } > > -static int __xe_exec(int fd, struct drm_xe_exec *exec) > +int __xe_exec(int fd, struct drm_xe_exec *exec) > { > int err = 0; > > diff --git a/lib/xe/xe_ioctl.h b/lib/xe/xe_ioctl.h > index e014ad66c9..320e0f9f68 100644 > --- a/lib/xe/xe_ioctl.h > +++ b/lib/xe/xe_ioctl.h > @@ -75,6 +75,7 @@ void xe_engine_destroy(int fd, uint32_t engine); > uint64_t xe_bo_mmap_offset(int fd, uint32_t bo); > void *xe_bo_map(int fd, uint32_t bo, size_t size); > void *xe_bo_mmap_ext(int fd, uint32_t bo, size_t size, int prot); > +int __xe_exec(int fd, struct drm_xe_exec *exec); > void xe_exec(int fd, struct drm_xe_exec *exec); > void xe_exec_sync(int fd, uint32_t engine, uint64_t addr, > struct drm_xe_sync *sync, uint32_t num_syncs); From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D8C710E033 for ; Wed, 12 Jul 2023 08:01:06 +0000 (UTC) Message-ID: <97399ca5-86a2-1b05-a120-73fcb99c2eba@intel.com> Date: Wed, 12 Jul 2023 10:00:45 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-10-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-10-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 09/17] lib/xe_util: Add vm bind/unbind helper for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > Before calling exec we need to prepare vm to contain valid entries. > Bind/unbind in xe expects single bind_op or vector of bind_ops what > makes preparation of it a little bit inconvinient. Add function > which iterates over list of xe_object (auxiliary structure which > describes bind information for object) and performs the bind/unbind > in one step. It also supports passing syncobj in/out to work in > pipelined executions. > > Signed-off-by: Zbigniew Kempczyński I'll see how the changes are used in 10/17, but the helpers themself look good to me: Reviewed-by: Karolina Stolarek > -- > v3: - Drop priv field in the structure > --- > lib/xe/xe_util.c | 125 +++++++++++++++++++++++++++++++++++++++++++++++ > lib/xe/xe_util.h | 17 +++++++ > 2 files changed, 142 insertions(+) > > diff --git a/lib/xe/xe_util.c b/lib/xe/xe_util.c > index 5f0f69a8c6..7d78065a13 100644 > --- a/lib/xe/xe_util.c > +++ b/lib/xe/xe_util.c > @@ -102,3 +102,128 @@ char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set) > return name; > } > > +#ifdef XEBINDDBG > +#define bind_info igt_info > +#define bind_debug igt_debug > +#else > +#define bind_info(...) {} > +#define bind_debug(...) {} > +#endif > + > +static struct drm_xe_vm_bind_op *xe_alloc_bind_ops(struct igt_list_head *obj_list, > + uint32_t *num_ops) > +{ > + struct drm_xe_vm_bind_op *bind_ops, *ops; > + struct xe_object *obj; > + uint32_t num_objects = 0, i = 0, op; > + > + igt_list_for_each_entry(obj, obj_list, link) > + num_objects++; > + > + *num_ops = num_objects; > + if (!num_objects) { > + bind_info(" [nothing to bind]\n"); > + return NULL; > + } > + > + bind_ops = calloc(num_objects, sizeof(*bind_ops)); > + igt_assert(bind_ops); > + > + igt_list_for_each_entry(obj, obj_list, link) { > + ops = &bind_ops[i]; > + > + if (obj->bind_op == XE_OBJECT_BIND) { > + op = XE_VM_BIND_OP_MAP | XE_VM_BIND_FLAG_ASYNC; > + ops->obj = obj->handle; > + } else { > + op = XE_VM_BIND_OP_UNMAP | XE_VM_BIND_FLAG_ASYNC; > + } > + > + ops->op = op; > + ops->obj_offset = 0; > + ops->addr = obj->offset; > + ops->range = obj->size; > + ops->region = 0; > + > + bind_info(" [%d]: [%6s] handle: %u, offset: %llx, size: %llx\n", > + i, obj->bind_op == XE_OBJECT_BIND ? "BIND" : "UNBIND", > + ops->obj, (long long)ops->addr, (long long)ops->range); > + i++; > + } > + > + return bind_ops; > +} > + > +/** > + * xe_bind_unbind_async: > + * @xe: drm fd of Xe device > + * @vm: vm to bind/unbind objects to/from > + * @bind_engine: bind engine, 0 if default > + * @obj_list: list of xe_object > + * @sync_in: sync object (fence-in), 0 if there's no input dependency > + * @sync_out: sync object (fence-out) to signal on bind/unbind completion, > + * if 0 wait for bind/unbind completion. > + * > + * Function iterates over xe_object @obj_list, prepares binding operation > + * and does bind/unbind in one step. Providing sync_in / sync_out allows > + * working in pipelined mode. With sync_in and sync_out set to 0 function > + * waits until binding operation is complete. > + */ > +void xe_bind_unbind_async(int xe, uint32_t vm, uint32_t bind_engine, > + struct igt_list_head *obj_list, > + uint32_t sync_in, uint32_t sync_out) > +{ > + struct drm_xe_vm_bind_op *bind_ops; > + struct drm_xe_sync tabsyncs[2] = { > + { .flags = DRM_XE_SYNC_SYNCOBJ, .handle = sync_in }, > + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, .handle = sync_out }, > + }; > + struct drm_xe_sync *syncs; > + uint32_t num_binds = 0; > + int num_syncs; > + > + bind_info("[Binding to vm: %u]\n", vm); > + bind_ops = xe_alloc_bind_ops(obj_list, &num_binds); > + > + if (!num_binds) { > + if (sync_out) > + syncobj_signal(xe, &sync_out, 1); > + return; > + } > + > + if (sync_in) { > + syncs = tabsyncs; > + num_syncs = 2; > + } else { > + syncs = &tabsyncs[1]; > + num_syncs = 1; > + } > + > + /* User didn't pass sync out, create it and wait for completion */ > + if (!sync_out) > + tabsyncs[1].handle = syncobj_create(xe, 0); > + > + bind_info("[Binding syncobjs: (in: %u, out: %u)]\n", > + tabsyncs[0].handle, tabsyncs[1].handle); > + > + if (num_binds == 1) { > + if ((bind_ops[0].op & 0xffff) == XE_VM_BIND_OP_MAP) > + xe_vm_bind_async(xe, vm, bind_engine, bind_ops[0].obj, 0, > + bind_ops[0].addr, bind_ops[0].range, > + syncs, num_syncs); > + else > + xe_vm_unbind_async(xe, vm, bind_engine, 0, > + bind_ops[0].addr, bind_ops[0].range, > + syncs, num_syncs); > + } else { > + xe_vm_bind_array(xe, vm, bind_engine, bind_ops, > + num_binds, syncs, num_syncs); > + } > + > + if (!sync_out) { > + igt_assert_eq(syncobj_wait_err(xe, &tabsyncs[1].handle, 1, INT64_MAX, 0), 0); > + syncobj_destroy(xe, tabsyncs[1].handle); > + } > + > + free(bind_ops); > +} > diff --git a/lib/xe/xe_util.h b/lib/xe/xe_util.h > index 9f56fa9898..61511dd97f 100644 > --- a/lib/xe/xe_util.h > +++ b/lib/xe/xe_util.h > @@ -27,4 +27,21 @@ __xe_get_memory_region_set(int xe, uint32_t *mem_regions_type, int num_regions); > > char *xe_memregion_dynamic_subtest_name(int xe, struct igt_collection *set); > > +enum xe_bind_op { > + XE_OBJECT_BIND, > + XE_OBJECT_UNBIND, > +}; > + > +struct xe_object { > + uint32_t handle; > + uint64_t offset; > + uint64_t size; > + enum xe_bind_op bind_op; > + struct igt_list_head link; > +}; > + > +void xe_bind_unbind_async(int fd, uint32_t vm, uint32_t bind_engine, > + struct igt_list_head *obj_list, > + uint32_t sync_in, uint32_t sync_out); > + > #endif /* XE_UTIL_H */ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBBB610E3DA for ; Wed, 12 Jul 2023 09:43:49 +0000 (UTC) Date: Wed, 12 Jul 2023 11:43:45 +0200 From: Zbigniew =?utf-8?Q?Kempczy=C5=84ski?= To: Karolina Stolarek Message-ID: <20230712094345.rgmvtef4qf6ieq4c@zkempczy-mobl2> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-14-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Subject: Re: [igt-dev] [PATCH i-g-t v3 13/17] lib/intel_blt: Extend blitter library to support xe driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On Wed, Jul 12, 2023 at 11:22:00AM +0200, Karolina Stolarek wrote: > On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > > Use already written for i915 blitter library in xe development. > > Add appropriate code paths which are unique for those drivers. > > > > Signed-off-by: Zbigniew Kempczyński > > --- > > v3: Extract common helpers for getting mapping and alignment (Karolina) > > --- > > lib/intel_blt.c | 235 ++++++++++++++++++++++++++++++------------------ > > lib/intel_blt.h | 2 +- > > 2 files changed, 150 insertions(+), 87 deletions(-) > > > > diff --git a/lib/intel_blt.c b/lib/intel_blt.c > > index f2f86e4947..5387a60ee3 100644 > > --- a/lib/intel_blt.c > > +++ b/lib/intel_blt.c > > @@ -9,9 +9,13 @@ > > #include > > #include > > #include "drm.h" > > -#include "igt.h" > > #include "i915/gem_create.h" > > +#include "igt.h" > > +#include "igt_syncobj.h" > > #include "intel_blt.h" > > +#include "xe/xe_ioctl.h" > > +#include "xe/xe_query.h" > > +#include "xe/xe_util.h" > > #define BITRANGE(start, end) (end - start + 1) > > #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd)) > > @@ -468,24 +472,40 @@ static int __special_mode(const struct blt_copy_data *blt) > > return SM_NONE; > > } > > -static int __memory_type(uint32_t region) > > +static int __memory_type(int fd, enum intel_driver driver, uint32_t region) > > { > > - igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || > > - IS_SYSTEM_MEMORY_REGION(region), > > - "Invalid region: %x\n", region); > > + if (driver == INTEL_DRIVER_I915) { > > + igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || > > + IS_SYSTEM_MEMORY_REGION(region), > > + "Invalid region: %x\n", region); > > + } else { > > + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, region) || > > + XE_IS_SYSMEM_MEMORY_REGION(fd, region), > > + "Invalid region: %x\n", region); > > + } > > - if (IS_DEVICE_MEMORY_REGION(region)) > > + if (driver == INTEL_DRIVER_I915 && IS_DEVICE_MEMORY_REGION(region)) > > return TM_LOCAL_MEM; > > + else if (driver == INTEL_DRIVER_XE && XE_IS_VRAM_MEMORY_REGION(fd, region)) > > + return TM_LOCAL_MEM; > > + > > return TM_SYSTEM_MEM; > > } > > -static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj) > > +static enum blt_aux_mode __aux_mode(int fd, > > + enum intel_driver driver, > > + const struct blt_copy_object *obj) > > { > > - if (obj->compression == COMPRESSION_ENABLED) { > > + if (driver == INTEL_DRIVER_I915 && obj->compression == COMPRESSION_ENABLED) { > > igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region), > > "XY_BLOCK_COPY_BLT supports compression " > > "on device memory only\n"); > > return AM_AUX_CCS_E; > > + } else if (driver == INTEL_DRIVER_XE && obj->compression == COMPRESSION_ENABLED) { > > + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, obj->region), > > + "XY_BLOCK_COPY_BLT supports compression " > > + "on device memory only\n"); > > + return AM_AUX_CCS_E; > > } > > return AM_AUX_NONE; > > @@ -508,9 +528,9 @@ static void fill_data(struct gen12_block_copy_data *data, > > data->dw00.length = extended_command ? 20 : 10; > > if (__special_mode(blt) == SM_FULL_RESOLVE) > > - data->dw01.dst_aux_mode = __aux_mode(&blt->src); > > + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); > > else > > - data->dw01.dst_aux_mode = __aux_mode(&blt->dst); > > + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->dst); > > data->dw01.dst_pitch = blt->dst.pitch - 1; > > data->dw01.dst_mocs = blt->dst.mocs; > > @@ -531,13 +551,13 @@ static void fill_data(struct gen12_block_copy_data *data, > > data->dw06.dst_x_offset = blt->dst.x_offset; > > data->dw06.dst_y_offset = blt->dst.y_offset; > > - data->dw06.dst_target_memory = __memory_type(blt->dst.region); > > + data->dw06.dst_target_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); > > data->dw07.src_x1 = blt->src.x1; > > data->dw07.src_y1 = blt->src.y1; > > data->dw08.src_pitch = blt->src.pitch - 1; > > - data->dw08.src_aux_mode = __aux_mode(&blt->src); > > + data->dw08.src_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); > > data->dw08.src_mocs = blt->src.mocs; > > data->dw08.src_compression = blt->src.compression; > > data->dw08.src_tiling = __block_tiling(blt->src.tiling); > > @@ -550,7 +570,7 @@ static void fill_data(struct gen12_block_copy_data *data, > > data->dw11.src_x_offset = blt->src.x_offset; > > data->dw11.src_y_offset = blt->src.y_offset; > > - data->dw11.src_target_memory = __memory_type(blt->src.region); > > + data->dw11.src_target_memory = __memory_type(blt->fd, blt->driver, blt->src.region); > > } > > static void fill_data_ext(struct gen12_block_copy_data_ext *dext, > > @@ -692,6 +712,24 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data) > > data->dw21.src_array_index); > > } > > +static uint64_t get_default_alignment(int fd, enum intel_driver driver) > > +{ > > + if (driver == INTEL_DRIVER_XE) > > + return xe_get_default_alignment(fd); > > + > > + return gem_detect_safe_alignment(fd); > > +} > > + > > +static void *bo_map(int fd, uint32_t handle, uint64_t size, > > + enum intel_driver driver) > > +{ > > + if (driver == INTEL_DRIVER_XE) > > + return xe_bo_map(fd, handle, size); > > + > > + return gem_mmap__device_coherent(fd, handle, 0, size, > > + PROT_READ | PROT_WRITE); > > +} > > + > > /** > > * blt_copy_init: > > * @fd: drm fd > > @@ -739,7 +777,7 @@ uint64_t emit_blt_block_copy(int fd, > > igt_assert_f(ahnd, "block-copy supports softpin only\n"); > > igt_assert_f(blt, "block-copy requires data to do blit\n"); > > - alignment = gem_detect_safe_alignment(fd); > > + alignment = get_default_alignment(fd, blt->driver); > > src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment) > > + blt->src.plane_offset; > > dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment) > > @@ -748,8 +786,7 @@ uint64_t emit_blt_block_copy(int fd, > > fill_data(&data, blt, src_offset, dst_offset, ext); > > - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, > > - PROT_READ | PROT_WRITE); > > + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); > > igt_assert(bb_pos + sizeof(data) < blt->bb.size); > > memcpy(bb + bb_pos, &data, sizeof(data)); > > @@ -812,29 +849,35 @@ int blt_block_copy(int fd, > > igt_assert_f(ahnd, "block-copy supports softpin only\n"); > > igt_assert_f(blt, "block-copy requires data to do blit\n"); > > + igt_assert_neq(blt->driver, 0); > > - alignment = gem_detect_safe_alignment(fd); > > + alignment = get_default_alignment(fd, blt->driver); > > src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); > > dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); > > bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); > > emit_blt_block_copy(fd, ahnd, blt, ext, 0, true); > > - obj[0].offset = CANONICAL(dst_offset); > > - obj[1].offset = CANONICAL(src_offset); > > - obj[2].offset = CANONICAL(bb_offset); > > - obj[0].handle = blt->dst.handle; > > - obj[1].handle = blt->src.handle; > > - obj[2].handle = blt->bb.handle; > > - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > > - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - execbuf.buffer_count = 3; > > - execbuf.buffers_ptr = to_user_pointer(obj); > > - execbuf.rsvd1 = ctx ? ctx->id : 0; > > - execbuf.flags = e ? e->flags : I915_EXEC_BLT; > > - ret = __gem_execbuf(fd, &execbuf); > > + if (blt->driver == INTEL_DRIVER_XE) { > > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > > + } else { > > + obj[0].offset = CANONICAL(dst_offset); > > + obj[1].offset = CANONICAL(src_offset); > > + obj[2].offset = CANONICAL(bb_offset); > > + obj[0].handle = blt->dst.handle; > > + obj[1].handle = blt->src.handle; > > + obj[2].handle = blt->bb.handle; > > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + execbuf.buffer_count = 3; > > + execbuf.buffers_ptr = to_user_pointer(obj); > > + execbuf.rsvd1 = ctx ? ctx->id : 0; > > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > > + > > + ret = __gem_execbuf(fd, &execbuf); > > + } > > return ret; > > } > > @@ -950,7 +993,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, > > igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); > > igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); > > - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); > > + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); > > data.dw00.client = 0x2; > > data.dw00.opcode = 0x48; > > @@ -973,8 +1016,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, > > data.dw04.dst_address_hi = dst_offset >> 32; > > data.dw04.dst_mocs = surf->dst.mocs; > > - bb = gem_mmap__device_coherent(fd, surf->bb.handle, 0, surf->bb.size, > > - PROT_READ | PROT_WRITE); > > + bb = bo_map(fd, surf->bb.handle, surf->bb.size, surf->driver); > > igt_assert(bb_pos + sizeof(data) < surf->bb.size); > > memcpy(bb + bb_pos, &data, sizeof(data)); > > @@ -1002,7 +1044,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, > > /** > > * blt_ctrl_surf_copy: > > - * @fd: drm fd > > + * @blt: bldrm fd > > Emm, the argument seem to still be fd, and there's no blt. A typo? I'm not sure how this appeared here. Will fix and send in v4. > > Thanks for adding the helpers, the code looks nice and tidy (although I'm > scared of __special_mode and the like, but there's no better way to do it). Yes, I also don't see better way to handle two different drivers here. But I believe conditional is readable and easily understandable. -- Zbigniew > > All the best, > Karolina > > > * @ctx: intel_ctx_t context > > * @e: blitter engine for @ctx > > * @ahnd: allocator handle > > @@ -1026,32 +1068,37 @@ int blt_ctrl_surf_copy(int fd, > > igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); > > igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); > > + igt_assert_neq(surf->driver, 0); > > - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); > > + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); > > src_offset = get_offset(ahnd, surf->src.handle, surf->src.size, alignment); > > dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size, alignment); > > bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size, alignment); > > emit_blt_ctrl_surf_copy(fd, ahnd, surf, 0, true); > > - obj[0].offset = CANONICAL(dst_offset); > > - obj[1].offset = CANONICAL(src_offset); > > - obj[2].offset = CANONICAL(bb_offset); > > - obj[0].handle = surf->dst.handle; > > - obj[1].handle = surf->src.handle; > > - obj[2].handle = surf->bb.handle; > > - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > > - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - execbuf.buffer_count = 3; > > - execbuf.buffers_ptr = to_user_pointer(obj); > > - execbuf.flags = e ? e->flags : I915_EXEC_BLT; > > - execbuf.rsvd1 = ctx ? ctx->id : 0; > > - gem_execbuf(fd, &execbuf); > > - put_offset(ahnd, surf->dst.handle); > > - put_offset(ahnd, surf->src.handle); > > - put_offset(ahnd, surf->bb.handle); > > + if (surf->driver == INTEL_DRIVER_XE) { > > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > > + } else { > > + obj[0].offset = CANONICAL(dst_offset); > > + obj[1].offset = CANONICAL(src_offset); > > + obj[2].offset = CANONICAL(bb_offset); > > + obj[0].handle = surf->dst.handle; > > + obj[1].handle = surf->src.handle; > > + obj[2].handle = surf->bb.handle; > > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + execbuf.buffer_count = 3; > > + execbuf.buffers_ptr = to_user_pointer(obj); > > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > > + execbuf.rsvd1 = ctx ? ctx->id : 0; > > + gem_execbuf(fd, &execbuf); > > + put_offset(ahnd, surf->dst.handle); > > + put_offset(ahnd, surf->src.handle); > > + put_offset(ahnd, surf->bb.handle); > > + } > > return 0; > > } > > @@ -1208,7 +1255,7 @@ uint64_t emit_blt_fast_copy(int fd, > > uint32_t bbe = MI_BATCH_BUFFER_END; > > uint32_t *bb; > > - alignment = gem_detect_safe_alignment(fd); > > + alignment = get_default_alignment(fd, blt->driver); > > data.dw00.client = 0x2; > > data.dw00.opcode = 0x42; > > @@ -1218,8 +1265,8 @@ uint64_t emit_blt_fast_copy(int fd, > > data.dw01.dst_pitch = blt->dst.pitch; > > data.dw01.color_depth = __fast_color_depth(blt->color_depth); > > - data.dw01.dst_memory = __memory_type(blt->dst.region); > > - data.dw01.src_memory = __memory_type(blt->src.region); > > + data.dw01.dst_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); > > + data.dw01.src_memory = __memory_type(blt->fd, blt->driver, blt->src.region); > > data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0; > > data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0; > > @@ -1246,8 +1293,7 @@ uint64_t emit_blt_fast_copy(int fd, > > data.dw08.src_address_lo = src_offset; > > data.dw09.src_address_hi = src_offset >> 32; > > - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, > > - PROT_READ | PROT_WRITE); > > + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); > > igt_assert(bb_pos + sizeof(data) < blt->bb.size); > > memcpy(bb + bb_pos, &data, sizeof(data)); > > @@ -1297,32 +1343,39 @@ int blt_fast_copy(int fd, > > uint64_t dst_offset, src_offset, bb_offset, alignment; > > int ret; > > - alignment = gem_detect_safe_alignment(fd); > > + igt_assert_f(ahnd, "fast-copy supports softpin only\n"); > > + igt_assert_f(blt, "fast-copy requires data to do fast-copy blit\n"); > > + igt_assert_neq(blt->driver, 0); > > + alignment = get_default_alignment(fd, blt->driver); > > src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); > > dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); > > bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); > > emit_blt_fast_copy(fd, ahnd, blt, 0, true); > > - obj[0].offset = CANONICAL(dst_offset); > > - obj[1].offset = CANONICAL(src_offset); > > - obj[2].offset = CANONICAL(bb_offset); > > - obj[0].handle = blt->dst.handle; > > - obj[1].handle = blt->src.handle; > > - obj[2].handle = blt->bb.handle; > > - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > > - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > - execbuf.buffer_count = 3; > > - execbuf.buffers_ptr = to_user_pointer(obj); > > - execbuf.rsvd1 = ctx ? ctx->id : 0; > > - execbuf.flags = e ? e->flags : I915_EXEC_BLT; > > - ret = __gem_execbuf(fd, &execbuf); > > - put_offset(ahnd, blt->dst.handle); > > - put_offset(ahnd, blt->src.handle); > > - put_offset(ahnd, blt->bb.handle); > > + if (blt->driver == INTEL_DRIVER_XE) { > > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > > + } else { > > + obj[0].offset = CANONICAL(dst_offset); > > + obj[1].offset = CANONICAL(src_offset); > > + obj[2].offset = CANONICAL(bb_offset); > > + obj[0].handle = blt->dst.handle; > > + obj[1].handle = blt->src.handle; > > + obj[2].handle = blt->bb.handle; > > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > > + execbuf.buffer_count = 3; > > + execbuf.buffers_ptr = to_user_pointer(obj); > > + execbuf.rsvd1 = ctx ? ctx->id : 0; > > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > > + ret = __gem_execbuf(fd, &execbuf); > > + put_offset(ahnd, blt->dst.handle); > > + put_offset(ahnd, blt->src.handle); > > + put_offset(ahnd, blt->bb.handle); > > + } > > return ret; > > } > > @@ -1366,16 +1419,21 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region, > > obj = calloc(1, sizeof(*obj)); > > obj->size = size; > > - igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, > > - &size, region) == 0); > > + > > + if (blt->driver == INTEL_DRIVER_XE) { > > + size = ALIGN(size, xe_get_default_alignment(blt->fd)); > > + handle = xe_bo_create_flags(blt->fd, 0, size, region); > > + } else { > > + igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, > > + &size, region) == 0); > > + } > > blt_set_object(obj, handle, size, region, mocs, tiling, > > compression, compression_type); > > blt_set_geom(obj, stride, 0, 0, width, height, 0, 0); > > if (create_mapping) > > - obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size, > > - PROT_READ | PROT_WRITE); > > + obj->ptr = bo_map(blt->fd, handle, size, blt->driver); > > return obj; > > } > > @@ -1518,14 +1576,19 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid, > > int format; > > int stride = obj->tiling ? obj->pitch * 4 : obj->pitch; > > char filename[FILENAME_MAX]; > > + bool is_xe = is_xe_device(fd); > > snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png", > > run_id, fileid, blt_tiling_name(obj->tiling), width, height, > > obj->compression ? "compressed" : "uncompressed"); > > - if (!map) > > - map = gem_mmap__device_coherent(fd, obj->handle, 0, > > - obj->size, PROT_READ); > > + if (!map) { > > + if (is_xe) > > + map = xe_bo_map(fd, obj->handle, obj->size); > > + else > > + map = gem_mmap__device_coherent(fd, obj->handle, 0, > > + obj->size, PROT_READ); > > + } > > format = CAIRO_FORMAT_RGB24; > > surface = cairo_image_surface_create_for_data(map, > > format, width, height, > > diff --git a/lib/intel_blt.h b/lib/intel_blt.h > > index 7516ce8ac7..944e2b4ae7 100644 > > --- a/lib/intel_blt.h > > +++ b/lib/intel_blt.h > > @@ -8,7 +8,7 @@ > > /** > > * SECTION:intel_blt > > - * @short_description: i915 blitter library > > + * @short_description: i915/xe blitter library > > * @title: Blitter library > > * @include: intel_blt.h > > * From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29B0210E0B9 for ; Wed, 12 Jul 2023 08:14:20 +0000 (UTC) Date: Wed, 12 Jul 2023 10:14:15 +0200 From: Zbigniew =?utf-8?Q?Kempczy=C5=84ski?= To: igt-dev@lists.freedesktop.org Message-ID: <20230712081415.doigqvklqmi26i4x@zkempczy-mobl2> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <168908713268.18666.15567798926028643785@emeril.freedesktop.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <168908713268.18666.15567798926028643785@emeril.freedesktop.org> Subject: Re: [igt-dev] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRXh0ZW5k?= =?utf-8?q?_intel=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: SaiX Nandan Yedireswarapu Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On Tue, Jul 11, 2023 at 02:52:12PM +0000, Patchwork wrote: > Patch Details > > Series: Extend intel_blt to work on Xe (rev3) > URL: https://patchwork.freedesktop.org/series/120162/ > State: failure > Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html > > CI Bug Log - changes from CI_DRM_13369_full -> IGTPW_9383_full > > Summary > > FAILURE > > Serious unknown changes coming with IGTPW_9383_full absolutely need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in IGTPW_9383_full, please notify your bug team to allow them > to document this new failure mode, which will reduce false positives in > CI. > > External URL: > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html > > Participating hosts (9 -> 9) > > No changes in participating hosts > > Possible new issues > > Here are the unknown changes that may have been introduced in > IGTPW_9383_full: > > IGT changes > > Possible regressions > > * igt@prime_vgem@fence-wait@ccs0: > > * shard-mtlp: PASS -> DMESG-WARN > * igt@prime_vgem@fence-wait@vecs0: > > * shard-mtlp: PASS -> ABORT > * igt@vgem_basic@sysfs: > > * shard-snb: PASS -> ABORT Unrelated to the change. -- Zbigniew > > Known issues > > Here are the changes found in IGTPW_9383_full that come from known issues: > > IGT changes > > Issues hit > > * igt@api_intel_bb@crc32: > > * shard-tglu: NOTRUN -> SKIP (i915#6230) > * igt@device_reset@unbind-cold-reset-rebind: > > * shard-rkl: NOTRUN -> SKIP (i915#7701) > > * shard-dg2: NOTRUN -> SKIP (i915#7701) > > * igt@drm_fdinfo@busy-hang@bcs0: > > * shard-dg2: NOTRUN -> SKIP (i915#8414) +19 similar issues > * igt@drm_fdinfo@most-busy-idle-check-all@rcs0: > > * shard-rkl: PASS -> FAIL (i915#7742) > * igt@drm_fdinfo@virtual-busy-all: > > * shard-mtlp: NOTRUN -> SKIP (i915#8414) > * igt@gem_bad_reloc@negative-reloc-bltcopy: > > * shard-mtlp: NOTRUN -> SKIP (i915#3281) +5 similar issues > * igt@gem_basic@multigpu-create-close: > > * shard-rkl: NOTRUN -> SKIP (i915#7697) +1 similar issue > * igt@gem_ccs@block-copy-compressed: > > * shard-tglu: NOTRUN -> SKIP (i915#3555 / i915#5325) > * igt@gem_ccs@ctrl-surf-copy-new-ctx: > > * shard-mtlp: NOTRUN -> SKIP (i915#5325) > * igt@gem_close_race@multigpu-basic-process: > > * shard-dg2: NOTRUN -> SKIP (i915#7697) +1 similar issue > * igt@gem_create@create-ext-cpu-access-big: > > * shard-tglu: NOTRUN -> SKIP (i915#6335) > * igt@gem_ctx_exec@basic-nohangcheck: > > * shard-tglu: PASS -> FAIL (i915#6268) > * igt@gem_ctx_param@set-priority-not-supported: > > * shard-dg2: NOTRUN -> SKIP (fdo#109314) > > * shard-rkl: NOTRUN -> SKIP (fdo#109314) > > * igt@gem_ctx_persistence@saturated-hostile@vecs0: > > * shard-mtlp: PASS -> FAIL (i915#7816) +2 similar issues > * igt@gem_eio@in-flight-contexts-1us: > > * shard-mtlp: PASS -> ABORT (i915#8503) > * igt@gem_eio@kms: > > * shard-dg2: PASS -> INCOMPLETE (i915#7892) > * igt@gem_exec_balancer@bonded-true-hang: > > * shard-dg2: NOTRUN -> SKIP (i915#4812) +2 similar issues > * igt@gem_exec_fair@basic-none@bcs0: > > * shard-tglu: NOTRUN -> FAIL (i915#2842) +4 similar issues > * igt@gem_exec_fair@basic-pace@vcs0: > > * shard-glk: PASS -> FAIL (i915#2842) +1 similar issue > * igt@gem_exec_fair@basic-throttle: > > * shard-dg2: NOTRUN -> SKIP (i915#3539) > * igt@gem_exec_fence@submit67: > > * shard-mtlp: NOTRUN -> SKIP (i915#4812) > * igt@gem_exec_params@secure-non-root: > > * shard-tglu: NOTRUN -> SKIP (fdo#112283) > * igt@gem_exec_reloc@basic-write-gtt-active: > > * shard-dg2: NOTRUN -> SKIP (i915#3281) +2 similar issues > > * shard-rkl: NOTRUN -> SKIP (i915#3281) +1 similar issue > > * igt@gem_exec_whisper@basic-forked: > > * shard-mtlp: NOTRUN -> FAIL (i915#6363) > * igt@gem_exec_whisper@basic-forked-all: > > * shard-mtlp: PASS -> FAIL (i915#6363) > * igt@gem_lmem_swapping@heavy-verify-random-ccs: > > * shard-tglu: NOTRUN -> SKIP (i915#4613) +2 similar issues > * igt@gem_lmem_swapping@parallel-multi: > > * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#4613) > * igt@gem_lmem_swapping@parallel-random: > > * shard-mtlp: NOTRUN -> SKIP (i915#4613) > * igt@gem_lmem_swapping@smem-oom@lmem0: > > * shard-dg2: PASS -> TIMEOUT (i915#5493) > * igt@gem_media_vme: > > * shard-tglu: NOTRUN -> SKIP (i915#284) > * igt@gem_mmap_wc@write: > > * shard-mtlp: NOTRUN -> SKIP (i915#4083) +1 similar issue > > * shard-dg2: NOTRUN -> SKIP (i915#4083) +3 similar issues > > * igt@gem_partial_pwrite_pread@reads: > > * shard-mtlp: NOTRUN -> SKIP (i915#3282) +3 similar issues > * igt@gem_partial_pwrite_pread@writes-after-reads: > > * shard-rkl: NOTRUN -> SKIP (i915#3282) +2 similar issues > * igt@gem_pxp@create-regular-buffer: > > * shard-mtlp: NOTRUN -> SKIP (i915#4270) > * igt@gem_pxp@fail-invalid-protected-context: > > * shard-tglu: NOTRUN -> SKIP (i915#4270) +1 similar issue > * igt@gem_readwrite@beyond-eob: > > * shard-dg2: NOTRUN -> SKIP (i915#3282) +3 similar issues > * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs: > > * shard-mtlp: NOTRUN -> SKIP (i915#8428) +3 similar issues > * igt@gem_set_tiling_vs_pwrite: > > * shard-dg2: NOTRUN -> SKIP (i915#4079) > * igt@gem_tiled_fence_blits@basic: > > * shard-dg2: NOTRUN -> SKIP (i915#4077) +3 similar issues > * igt@gem_tiled_pread_basic: > > * shard-mtlp: NOTRUN -> SKIP (i915#4079) > * igt@gem_userptr_blits@coherency-unsync: > > * shard-mtlp: NOTRUN -> SKIP (i915#3297) > * igt@gem_userptr_blits@invalid-mmap-offset-unsync: > > * shard-dg2: NOTRUN -> SKIP (i915#3297) > > * shard-rkl: NOTRUN -> SKIP (i915#3297) > > * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: > > * shard-dg2: NOTRUN -> SKIP (i915#3297 / i915#4880) > * igt@gem_userptr_blits@nohangcheck: > > * shard-mtlp: PASS -> FAIL (i915#7916) > * igt@gen7_exec_parse@load-register-reg: > > * shard-dg2: NOTRUN -> SKIP (fdo#109289) > * igt@gen7_exec_parse@oacontrol-tracking: > > * shard-mtlp: NOTRUN -> SKIP (fdo#109289) > * igt@gen9_exec_parse@bb-large: > > * shard-dg2: NOTRUN -> SKIP (i915#2856) > > * shard-rkl: NOTRUN -> SKIP (i915#2527) > > * igt@i915_hangman@gt-engine-error@vcs0: > > * shard-mtlp: PASS -> FAIL (i915#7069) > * igt@i915_module_load@load: > > * shard-rkl: NOTRUN -> SKIP (i915#6227) > * igt@i915_pm_backlight@bad-brightness: > > * shard-dg2: NOTRUN -> SKIP (i915#5354 / i915#7561) > * igt@i915_pm_dc@dc5-psr: > > * shard-tglu: NOTRUN -> SKIP (i915#658) > * igt@i915_pm_dc@dc9-dpms: > > * shard-apl: PASS -> SKIP (fdo#109271) > * igt@i915_pm_lpsp@screens-disabled: > > * shard-mtlp: NOTRUN -> SKIP (i915#8430) > * igt@i915_pm_rpm@modeset-non-lpsp-stress: > > * shard-dg2: PASS -> SKIP (i915#1397) +1 similar issue > * igt@i915_pm_rpm@pc8-residency: > > * shard-mtlp: NOTRUN -> SKIP (fdo#109293) > * igt@i915_pm_rpm@system-suspend-execbuf: > > * shard-tglu: NOTRUN -> FAIL (i915#7940) > * igt@i915_suspend@basic-s3-without-i915: > > * shard-dg2: PASS -> FAIL (fdo#103375 / i915#6121) +2 similar > issues > > * shard-tglu: NOTRUN -> INCOMPLETE (i915#7443 / i915#8102) > > * igt@i915_suspend@debugfs-reader: > > * shard-apl: PASS -> ABORT (i915#180 / i915#8213) > * igt@i915_suspend@fence-restore-tiled2untiled: > > * shard-snb: NOTRUN -> DMESG-WARN (i915#8841) +4 similar issues > * igt@kms_addfb_basic@addfb25-x-tiled-legacy: > > * shard-mtlp: NOTRUN -> SKIP (i915#4212) > * igt@kms_addfb_basic@basic-y-tiled-legacy: > > * shard-dg2: NOTRUN -> SKIP (i915#4215 / i915#5190) > * igt@kms_async_flips@crc@pipe-a-hdmi-a-3: > > * shard-dg2: NOTRUN -> FAIL (i915#8247) +3 similar issues > * igt@kms_big_fb@4-tiled-16bpp-rotate-90: > > * shard-mtlp: NOTRUN -> SKIP (fdo#111614) > * igt@kms_big_fb@4-tiled-8bpp-rotate-270: > > * shard-dg2: NOTRUN -> SKIP (fdo#111614) +1 similar issue > * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip: > > * shard-mtlp: PASS -> FAIL (i915#3743) > * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip: > > * shard-tglu: NOTRUN -> SKIP (fdo#111615 / i915#5286) > * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: > > * shard-rkl: NOTRUN -> SKIP (i915#5286) +1 similar issue > > * shard-mtlp: PASS -> FAIL (i915#5138) > > * igt@kms_big_fb@x-tiled-32bpp-rotate-90: > > * shard-rkl: NOTRUN -> SKIP (fdo#111614 / i915#3638) > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: > > * shard-mtlp: NOTRUN -> FAIL (i915#3743) > * igt@kms_big_fb@y-tiled-8bpp-rotate-90: > > * shard-tglu: NOTRUN -> SKIP (fdo#111614) > * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: > > * shard-rkl: NOTRUN -> SKIP (fdo#110723) +2 similar issues > * igt@kms_big_fb@yf-tiled-addfb-size-overflow: > > * shard-dg2: NOTRUN -> SKIP (i915#5190) +5 similar issues > > * shard-tglu: NOTRUN -> SKIP (fdo#111615) +1 similar issue > > * shard-mtlp: NOTRUN -> SKIP (i915#6187) > > * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: > > * shard-mtlp: NOTRUN -> SKIP (fdo#111615) +4 similar issues > * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: > > * shard-dg2: NOTRUN -> SKIP (i915#4538 / i915#5190) +3 similar > issues > * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs: > > * shard-mtlp: NOTRUN -> SKIP (i915#3886 / i915#6095) +5 similar > issues > * igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc: > > * shard-rkl: NOTRUN -> SKIP (i915#5354 / i915#6095) +4 similar > issues > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs: > > * shard-dg2: NOTRUN -> SKIP (i915#3689 / i915#5354) +12 similar > issues > * igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc: > > * shard-tglu: NOTRUN -> SKIP (i915#5354 / i915#6095) +8 similar > issues > * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs: > > * shard-rkl: NOTRUN -> SKIP (i915#3886 / i915#5354 / i915#6095) > * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: > > * shard-tglu: NOTRUN -> SKIP (i915#3689 / i915#3886 / i915#5354 / > i915#6095) +2 similar issues > * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs: > > * shard-rkl: NOTRUN -> SKIP (i915#3734 / i915#5354 / i915#6095) +1 > similar issue > * igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs: > > * shard-tglu: NOTRUN -> SKIP (fdo#111615 / i915#3689 / i915#5354 / > i915#6095) +1 similar issue > * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs: > > * shard-dg2: NOTRUN -> SKIP (i915#5354) +18 similar issues > > * shard-rkl: NOTRUN -> SKIP (i915#5354) +8 similar issues > > * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: > > * shard-dg2: NOTRUN -> SKIP (i915#3689 / i915#3886 / i915#5354) +3 > similar issues > * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc: > > * shard-tglu: NOTRUN -> SKIP (i915#3689 / i915#5354 / i915#6095) +9 > similar issues > * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: > > * shard-mtlp: NOTRUN -> SKIP (i915#6095) +16 similar issues > * igt@kms_chamelium_audio@dp-audio: > > * shard-tglu: NOTRUN -> SKIP (i915#7828) +3 similar issues > > * shard-mtlp: NOTRUN -> SKIP (i915#7828) > > * igt@kms_chamelium_color@ctm-0-50: > > * shard-tglu: NOTRUN -> SKIP (fdo#111827) +1 similar issue > * igt@kms_chamelium_color@ctm-0-75: > > * shard-mtlp: NOTRUN -> SKIP (fdo#111827) > * igt@kms_chamelium_color@ctm-blue-to-red: > > * shard-dg2: NOTRUN -> SKIP (fdo#111827) > * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: > > * shard-rkl: NOTRUN -> SKIP (i915#7828) > * igt@kms_chamelium_frames@hdmi-cmp-planar-formats: > > * shard-dg2: NOTRUN -> SKIP (i915#7828) +1 similar issue > * igt@kms_content_protection@legacy: > > * shard-dg2: NOTRUN -> SKIP (i915#7118) +2 similar issues > * igt@kms_content_protection@mei_interface: > > * shard-mtlp: NOTRUN -> SKIP (i915#8063) > * igt@kms_content_protection@uevent: > > * shard-rkl: NOTRUN -> SKIP (i915#7118) > * igt@kms_cursor_crc@cursor-onscreen-512x170: > > * shard-rkl: NOTRUN -> SKIP (fdo#109279 / i915#3359) > * igt@kms_cursor_crc@cursor-onscreen-512x512: > > * shard-tglu: NOTRUN -> SKIP (i915#3359) +1 similar issue > * igt@kms_cursor_crc@cursor-random-32x10: > > * shard-mtlp: NOTRUN -> SKIP (i915#8814) > * igt@kms_cursor_crc@cursor-random-512x512: > > * shard-mtlp: NOTRUN -> SKIP (i915#3359) > * igt@kms_cursor_crc@cursor-sliding-512x512: > > * shard-dg2: NOTRUN -> SKIP (i915#3359) +2 similar issues > > * shard-rkl: NOTRUN -> SKIP (i915#3359) +1 similar issue > > * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: > > * shard-mtlp: NOTRUN -> SKIP (i915#3546) > * igt@kms_cursor_legacy@cursora-vs-flipb-legacy: > > * shard-tglu: NOTRUN -> SKIP (fdo#109274) +3 similar issues > * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: > > * shard-dg2: NOTRUN -> SKIP (fdo#109274 / i915#5354) +1 similar > issue > > * shard-rkl: NOTRUN -> SKIP (fdo#111825) +1 similar issue > > * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: > > * shard-dg2: NOTRUN -> SKIP (fdo#109274 / fdo#111767 / i915#5354) > > * shard-rkl: NOTRUN -> SKIP (fdo#111767 / fdo#111825) > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > > * shard-apl: PASS -> FAIL (i915#2346) > > * shard-glk: PASS -> FAIL (i915#2346) > > * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1: > > * shard-rkl: NOTRUN -> SKIP (i915#3804) > * igt@kms_dp_aux_dev: > > * shard-tglu: NOTRUN -> SKIP (i915#1257) > * igt@kms_dsc@dsc-with-bpc-formats: > > * shard-tglu: NOTRUN -> SKIP (i915#3555 / i915#3840) > * igt@kms_dsc@dsc-with-output-formats: > > * shard-mtlp: NOTRUN -> SKIP (i915#3840) > * igt@kms_fbcon_fbt@psr: > > * shard-dg2: NOTRUN -> SKIP (i915#3469) > > * shard-rkl: NOTRUN -> SKIP (fdo#110189 / i915#3955) > > * igt@kms_flip@2x-blocking-absolute-wf_vblank: > > * shard-tglu: NOTRUN -> SKIP (fdo#109274 / i915#3637) +2 similar > issues > * igt@kms_flip@2x-flip-vs-blocking-wf-vblank: > > * shard-snb: NOTRUN -> SKIP (fdo#109271 / fdo#111767) > * igt@kms_flip@2x-flip-vs-fences-interruptible: > > * shard-mtlp: NOTRUN -> SKIP (i915#8381) > * igt@kms_flip@2x-plain-flip-fb-recreate: > > * shard-apl: NOTRUN -> SKIP (fdo#109271) +24 similar issues > * igt@kms_flip@2x-plain-flip-interruptible: > > * shard-mtlp: NOTRUN -> SKIP (i915#3637) > * igt@kms_flip@2x-wf_vblank-ts-check-interruptible: > > * shard-dg2: NOTRUN -> SKIP (fdo#109274) > * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode: > > * shard-rkl: NOTRUN -> SKIP (i915#2672) > * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: > > * shard-mtlp: NOTRUN -> SKIP (i915#2672) +1 similar issue > * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode: > > * shard-mtlp: NOTRUN -> SKIP (i915#8810) > * igt@kms_force_connector_basic@prune-stale-modes: > > * shard-mtlp: NOTRUN -> SKIP (i915#5274) > > * shard-dg2: NOTRUN -> SKIP (i915#5274) > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: > > * shard-mtlp: NOTRUN -> SKIP (i915#8708) +1 similar issue > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: > > * shard-dg2: PASS -> FAIL (i915#6880) > * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt: > > * shard-rkl: NOTRUN -> SKIP (i915#3023) +4 similar issues > * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc: > > * shard-dg2: NOTRUN -> SKIP (i915#8708) +5 similar issues > > * shard-rkl: NOTRUN -> SKIP (fdo#111825 / i915#1825) +8 similar > issues > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite: > > * shard-tglu: NOTRUN -> SKIP (fdo#109280) +14 similar issues > * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4: > > * shard-tglu: NOTRUN -> SKIP (i915#5439) > * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu: > > * shard-tglu: NOTRUN -> SKIP (fdo#110189) +12 similar issues > * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render: > > * shard-dg2: NOTRUN -> SKIP (i915#3458) +3 similar issues > * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu: > > * shard-mtlp: NOTRUN -> SKIP (i915#1825) +10 similar issues > * igt@kms_hdr@bpc-switch: > > * shard-tglu: NOTRUN -> SKIP (i915#3555 / i915#8228) > * igt@kms_hdr@bpc-switch-suspend: > > * shard-rkl: NOTRUN -> SKIP (i915#3555 / i915#8228) > * igt@kms_hdr@static-toggle: > > * shard-dg2: NOTRUN -> SKIP (i915#3555 / i915#8228) +1 similar > issue > * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c: > > * shard-tglu: NOTRUN -> SKIP (fdo#109289) +1 similar issue > * igt@kms_plane_scaling@intel-max-src-size: > > * shard-dg2: NOTRUN -> SKIP (i915#6953) > * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1: > > * shard-snb: NOTRUN -> SKIP (fdo#109271) +101 similar issues > * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1: > > * shard-tglu: NOTRUN -> SKIP (i915#5176) +15 similar issues > * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2: > > * shard-rkl: NOTRUN -> SKIP (i915#5176) +7 similar issues > * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3: > > * shard-dg2: NOTRUN -> SKIP (i915#5235) +15 similar issues > * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1: > > * shard-mtlp: NOTRUN -> SKIP (i915#5235) +3 similar issues > * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2: > > * shard-rkl: NOTRUN -> SKIP (i915#5235) +3 similar issues > * igt@kms_psr2_sf@cursor-plane-move-continuous-sf: > > * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#658) > * igt@kms_psr2_su@frontbuffer-xrgb8888: > > * shard-dg2: NOTRUN -> SKIP (i915#658) +1 similar issue > > * shard-mtlp: NOTRUN -> SKIP (i915#4348) > > * igt@kms_psr2_su@page_flip-xrgb8888: > > * shard-tglu: NOTRUN -> SKIP (fdo#109642 / fdo#111068 / i915#658) > +1 similar issue > * igt@kms_psr@primary_mmap_cpu: > > * shard-dg2: NOTRUN -> SKIP (i915#1072) +4 similar issues > > * shard-rkl: NOTRUN -> SKIP (i915#1072) +2 similar issues > > * igt@kms_psr@psr2_cursor_blt: > > * shard-mtlp: PASS -> FAIL (i915#8726) > * igt@kms_psr@psr2_cursor_mmap_gtt: > > * shard-mtlp: NOTRUN -> SKIP (i915#4077) +2 similar issues > * igt@kms_rmfb@close-fd@pipe-a-edp-1: > > * shard-mtlp: PASS -> DMESG-WARN (i915#1982) > * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270: > > * shard-mtlp: NOTRUN -> SKIP (i915#4235) > * igt@kms_scaling_modes@scaling-mode-full: > > * shard-tglu: NOTRUN -> SKIP (i915#3555) +2 similar issues > * igt@kms_tiled_display@basic-test-pattern: > > * shard-tglu: NOTRUN -> SKIP (i915#8623) > * igt@kms_tiled_display@basic-test-pattern-with-chamelium: > > * shard-mtlp: NOTRUN -> SKIP (i915#8623) > * igt@kms_vblank@pipe-c-query-forked-busy: > > * shard-rkl: NOTRUN -> SKIP (i915#4070 / i915#6768) > * igt@kms_vblank@pipe-d-wait-idle: > > * shard-rkl: NOTRUN -> SKIP (i915#4070 / i915#533 / i915#6768) > * igt@kms_writeback@writeback-pixel-formats: > > * shard-tglu: NOTRUN -> SKIP (i915#2437) > * igt@perf@oa-exponents@0-rcs0: > > * shard-glk: PASS -> ABORT (i915#5213 / i915#7941) > * igt@perf_pmu@event-wait@rcs0: > > * shard-mtlp: NOTRUN -> SKIP (i915#8807) > * igt@perf_pmu@rc6@other-idle-gt0: > > * shard-dg2: NOTRUN -> SKIP (i915#8516) > > * shard-tglu: NOTRUN -> SKIP (i915#8516) > > * igt@perf_pmu@render-node-busy-idle@ccs0: > > * shard-mtlp: PASS -> FAIL (i915#4349) +7 similar issues > * igt@prime_vgem@basic-gtt: > > * shard-mtlp: NOTRUN -> SKIP (i915#3708 / i915#4077) > * igt@sysfs_heartbeat_interval@nopreempt@bcs0: > > * shard-mtlp: PASS -> FAIL (i915#6015) +1 similar issue > * igt@sysfs_preempt_timeout@timeout@vecs0: > > * shard-mtlp: PASS -> ABORT (i915#8521) > * igt@v3d/v3d_perfmon@create-perfmon-exceed: > > * shard-mtlp: NOTRUN -> SKIP (i915#2575) +5 similar issues > * igt@v3d/v3d_submit_cl@valid-submission: > > * shard-tglu: NOTRUN -> SKIP (fdo#109315 / i915#2575) +4 similar > issues > * igt@v3d/v3d_submit_csd@bad-multisync-in-sync: > > * shard-dg2: NOTRUN -> SKIP (i915#2575) +2 similar issues > > * shard-rkl: NOTRUN -> SKIP (fdo#109315) +2 similar issues > > * igt@vc4/vc4_mmap@mmap-bo: > > * shard-dg2: NOTRUN -> SKIP (i915#7711) +3 similar issues > > * shard-rkl: NOTRUN -> SKIP (i915#7711) +2 similar issues > > * igt@vc4/vc4_perfmon@create-perfmon-exceed: > > * shard-mtlp: NOTRUN -> SKIP (i915#7711) +3 similar issues > * igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged: > > * shard-tglu: NOTRUN -> SKIP (i915#2575) +4 similar issues > * igt@vgem_basic@bad-pad: > > * shard-mtlp: PASS -> DMESG-WARN (i915#2017) > > Possible fixes > > * igt@gem_create@hog-create@smem0: > > * shard-dg2: FAIL (i915#5892 / i915#8758) -> PASS > * igt@gem_eio@hibernate: > > * {shard-dg1}: ABORT (i915#4391 / i915#7975 / i915#8213) -> PASS > * igt@gem_exec_fair@basic-pace-share@rcs0: > > * shard-glk: FAIL (i915#2842) -> PASS > * igt@gem_exec_fair@basic-throttle@rcs0: > > * shard-rkl: FAIL (i915#2842) -> PASS +3 similar issues > * igt@gem_exec_whisper@basic-contexts-forked-all: > > * shard-mtlp: ABORT (i915#8131) -> PASS > * igt@gem_exec_whisper@basic-fds-priority-all: > > * shard-mtlp: FAIL (i915#6363) -> PASS > * igt@gem_lmem_swapping@smem-oom@lmem0: > > * {shard-dg1}: DMESG-WARN (i915#4936 / i915#5493) -> PASS > * igt@i915_hangman@engine-engine-hang@vcs0: > > * shard-mtlp: FAIL (i915#7069) -> PASS > * igt@i915_module_load@reload-with-fault-injection: > > * shard-mtlp: ABORT (i915#8489 / i915#8668) -> PASS > * igt@i915_pm_dc@dc9-dpms: > > * shard-tglu: SKIP (i915#4281) -> PASS > * igt@i915_pm_rc6_residency@rc6-idle@rcs0: > > * {shard-dg1}: FAIL (i915#3591) -> PASS +1 similar issue > * igt@i915_pm_rpm@cursor-dpms: > > * shard-tglu: FAIL (i915#7940) -> PASS +1 similar issue > * igt@i915_pm_rpm@dpms-mode-unset-lpsp: > > * {shard-dg1}: SKIP (i915#1397) -> PASS > * igt@i915_pm_rpm@dpms-non-lpsp: > > * shard-rkl: SKIP (i915#1397) -> PASS +1 similar issue > * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait: > > * shard-dg2: SKIP (i915#1397) -> PASS +2 similar issues > * igt@i915_selftest@live@gt_mocs: > > * shard-mtlp: DMESG-FAIL (i915#7059) -> PASS > * igt@i915_selftest@live@hangcheck: > > * shard-dg2: ABORT (i915#7913) -> PASS > * igt@i915_selftest@live@workarounds: > > * shard-mtlp: DMESG-FAIL (i915#6763) -> PASS > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: > > * shard-mtlp: FAIL (i915#3743) -> PASS > * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: > > * shard-glk: FAIL (i915#72) -> PASS > * igt@kms_cursor_legacy@cursor-vs-flip-toggle: > > * shard-mtlp: FAIL (i915#8248) -> PASS > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: > > * shard-glk: FAIL (i915#2346) -> PASS > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4: > > * {shard-dg1}: FAIL (i915#79) -> PASS > * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: > > * shard-apl: ABORT (i915#180) -> PASS > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: > > * shard-dg2: FAIL (i915#6880) -> PASS +1 similar issue > * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2: > > * shard-rkl: FAIL (i915#8292) -> PASS > * igt@kms_sysfs_edid_timing: > > * shard-dg2: FAIL (IGT#2) -> PASS > * igt@kms_vblank@pipe-a-ts-continuation-suspend: > > * shard-dg2: FAIL (fdo#103375 / i915#6121) -> PASS > * igt@perf_pmu@busy-double-start@ccs0: > > * shard-mtlp: FAIL (i915#4349) -> PASS > * igt@perf_pmu@most-busy-idle-check-all@bcs0: > > * shard-mtlp: FAIL (i915#5234) -> PASS +1 similar issue > * igt@perf_pmu@most-busy-idle-check-all@rcs0: > > * shard-dg2: FAIL (i915#5234) -> PASS > > * {shard-dg1}: FAIL (i915#5234) -> PASS > > * igt@sysfs_timeslice_duration@timeout@vecs0: > > * shard-mtlp: ABORT (i915#8521) -> PASS > > Warnings > > * igt@gem_exec_suspend@basic-s0@smem: > > * shard-snb: DMESG-FAIL (fdo#103375) -> DMESG-WARN (i915#8841) > * igt@i915_pm_rc6_residency@rc6-idle@bcs0: > > * shard-tglu: FAIL (i915#2681 / i915#3591) -> WARN (i915#2681) > * igt@i915_pm_rc6_residency@rc6-idle@rcs0: > > * shard-tglu: WARN (i915#2681) -> FAIL (i915#2681 / i915#3591) > * igt@i915_suspend@basic-s2idle-without-i915: > > * shard-snb: DMESG-WARN (i915#8841) -> ABORT (i915#4528 / > i915#8213) > * igt@kms_content_protection@mei_interface: > > * shard-dg2: SKIP (i915#7118 / i915#7162) -> SKIP (i915#7118) > > * shard-rkl: SKIP (fdo#109300) -> SKIP (i915#7118) > > * shard-tglu: SKIP (fdo#109300) -> SKIP (i915#6944 / i915#7116 / > i915#7118) > > * igt@kms_force_connector_basic@force-load-detect: > > * shard-rkl: SKIP (fdo#109285 / i915#4098) -> SKIP (fdo#109285) > * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem: > > * shard-dg2: CRASH (i915#7331) -> INCOMPLETE (i915#5493) > > {name}: This element is suppressed. This means it is ignored when > computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > Build changes > > * CI: CI-20190529 -> None > * IGT: IGT_7380 -> IGTPW_9383 > * Piglit: piglit_4509 -> None > > CI-20190529: 20190529 > CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ > git://anongit.freedesktop.org/gfx-ci/linux > IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html > IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C6A0610E3C2 for ; Wed, 12 Jul 2023 09:13:53 +0000 (UTC) Message-ID: <01576293-301d-c3c7-29f1-2f23a04fe2ae@intel.com> Date: Wed, 12 Jul 2023 11:13:24 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-11-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-11-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 10/17] lib/intel_allocator: Add intel_allocator_bind() List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > Synchronize allocator state to vm. > > This change allows xe user to execute vm-bind/unbind for allocator > alloc()/free() operations which occurred since last binding/unbinding. > Before doing exec user should call intel_allocator_bind() to ensure > all vma's are in place. > > Signed-off-by: Zbigniew Kempczyński > --- > v2: Rewrite tracking mechanism: previous code uses bind map embedded > in allocator structure. Unfortunately this wasn't good idea > - for xe binding everything was fine, but it regress multiprocess/ > multithreaded allocations. Main reason of this was children > processes couldn't get its reference as this memory was allocated > on allocator thread (separate process). Currently each child > contains its own separate tracking maps for ahnd and for each > ahnd bind map. > v3: - Don't use priv field (we may clean bind_map apriori as failing > asserts and outdated bind_map is not a problem anymore). > - Use only vm on tracking ahnd (Karolina) > - Add braces to avoid checkpatch complaining (Karolina) > - Use igt_assert_f() instead conditional block (Karolina) > --- > lib/igt_core.c | 5 + > lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++- > lib/intel_allocator.h | 3 + > 3 files changed, 265 insertions(+), 2 deletions(-) > > diff --git a/lib/igt_core.c b/lib/igt_core.c > index 2ae2cb6883..041e4b3288 100644 > --- a/lib/igt_core.c > +++ b/lib/igt_core.c > @@ -74,6 +74,7 @@ > #include "igt_sysrq.h" > #include "igt_rc.h" > #include "igt_list.h" > +#include "igt_map.h" > #include "igt_device_scan.h" > #include "igt_thread.h" > #include "runnercomms.h" > @@ -320,6 +321,8 @@ bool test_multi_fork_child; > /* For allocator purposes */ > pid_t child_pid = -1; > __thread pid_t child_tid = -1; > +struct igt_map *ahnd_map; > +pthread_mutex_t ahnd_map_mutex; > > enum { > /* > @@ -2523,6 +2526,8 @@ bool __igt_fork(void) > case 0: > test_child = true; > pthread_mutex_init(&print_mutex, NULL); > + pthread_mutex_init(&ahnd_map_mutex, NULL); > + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); > child_pid = getpid(); > child_tid = -1; > exit_handler_count = 0; > diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c > index cf964ccc41..f0a9b7fb53 100644 > --- a/lib/intel_allocator.c > +++ b/lib/intel_allocator.c > @@ -17,8 +17,8 @@ > #include "intel_allocator.h" > #include "intel_allocator_msgchannel.h" > #include "xe/xe_query.h" > +#include "xe/xe_util.h" > > -//#define ALLOCDBG > #ifdef ALLOCDBG > #define alloc_info igt_info > #define alloc_debug igt_debug > @@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type) > #define alloc_debug(...) {} > #endif > > +#ifdef ALLOCBINDDBG > +#define bind_info igt_info > +#define bind_debug igt_debug > +#else > +#define bind_info(...) {} > +#define bind_debug(...) {} > +#endif > + > /* > * We limit allocator space to avoid hang when batch would be > * pinned in the last page. > @@ -64,6 +72,30 @@ struct handle_entry { > struct allocator *al; > }; > > +/* For tracking alloc()/free() for Xe */ > +struct ahnd_info { > + int fd; > + uint64_t ahnd; > + uint32_t vm; > + enum intel_driver driver; > + struct igt_map *bind_map; > + pthread_mutex_t bind_map_mutex; > +}; > + > +enum allocator_bind_op { > + BOUND, > + TO_BIND, > + TO_UNBIND, > +}; > + > +struct allocator_object { > + uint32_t handle; > + uint64_t offset; > + uint64_t size; > + > + enum allocator_bind_op bind_op; > +}; > + > struct intel_allocator * > intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); > struct intel_allocator * > @@ -122,6 +154,13 @@ static pid_t allocator_pid = -1; > extern pid_t child_pid; > extern __thread pid_t child_tid; > > +/* > + * Track alloc()/free() requires storing in local process which has > + * an access to real drm fd it can work on. > + */ > +extern struct igt_map *ahnd_map; > +extern pthread_mutex_t ahnd_map_mutex; > + > /* > * - for parent process we have child_pid == -1 > * - for child which calls intel_allocator_init() allocator_pid == child_pid > @@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void) > } > } > > +static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm) > +{ > + struct ahnd_info *ainfo; > + > + pthread_mutex_lock(&ahnd_map_mutex); > + ainfo = igt_map_search(ahnd_map, &ahnd); > + if (!ainfo) { > + ainfo = malloc(sizeof(*ainfo)); > + ainfo->fd = fd; > + ainfo->ahnd = ahnd; > + ainfo->vm = vm; > + ainfo->driver = get_intel_driver(fd); > + ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32); > + pthread_mutex_init(&ainfo->bind_map_mutex, NULL); > + bind_debug("[TRACK AHND] pid: %d, tid: %d, create + "ahnd: %llx, vm: %u, driver: %d, ahnd_map: %p, bind_map: %p>\n", > + getpid(), gettid(), ainfo->fd, > + (long long)ainfo->ahnd, ainfo->vm, > + ainfo->driver, ahnd_map, ainfo->bind_map); > + igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo); > + } > + > + pthread_mutex_unlock(&ahnd_map_mutex); > +} > + > +static void untrack_ahnd(uint64_t ahnd) > +{ > + struct ahnd_info *ainfo; > + > + pthread_mutex_lock(&ahnd_map_mutex); > + ainfo = igt_map_search(ahnd_map, &ahnd); > + if (ainfo) { > + bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n", > + getpid(), gettid(), (long long)ahnd); > + igt_map_remove(ahnd_map, &ahnd, map_entry_free_func); > + } > + pthread_mutex_unlock(&ahnd_map_mutex); > +} > + > static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > uint32_t vm, > uint64_t start, uint64_t end, > @@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > igt_assert(resp.open.allocator_handle); > igt_assert(resp.response_type == RESP_OPEN); > > + /* > + * Igts mostly uses ctx as id when opening the allocator (i915 legacy). > + * If ctx is passed let's use it as an vm id, otherwise use vm. > + */ > + track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm); > + > return resp.open.allocator_handle; > } > > @@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle) > igt_assert(handle_request(&req, &resp) == 0); > igt_assert(resp.response_type == RESP_CLOSE); > > + untrack_ahnd(allocator_handle); > + > return resp.close.is_empty; > } > > @@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle, > *endp = resp.address_range.end; > } > > +static bool is_same(struct allocator_object *obj, > + uint32_t handle, uint64_t offset, uint64_t size, > + enum allocator_bind_op bind_op) > +{ > + return obj->handle == handle && obj->offset == offset && obj->size == size && > + (obj->bind_op == bind_op || obj->bind_op == BOUND); > +} > + > +static void track_object(uint64_t allocator_handle, uint32_t handle, > + uint64_t offset, uint64_t size, > + enum allocator_bind_op bind_op) > +{ > + struct ahnd_info *ainfo; > + struct allocator_object *obj; > + > + bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n", > + bind_op == TO_BIND ? "BIND" : "UNBIND", > + getpid(), gettid(), > + (long long)allocator_handle, > + handle, (long long)offset, (long long)size); > + > + if (offset == ALLOC_INVALID_ADDRESS) { > + bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n", > + (long long)offset); > + return; > + } > + > + pthread_mutex_lock(&ahnd_map_mutex); > + ainfo = igt_map_search(ahnd_map, &allocator_handle); > + pthread_mutex_unlock(&ahnd_map_mutex); > + igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n", > + (long long)allocator_handle); > + > + if (ainfo->driver == INTEL_DRIVER_I915) > + return; /* no-op for i915, at least for now */ > + > + pthread_mutex_lock(&ainfo->bind_map_mutex); > + obj = igt_map_search(ainfo->bind_map, &handle); > + if (obj) { > + /* > + * User may call alloc() couple of times, check object is the > + * same. For free() there's simple case, just remove from > + * bind_map. > + */ > + if (bind_op == TO_BIND) { > + igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true); > + } else if (bind_op == TO_UNBIND) { > + if (obj->bind_op == TO_BIND) > + igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func); > + else if (obj->bind_op == BOUND) > + obj->bind_op = bind_op; > + } > + } else { > + /* Ignore to unbind bo which wasn't previously inserted */ > + if (bind_op == TO_UNBIND) > + goto out; > + > + obj = calloc(1, sizeof(*obj)); > + obj->handle = handle; > + obj->offset = offset; > + obj->size = size; > + obj->bind_op = bind_op; > + igt_map_insert(ainfo->bind_map, &obj->handle, obj); > + } > +out: > + pthread_mutex_unlock(&ainfo->bind_map_mutex); > +} > + > /** > * __intel_allocator_alloc: > * @allocator_handle: handle to an allocator > @@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, > igt_assert(handle_request(&req, &resp) == 0); > igt_assert(resp.response_type == RESP_ALLOC); > > + track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND); > + > return resp.alloc.offset; > } > > @@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle) > igt_assert(handle_request(&req, &resp) == 0); > igt_assert(resp.response_type == RESP_FREE); > > + track_object(allocator_handle, handle, 0, 0, TO_UNBIND); > + > return resp.free.freed; > } > > @@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle) > } > } > > +static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out) > +{ > + struct allocator_object *obj; > + struct igt_map_entry *pos; > + struct igt_list_head obj_list; > + struct xe_object *entry, *tmp; > + > + IGT_INIT_LIST_HEAD(&obj_list); > + > + pthread_mutex_lock(&ainfo->bind_map_mutex); > + igt_map_foreach(ainfo->bind_map, pos) { > + obj = pos->data; > + > + if (obj->bind_op == BOUND) > + continue; > + > + bind_info("= [vm: %u] %s => %u %lx %lx\n", > + ainfo->vm, > + obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND", > + obj->handle, obj->offset, > + obj->size); > + > + entry = malloc(sizeof(*entry)); > + entry->handle = obj->handle; > + entry->offset = obj->offset; > + entry->size = obj->size; > + entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND : > + XE_OBJECT_UNBIND; > + igt_list_add(&entry->link, &obj_list); > + > + /* > + * We clean bind_map even before calling bind/unbind > + * as all binding operations asserts in case of error. > + */ > + if (obj->bind_op == TO_BIND) > + obj->bind_op = BOUND; > + else > + igt_map_remove(ainfo->bind_map, &obj->handle, > + map_entry_free_func); I don't quite understand why we can clean up the map even before the actual bind/unbind happens. If an assert fails, it means that vm_(un)bind failed, so the actual operation didn't succeed, and that state change is incorrect. I believe that there's a reason we can do it this way, I just don't understand it. Apart from that one thing, the patch looks good to me. All the best, Karolina > + } > + pthread_mutex_unlock(&ainfo->bind_map_mutex); > + > + xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out); > + > + igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) { > + igt_list_del(&entry->link); > + free(entry); > + } > +} > + > +/** > + * intel_allocator_bind: > + * @allocator_handle: handle to an allocator > + * @sync_in: syncobj (fence-in) > + * @sync_out: syncobj (fence-out) > + * > + * Function binds and unbinds all objects added to the allocator which weren't > + * previously binded/unbinded. > + * > + **/ > +void intel_allocator_bind(uint64_t allocator_handle, > + uint32_t sync_in, uint32_t sync_out) > +{ > + struct ahnd_info *ainfo; > + > + pthread_mutex_lock(&ahnd_map_mutex); > + ainfo = igt_map_search(ahnd_map, &allocator_handle); > + pthread_mutex_unlock(&ahnd_map_mutex); > + igt_assert(ainfo); > + > + /* > + * We collect bind/unbind operations on alloc()/free() to do group > + * operation getting @sync_in as syncobj handle (fence-in). If user > + * passes 0 as @sync_out we bind/unbind synchronously. > + */ > + __xe_op_bind(ainfo, sync_in, sync_out); > +} > + > static int equal_handles(const void *key1, const void *key2) > { > const struct handle_entry *h1 = key1, *h2 = key2; > @@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators) > igt_map_destroy(map, map_entry_free_func); > } > > +static void __free_ahnd_map(void) > +{ > + struct igt_map_entry *pos; > + struct ahnd_info *ainfo; > + > + if (!ahnd_map) > + return; > + > + igt_map_foreach(ahnd_map, pos) { > + ainfo = pos->data; > + igt_map_destroy(ainfo->bind_map, map_entry_free_func); > + } > + > + igt_map_destroy(ahnd_map, map_entry_free_func); > +} > + > /** > * intel_allocator_init: > * > @@ -1400,12 +1652,15 @@ void intel_allocator_init(void) > __free_maps(handles, true); > __free_maps(ctx_map, false); > __free_maps(vm_map, false); > + __free_ahnd_map(); > > atomic_init(&next_handle, 1); > handles = igt_map_create(hash_handles, equal_handles); > ctx_map = igt_map_create(hash_instance, equal_ctx); > vm_map = igt_map_create(hash_instance, equal_vm); > - igt_assert(handles && ctx_map && vm_map); > + pthread_mutex_init(&ahnd_map_mutex, NULL); > + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); > + igt_assert(handles && ctx_map && vm_map && ahnd_map); > > channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE); > } > diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h > index 3ec74f6191..f9ff7f1cc9 100644 > --- a/lib/intel_allocator.h > +++ b/lib/intel_allocator.h > @@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle, > > void intel_allocator_print(uint64_t allocator_handle); > > +void intel_allocator_bind(uint64_t allocator_handle, > + uint32_t sync_in, uint32_t sync_out); > + > #define ALLOC_INVALID_ADDRESS (-1ull) > #define INTEL_ALLOCATOR_NONE 0 > #define INTEL_ALLOCATOR_RELOC 1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0995B10E3C2 for ; Wed, 12 Jul 2023 09:14:56 +0000 (UTC) Message-ID: <5c999e81-3a93-245a-dd7b-f4b51daba3f9@intel.com> Date: Wed, 12 Jul 2023 11:14:41 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-12-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-12-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 11/17] lib/intel_ctx: Add xe context information List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > Most complicated part in adopting i915_blt to intel_blt - which should > handle both drivers - is how to achieve pipelined execution. In term > pipelined execution I mean all gpu workloads are executed without > stalls. > > Comparing to i915 relocations and softpinning xe architecture migrates > binding (this means also unbind operation) responsibility from the > kernel to user via vm_bind ioctl(). To avoid stalls user has to > provide in/out fences (syncobjs) between consecutive bindings/execs. > Of course for many igt tests we don't need pipelined execution, > just synchronous bind, then exec. But exercising the driver should > also cover pipelining to verify it is possible to work without stalls. > > I decided to extend intel_ctx_t with all necessary for xe objects > (vm, engine, syncobjs) to get flexibility in deciding how to bind, > execute and wait for (synchronize) those operations. Context object > along with i915 engine is already passed to blitter library so adding > xe required fields doesn't break i915 but will allow xe path to get > all necessary data to execute. > > Using intel_ctx with xe requires some code patterns caused by usage > of an allocator. For xe the allocator started tracking alloc()/free() > operations to do bind/unbind in one call just before execution. > I've added two helpers in intel_ctx which - intel_ctx_xe_exec() > and intel_ctx_xe_sync(). Depending how intel_ctx was created > (with 0 or real syncobj handles as in/bind/out fences) bind and exec > in intel_ctx_xe_exec() are pipelined but synchronize last operation > (exec). For real syncobjs they are used to join bind + exec calls > but there's no wait for exec (sync-out) completion. This allows > building more cascaded bind + exec operations without stalls. > > To wait for a sync-out fence caller may use intel_ctx_xe_sync() > which is synchronous wait on syncobj. It allows user to reset > fences to prepare for next operation. > > Signed-off-by: Zbigniew Kempczyński Reviewed-by: Karolina Stolarek > --- > v3: drop local __xe_exec() (Karolina) > --- > lib/intel_ctx.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++- > lib/intel_ctx.h | 14 +++++++ > 2 files changed, 111 insertions(+), 1 deletion(-) > > diff --git a/lib/intel_ctx.c b/lib/intel_ctx.c > index ded9c0f1e4..0c1ce6d10b 100644 > --- a/lib/intel_ctx.c > +++ b/lib/intel_ctx.c > @@ -5,9 +5,12 @@ > > #include > > +#include "i915/gem_engine_topology.h" > +#include "igt_syncobj.h" > +#include "intel_allocator.h" > #include "intel_ctx.h" > #include "ioctl_wrappers.h" > -#include "i915/gem_engine_topology.h" > +#include "xe/xe_ioctl.h" > > /** > * SECTION:intel_ctx > @@ -390,3 +393,96 @@ unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine) > { > return intel_ctx_cfg_engine_class(&ctx->cfg, engine); > } > + > +/** > + * intel_ctx_xe: > + * @fd: open i915 drm file descriptor > + * @vm: vm > + * @engine: engine > + * > + * Returns an intel_ctx_t representing the xe context. > + */ > +intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine, > + uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out) > +{ > + intel_ctx_t *ctx; > + > + ctx = calloc(1, sizeof(*ctx)); > + igt_assert(ctx); > + > + ctx->fd = fd; > + ctx->vm = vm; > + ctx->engine = engine; > + ctx->sync_in = sync_in; > + ctx->sync_bind = sync_bind; > + ctx->sync_out = sync_out; > + > + return ctx; > +} > + > +int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset) > +{ > + struct drm_xe_sync syncs[2] = { > + { .flags = DRM_XE_SYNC_SYNCOBJ, }, > + { .flags = DRM_XE_SYNC_SYNCOBJ | DRM_XE_SYNC_SIGNAL, }, > + }; > + struct drm_xe_exec exec = { > + .engine_id = ctx->engine, > + .syncs = (uintptr_t)syncs, > + .num_syncs = 2, > + .address = bb_offset, > + .num_batch_buffer = 1, > + }; > + uint32_t sync_in = ctx->sync_in; > + uint32_t sync_bind = ctx->sync_bind ?: syncobj_create(ctx->fd, 0); > + uint32_t sync_out = ctx->sync_out ?: syncobj_create(ctx->fd, 0); > + int ret; > + > + /* Synchronize allocator state -> vm */ > + intel_allocator_bind(ahnd, sync_in, sync_bind); > + > + /* Pipelined exec */ > + syncs[0].handle = sync_bind; > + syncs[1].handle = sync_out; > + > + ret = __xe_exec(ctx->fd, &exec); > + if (ret) > + goto err; > + > + if (!ctx->sync_bind || !ctx->sync_out) > + syncobj_wait_err(ctx->fd, &sync_out, 1, INT64_MAX, 0); > + > +err: > + if (!ctx->sync_bind) > + syncobj_destroy(ctx->fd, sync_bind); > + > + if (!ctx->sync_out) > + syncobj_destroy(ctx->fd, sync_out); > + > + return ret; > +} > + > +void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset) > +{ > + igt_assert_eq(__intel_ctx_xe_exec(ctx, ahnd, bb_offset), 0); > +} > + > +#define RESET_SYNCOBJ(__fd, __sync) do { \ > + if (__sync) \ > + syncobj_reset((__fd), &(__sync), 1); \ > +} while (0) > + > +int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs) > +{ > + int ret; > + > + ret = syncobj_wait_err(ctx->fd, &ctx->sync_out, 1, INT64_MAX, 0); > + > + if (reset_syncs) { > + RESET_SYNCOBJ(ctx->fd, ctx->sync_in); > + RESET_SYNCOBJ(ctx->fd, ctx->sync_bind); > + RESET_SYNCOBJ(ctx->fd, ctx->sync_out); > + } > + > + return ret; > +} > diff --git a/lib/intel_ctx.h b/lib/intel_ctx.h > index 3cfeaae81e..59d0360ada 100644 > --- a/lib/intel_ctx.h > +++ b/lib/intel_ctx.h > @@ -67,6 +67,14 @@ int intel_ctx_cfg_engine_class(const intel_ctx_cfg_t *cfg, unsigned int engine); > typedef struct intel_ctx { > uint32_t id; > intel_ctx_cfg_t cfg; > + > + /* Xe */ > + int fd; > + uint32_t vm; > + uint32_t engine; > + uint32_t sync_in; > + uint32_t sync_bind; > + uint32_t sync_out; > } intel_ctx_t; > > int __intel_ctx_create(int fd, const intel_ctx_cfg_t *cfg, > @@ -81,4 +89,10 @@ void intel_ctx_destroy(int fd, const intel_ctx_t *ctx); > > unsigned int intel_ctx_engine_class(const intel_ctx_t *ctx, unsigned int engine); > > +intel_ctx_t *intel_ctx_xe(int fd, uint32_t vm, uint32_t engine, > + uint32_t sync_in, uint32_t sync_bind, uint32_t sync_out); > +int __intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset); > +void intel_ctx_xe_exec(const intel_ctx_t *ctx, uint64_t ahnd, uint64_t bb_offset); > +int intel_ctx_xe_sync(intel_ctx_t *ctx, bool reset_syncs); > + > #endif From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D266410E3D4 for ; Wed, 12 Jul 2023 09:22:27 +0000 (UTC) Message-ID: Date: Wed, 12 Jul 2023 11:22:00 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-14-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-14-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 13/17] lib/intel_blt: Extend blitter library to support xe driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > Use already written for i915 blitter library in xe development. > Add appropriate code paths which are unique for those drivers. > > Signed-off-by: Zbigniew Kempczyński > --- > v3: Extract common helpers for getting mapping and alignment (Karolina) > --- > lib/intel_blt.c | 235 ++++++++++++++++++++++++++++++------------------ > lib/intel_blt.h | 2 +- > 2 files changed, 150 insertions(+), 87 deletions(-) > > diff --git a/lib/intel_blt.c b/lib/intel_blt.c > index f2f86e4947..5387a60ee3 100644 > --- a/lib/intel_blt.c > +++ b/lib/intel_blt.c > @@ -9,9 +9,13 @@ > #include > #include > #include "drm.h" > -#include "igt.h" > #include "i915/gem_create.h" > +#include "igt.h" > +#include "igt_syncobj.h" > #include "intel_blt.h" > +#include "xe/xe_ioctl.h" > +#include "xe/xe_query.h" > +#include "xe/xe_util.h" > > #define BITRANGE(start, end) (end - start + 1) > #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd)) > @@ -468,24 +472,40 @@ static int __special_mode(const struct blt_copy_data *blt) > return SM_NONE; > } > > -static int __memory_type(uint32_t region) > +static int __memory_type(int fd, enum intel_driver driver, uint32_t region) > { > - igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || > - IS_SYSTEM_MEMORY_REGION(region), > - "Invalid region: %x\n", region); > + if (driver == INTEL_DRIVER_I915) { > + igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || > + IS_SYSTEM_MEMORY_REGION(region), > + "Invalid region: %x\n", region); > + } else { > + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, region) || > + XE_IS_SYSMEM_MEMORY_REGION(fd, region), > + "Invalid region: %x\n", region); > + } > > - if (IS_DEVICE_MEMORY_REGION(region)) > + if (driver == INTEL_DRIVER_I915 && IS_DEVICE_MEMORY_REGION(region)) > return TM_LOCAL_MEM; > + else if (driver == INTEL_DRIVER_XE && XE_IS_VRAM_MEMORY_REGION(fd, region)) > + return TM_LOCAL_MEM; > + > return TM_SYSTEM_MEM; > } > > -static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj) > +static enum blt_aux_mode __aux_mode(int fd, > + enum intel_driver driver, > + const struct blt_copy_object *obj) > { > - if (obj->compression == COMPRESSION_ENABLED) { > + if (driver == INTEL_DRIVER_I915 && obj->compression == COMPRESSION_ENABLED) { > igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region), > "XY_BLOCK_COPY_BLT supports compression " > "on device memory only\n"); > return AM_AUX_CCS_E; > + } else if (driver == INTEL_DRIVER_XE && obj->compression == COMPRESSION_ENABLED) { > + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, obj->region), > + "XY_BLOCK_COPY_BLT supports compression " > + "on device memory only\n"); > + return AM_AUX_CCS_E; > } > > return AM_AUX_NONE; > @@ -508,9 +528,9 @@ static void fill_data(struct gen12_block_copy_data *data, > data->dw00.length = extended_command ? 20 : 10; > > if (__special_mode(blt) == SM_FULL_RESOLVE) > - data->dw01.dst_aux_mode = __aux_mode(&blt->src); > + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); > else > - data->dw01.dst_aux_mode = __aux_mode(&blt->dst); > + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->dst); > data->dw01.dst_pitch = blt->dst.pitch - 1; > > data->dw01.dst_mocs = blt->dst.mocs; > @@ -531,13 +551,13 @@ static void fill_data(struct gen12_block_copy_data *data, > > data->dw06.dst_x_offset = blt->dst.x_offset; > data->dw06.dst_y_offset = blt->dst.y_offset; > - data->dw06.dst_target_memory = __memory_type(blt->dst.region); > + data->dw06.dst_target_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); > > data->dw07.src_x1 = blt->src.x1; > data->dw07.src_y1 = blt->src.y1; > > data->dw08.src_pitch = blt->src.pitch - 1; > - data->dw08.src_aux_mode = __aux_mode(&blt->src); > + data->dw08.src_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); > data->dw08.src_mocs = blt->src.mocs; > data->dw08.src_compression = blt->src.compression; > data->dw08.src_tiling = __block_tiling(blt->src.tiling); > @@ -550,7 +570,7 @@ static void fill_data(struct gen12_block_copy_data *data, > > data->dw11.src_x_offset = blt->src.x_offset; > data->dw11.src_y_offset = blt->src.y_offset; > - data->dw11.src_target_memory = __memory_type(blt->src.region); > + data->dw11.src_target_memory = __memory_type(blt->fd, blt->driver, blt->src.region); > } > > static void fill_data_ext(struct gen12_block_copy_data_ext *dext, > @@ -692,6 +712,24 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data) > data->dw21.src_array_index); > } > > +static uint64_t get_default_alignment(int fd, enum intel_driver driver) > +{ > + if (driver == INTEL_DRIVER_XE) > + return xe_get_default_alignment(fd); > + > + return gem_detect_safe_alignment(fd); > +} > + > +static void *bo_map(int fd, uint32_t handle, uint64_t size, > + enum intel_driver driver) > +{ > + if (driver == INTEL_DRIVER_XE) > + return xe_bo_map(fd, handle, size); > + > + return gem_mmap__device_coherent(fd, handle, 0, size, > + PROT_READ | PROT_WRITE); > +} > + > /** > * blt_copy_init: > * @fd: drm fd > @@ -739,7 +777,7 @@ uint64_t emit_blt_block_copy(int fd, > igt_assert_f(ahnd, "block-copy supports softpin only\n"); > igt_assert_f(blt, "block-copy requires data to do blit\n"); > > - alignment = gem_detect_safe_alignment(fd); > + alignment = get_default_alignment(fd, blt->driver); > src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment) > + blt->src.plane_offset; > dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment) > @@ -748,8 +786,7 @@ uint64_t emit_blt_block_copy(int fd, > > fill_data(&data, blt, src_offset, dst_offset, ext); > > - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, > - PROT_READ | PROT_WRITE); > + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); > > igt_assert(bb_pos + sizeof(data) < blt->bb.size); > memcpy(bb + bb_pos, &data, sizeof(data)); > @@ -812,29 +849,35 @@ int blt_block_copy(int fd, > > igt_assert_f(ahnd, "block-copy supports softpin only\n"); > igt_assert_f(blt, "block-copy requires data to do blit\n"); > + igt_assert_neq(blt->driver, 0); > > - alignment = gem_detect_safe_alignment(fd); > + alignment = get_default_alignment(fd, blt->driver); > src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); > dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); > bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); > > emit_blt_block_copy(fd, ahnd, blt, ext, 0, true); > > - obj[0].offset = CANONICAL(dst_offset); > - obj[1].offset = CANONICAL(src_offset); > - obj[2].offset = CANONICAL(bb_offset); > - obj[0].handle = blt->dst.handle; > - obj[1].handle = blt->src.handle; > - obj[2].handle = blt->bb.handle; > - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - execbuf.buffer_count = 3; > - execbuf.buffers_ptr = to_user_pointer(obj); > - execbuf.rsvd1 = ctx ? ctx->id : 0; > - execbuf.flags = e ? e->flags : I915_EXEC_BLT; > - ret = __gem_execbuf(fd, &execbuf); > + if (blt->driver == INTEL_DRIVER_XE) { > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > + } else { > + obj[0].offset = CANONICAL(dst_offset); > + obj[1].offset = CANONICAL(src_offset); > + obj[2].offset = CANONICAL(bb_offset); > + obj[0].handle = blt->dst.handle; > + obj[1].handle = blt->src.handle; > + obj[2].handle = blt->bb.handle; > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + execbuf.buffer_count = 3; > + execbuf.buffers_ptr = to_user_pointer(obj); > + execbuf.rsvd1 = ctx ? ctx->id : 0; > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > + > + ret = __gem_execbuf(fd, &execbuf); > + } > > return ret; > } > @@ -950,7 +993,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, > igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); > igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); > > - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); > + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); > > data.dw00.client = 0x2; > data.dw00.opcode = 0x48; > @@ -973,8 +1016,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, > data.dw04.dst_address_hi = dst_offset >> 32; > data.dw04.dst_mocs = surf->dst.mocs; > > - bb = gem_mmap__device_coherent(fd, surf->bb.handle, 0, surf->bb.size, > - PROT_READ | PROT_WRITE); > + bb = bo_map(fd, surf->bb.handle, surf->bb.size, surf->driver); > > igt_assert(bb_pos + sizeof(data) < surf->bb.size); > memcpy(bb + bb_pos, &data, sizeof(data)); > @@ -1002,7 +1044,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, > > /** > * blt_ctrl_surf_copy: > - * @fd: drm fd > + * @blt: bldrm fd Emm, the argument seem to still be fd, and there's no blt. A typo? Thanks for adding the helpers, the code looks nice and tidy (although I'm scared of __special_mode and the like, but there's no better way to do it). All the best, Karolina > * @ctx: intel_ctx_t context > * @e: blitter engine for @ctx > * @ahnd: allocator handle > @@ -1026,32 +1068,37 @@ int blt_ctrl_surf_copy(int fd, > > igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); > igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); > + igt_assert_neq(surf->driver, 0); > > - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); > + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); > src_offset = get_offset(ahnd, surf->src.handle, surf->src.size, alignment); > dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size, alignment); > bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size, alignment); > > emit_blt_ctrl_surf_copy(fd, ahnd, surf, 0, true); > > - obj[0].offset = CANONICAL(dst_offset); > - obj[1].offset = CANONICAL(src_offset); > - obj[2].offset = CANONICAL(bb_offset); > - obj[0].handle = surf->dst.handle; > - obj[1].handle = surf->src.handle; > - obj[2].handle = surf->bb.handle; > - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - execbuf.buffer_count = 3; > - execbuf.buffers_ptr = to_user_pointer(obj); > - execbuf.flags = e ? e->flags : I915_EXEC_BLT; > - execbuf.rsvd1 = ctx ? ctx->id : 0; > - gem_execbuf(fd, &execbuf); > - put_offset(ahnd, surf->dst.handle); > - put_offset(ahnd, surf->src.handle); > - put_offset(ahnd, surf->bb.handle); > + if (surf->driver == INTEL_DRIVER_XE) { > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > + } else { > + obj[0].offset = CANONICAL(dst_offset); > + obj[1].offset = CANONICAL(src_offset); > + obj[2].offset = CANONICAL(bb_offset); > + obj[0].handle = surf->dst.handle; > + obj[1].handle = surf->src.handle; > + obj[2].handle = surf->bb.handle; > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + execbuf.buffer_count = 3; > + execbuf.buffers_ptr = to_user_pointer(obj); > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > + execbuf.rsvd1 = ctx ? ctx->id : 0; > + gem_execbuf(fd, &execbuf); > + put_offset(ahnd, surf->dst.handle); > + put_offset(ahnd, surf->src.handle); > + put_offset(ahnd, surf->bb.handle); > + } > > return 0; > } > @@ -1208,7 +1255,7 @@ uint64_t emit_blt_fast_copy(int fd, > uint32_t bbe = MI_BATCH_BUFFER_END; > uint32_t *bb; > > - alignment = gem_detect_safe_alignment(fd); > + alignment = get_default_alignment(fd, blt->driver); > > data.dw00.client = 0x2; > data.dw00.opcode = 0x42; > @@ -1218,8 +1265,8 @@ uint64_t emit_blt_fast_copy(int fd, > > data.dw01.dst_pitch = blt->dst.pitch; > data.dw01.color_depth = __fast_color_depth(blt->color_depth); > - data.dw01.dst_memory = __memory_type(blt->dst.region); > - data.dw01.src_memory = __memory_type(blt->src.region); > + data.dw01.dst_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); > + data.dw01.src_memory = __memory_type(blt->fd, blt->driver, blt->src.region); > data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0; > data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0; > > @@ -1246,8 +1293,7 @@ uint64_t emit_blt_fast_copy(int fd, > data.dw08.src_address_lo = src_offset; > data.dw09.src_address_hi = src_offset >> 32; > > - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, > - PROT_READ | PROT_WRITE); > + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); > > igt_assert(bb_pos + sizeof(data) < blt->bb.size); > memcpy(bb + bb_pos, &data, sizeof(data)); > @@ -1297,32 +1343,39 @@ int blt_fast_copy(int fd, > uint64_t dst_offset, src_offset, bb_offset, alignment; > int ret; > > - alignment = gem_detect_safe_alignment(fd); > + igt_assert_f(ahnd, "fast-copy supports softpin only\n"); > + igt_assert_f(blt, "fast-copy requires data to do fast-copy blit\n"); > + igt_assert_neq(blt->driver, 0); > > + alignment = get_default_alignment(fd, blt->driver); > src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); > dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); > bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); > > emit_blt_fast_copy(fd, ahnd, blt, 0, true); > > - obj[0].offset = CANONICAL(dst_offset); > - obj[1].offset = CANONICAL(src_offset); > - obj[2].offset = CANONICAL(bb_offset); > - obj[0].handle = blt->dst.handle; > - obj[1].handle = blt->src.handle; > - obj[2].handle = blt->bb.handle; > - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > - execbuf.buffer_count = 3; > - execbuf.buffers_ptr = to_user_pointer(obj); > - execbuf.rsvd1 = ctx ? ctx->id : 0; > - execbuf.flags = e ? e->flags : I915_EXEC_BLT; > - ret = __gem_execbuf(fd, &execbuf); > - put_offset(ahnd, blt->dst.handle); > - put_offset(ahnd, blt->src.handle); > - put_offset(ahnd, blt->bb.handle); > + if (blt->driver == INTEL_DRIVER_XE) { > + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); > + } else { > + obj[0].offset = CANONICAL(dst_offset); > + obj[1].offset = CANONICAL(src_offset); > + obj[2].offset = CANONICAL(bb_offset); > + obj[0].handle = blt->dst.handle; > + obj[1].handle = blt->src.handle; > + obj[2].handle = blt->bb.handle; > + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | > + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; > + execbuf.buffer_count = 3; > + execbuf.buffers_ptr = to_user_pointer(obj); > + execbuf.rsvd1 = ctx ? ctx->id : 0; > + execbuf.flags = e ? e->flags : I915_EXEC_BLT; > + ret = __gem_execbuf(fd, &execbuf); > + put_offset(ahnd, blt->dst.handle); > + put_offset(ahnd, blt->src.handle); > + put_offset(ahnd, blt->bb.handle); > + } > > return ret; > } > @@ -1366,16 +1419,21 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region, > obj = calloc(1, sizeof(*obj)); > > obj->size = size; > - igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, > - &size, region) == 0); > + > + if (blt->driver == INTEL_DRIVER_XE) { > + size = ALIGN(size, xe_get_default_alignment(blt->fd)); > + handle = xe_bo_create_flags(blt->fd, 0, size, region); > + } else { > + igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, > + &size, region) == 0); > + } > > blt_set_object(obj, handle, size, region, mocs, tiling, > compression, compression_type); > blt_set_geom(obj, stride, 0, 0, width, height, 0, 0); > > if (create_mapping) > - obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size, > - PROT_READ | PROT_WRITE); > + obj->ptr = bo_map(blt->fd, handle, size, blt->driver); > > return obj; > } > @@ -1518,14 +1576,19 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid, > int format; > int stride = obj->tiling ? obj->pitch * 4 : obj->pitch; > char filename[FILENAME_MAX]; > + bool is_xe = is_xe_device(fd); > > snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png", > run_id, fileid, blt_tiling_name(obj->tiling), width, height, > obj->compression ? "compressed" : "uncompressed"); > > - if (!map) > - map = gem_mmap__device_coherent(fd, obj->handle, 0, > - obj->size, PROT_READ); > + if (!map) { > + if (is_xe) > + map = xe_bo_map(fd, obj->handle, obj->size); > + else > + map = gem_mmap__device_coherent(fd, obj->handle, 0, > + obj->size, PROT_READ); > + } > format = CAIRO_FORMAT_RGB24; > surface = cairo_image_surface_create_for_data(map, > format, width, height, > diff --git a/lib/intel_blt.h b/lib/intel_blt.h > index 7516ce8ac7..944e2b4ae7 100644 > --- a/lib/intel_blt.h > +++ b/lib/intel_blt.h > @@ -8,7 +8,7 @@ > > /** > * SECTION:intel_blt > - * @short_description: i915 blitter library > + * @short_description: i915/xe blitter library > * @title: Blitter library > * @include: intel_blt.h > * From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D6A4E10E3D8 for ; Wed, 12 Jul 2023 09:25:07 +0000 (UTC) Message-ID: <340f937c-6a97-966f-0b6c-4231c3159672@intel.com> Date: Wed, 12 Jul 2023 11:24:49 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-18-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-18-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 17/17] tests/gem_ccs: Avoid writing png twice List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > As Karolina noticed we write source png twice what's just takes > time as source surface is not touched. Drop one png write. It was outside of the scope, but you did it! Thanks for writing this patch: Reviewed-by: Karolina Stolarek > > Signed-off-by: Zbigniew Kempczyński > Cc: Karolina Stolarek > --- > tests/i915/gem_ccs.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c > index d9d785ed9b..a1302e0a4d 100644 > --- a/tests/i915/gem_ccs.c > +++ b/tests/i915/gem_ccs.c > @@ -421,7 +421,6 @@ static void block_copy(int i915, > if (mid->compression) > igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0); > > - WRITE_PNG(i915, run_id, "src", &blt.src, width, height); > WRITE_PNG(i915, run_id, "mid", &blt.dst, width, height); > > if (config->surfcopy && pext) { From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id B384510E3DA for ; Wed, 12 Jul 2023 09:34:06 +0000 (UTC) Date: Wed, 12 Jul 2023 11:33:57 +0200 From: Zbigniew =?utf-8?Q?Kempczy=C5=84ski?= To: Karolina Stolarek Message-ID: <20230712093357.atvsv7m4chl6iebn@zkempczy-mobl2> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-11-zbigniew.kempczynski@intel.com> <01576293-301d-c3c7-29f1-2f23a04fe2ae@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <01576293-301d-c3c7-29f1-2f23a04fe2ae@intel.com> Subject: Re: [igt-dev] [PATCH i-g-t v3 10/17] lib/intel_allocator: Add intel_allocator_bind() List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On Wed, Jul 12, 2023 at 11:13:24AM +0200, Karolina Stolarek wrote: > On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > > Synchronize allocator state to vm. > > > > This change allows xe user to execute vm-bind/unbind for allocator > > alloc()/free() operations which occurred since last binding/unbinding. > > Before doing exec user should call intel_allocator_bind() to ensure > > all vma's are in place. > > > > Signed-off-by: Zbigniew Kempczyński > > --- > > v2: Rewrite tracking mechanism: previous code uses bind map embedded > > in allocator structure. Unfortunately this wasn't good idea > > - for xe binding everything was fine, but it regress multiprocess/ > > multithreaded allocations. Main reason of this was children > > processes couldn't get its reference as this memory was allocated > > on allocator thread (separate process). Currently each child > > contains its own separate tracking maps for ahnd and for each > > ahnd bind map. > > v3: - Don't use priv field (we may clean bind_map apriori as failing > > asserts and outdated bind_map is not a problem anymore). > > - Use only vm on tracking ahnd (Karolina) > > - Add braces to avoid checkpatch complaining (Karolina) > > - Use igt_assert_f() instead conditional block (Karolina) > > --- > > lib/igt_core.c | 5 + > > lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++- > > lib/intel_allocator.h | 3 + > > 3 files changed, 265 insertions(+), 2 deletions(-) > > > > diff --git a/lib/igt_core.c b/lib/igt_core.c > > index 2ae2cb6883..041e4b3288 100644 > > --- a/lib/igt_core.c > > +++ b/lib/igt_core.c > > @@ -74,6 +74,7 @@ > > #include "igt_sysrq.h" > > #include "igt_rc.h" > > #include "igt_list.h" > > +#include "igt_map.h" > > #include "igt_device_scan.h" > > #include "igt_thread.h" > > #include "runnercomms.h" > > @@ -320,6 +321,8 @@ bool test_multi_fork_child; > > /* For allocator purposes */ > > pid_t child_pid = -1; > > __thread pid_t child_tid = -1; > > +struct igt_map *ahnd_map; > > +pthread_mutex_t ahnd_map_mutex; > > enum { > > /* > > @@ -2523,6 +2526,8 @@ bool __igt_fork(void) > > case 0: > > test_child = true; > > pthread_mutex_init(&print_mutex, NULL); > > + pthread_mutex_init(&ahnd_map_mutex, NULL); > > + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); > > child_pid = getpid(); > > child_tid = -1; > > exit_handler_count = 0; > > diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c > > index cf964ccc41..f0a9b7fb53 100644 > > --- a/lib/intel_allocator.c > > +++ b/lib/intel_allocator.c > > @@ -17,8 +17,8 @@ > > #include "intel_allocator.h" > > #include "intel_allocator_msgchannel.h" > > #include "xe/xe_query.h" > > +#include "xe/xe_util.h" > > -//#define ALLOCDBG > > #ifdef ALLOCDBG > > #define alloc_info igt_info > > #define alloc_debug igt_debug > > @@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type) > > #define alloc_debug(...) {} > > #endif > > +#ifdef ALLOCBINDDBG > > +#define bind_info igt_info > > +#define bind_debug igt_debug > > +#else > > +#define bind_info(...) {} > > +#define bind_debug(...) {} > > +#endif > > + > > /* > > * We limit allocator space to avoid hang when batch would be > > * pinned in the last page. > > @@ -64,6 +72,30 @@ struct handle_entry { > > struct allocator *al; > > }; > > +/* For tracking alloc()/free() for Xe */ > > +struct ahnd_info { > > + int fd; > > + uint64_t ahnd; > > + uint32_t vm; > > + enum intel_driver driver; > > + struct igt_map *bind_map; > > + pthread_mutex_t bind_map_mutex; > > +}; > > + > > +enum allocator_bind_op { > > + BOUND, > > + TO_BIND, > > + TO_UNBIND, > > +}; > > + > > +struct allocator_object { > > + uint32_t handle; > > + uint64_t offset; > > + uint64_t size; > > + > > + enum allocator_bind_op bind_op; > > +}; > > + > > struct intel_allocator * > > intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); > > struct intel_allocator * > > @@ -122,6 +154,13 @@ static pid_t allocator_pid = -1; > > extern pid_t child_pid; > > extern __thread pid_t child_tid; > > +/* > > + * Track alloc()/free() requires storing in local process which has > > + * an access to real drm fd it can work on. > > + */ > > +extern struct igt_map *ahnd_map; > > +extern pthread_mutex_t ahnd_map_mutex; > > + > > /* > > * - for parent process we have child_pid == -1 > > * - for child which calls intel_allocator_init() allocator_pid == child_pid > > @@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void) > > } > > } > > +static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm) > > +{ > > + struct ahnd_info *ainfo; > > + > > + pthread_mutex_lock(&ahnd_map_mutex); > > + ainfo = igt_map_search(ahnd_map, &ahnd); > > + if (!ainfo) { > > + ainfo = malloc(sizeof(*ainfo)); > > + ainfo->fd = fd; > > + ainfo->ahnd = ahnd; > > + ainfo->vm = vm; > > + ainfo->driver = get_intel_driver(fd); > > + ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32); > > + pthread_mutex_init(&ainfo->bind_map_mutex, NULL); > > + bind_debug("[TRACK AHND] pid: %d, tid: %d, create > + "ahnd: %llx, vm: %u, driver: %d, ahnd_map: %p, bind_map: %p>\n", > > + getpid(), gettid(), ainfo->fd, > > + (long long)ainfo->ahnd, ainfo->vm, > > + ainfo->driver, ahnd_map, ainfo->bind_map); > > + igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo); > > + } > > + > > + pthread_mutex_unlock(&ahnd_map_mutex); > > +} > > + > > +static void untrack_ahnd(uint64_t ahnd) > > +{ > > + struct ahnd_info *ainfo; > > + > > + pthread_mutex_lock(&ahnd_map_mutex); > > + ainfo = igt_map_search(ahnd_map, &ahnd); > > + if (ainfo) { > > + bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n", > > + getpid(), gettid(), (long long)ahnd); > > + igt_map_remove(ahnd_map, &ahnd, map_entry_free_func); > > + } > > + pthread_mutex_unlock(&ahnd_map_mutex); > > +} > > + > > static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > > uint32_t vm, > > uint64_t start, uint64_t end, > > @@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > > igt_assert(resp.open.allocator_handle); > > igt_assert(resp.response_type == RESP_OPEN); > > + /* > > + * Igts mostly uses ctx as id when opening the allocator (i915 legacy). > > + * If ctx is passed let's use it as an vm id, otherwise use vm. > > + */ > > + track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm); > > + > > return resp.open.allocator_handle; > > } > > @@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle) > > igt_assert(handle_request(&req, &resp) == 0); > > igt_assert(resp.response_type == RESP_CLOSE); > > + untrack_ahnd(allocator_handle); > > + > > return resp.close.is_empty; > > } > > @@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle, > > *endp = resp.address_range.end; > > } > > +static bool is_same(struct allocator_object *obj, > > + uint32_t handle, uint64_t offset, uint64_t size, > > + enum allocator_bind_op bind_op) > > +{ > > + return obj->handle == handle && obj->offset == offset && obj->size == size && > > + (obj->bind_op == bind_op || obj->bind_op == BOUND); > > +} > > + > > +static void track_object(uint64_t allocator_handle, uint32_t handle, > > + uint64_t offset, uint64_t size, > > + enum allocator_bind_op bind_op) > > +{ > > + struct ahnd_info *ainfo; > > + struct allocator_object *obj; > > + > > + bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n", > > + bind_op == TO_BIND ? "BIND" : "UNBIND", > > + getpid(), gettid(), > > + (long long)allocator_handle, > > + handle, (long long)offset, (long long)size); > > + > > + if (offset == ALLOC_INVALID_ADDRESS) { > > + bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n", > > + (long long)offset); > > + return; > > + } > > + > > + pthread_mutex_lock(&ahnd_map_mutex); > > + ainfo = igt_map_search(ahnd_map, &allocator_handle); > > + pthread_mutex_unlock(&ahnd_map_mutex); > > + igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n", > > + (long long)allocator_handle); > > + > > + if (ainfo->driver == INTEL_DRIVER_I915) > > + return; /* no-op for i915, at least for now */ > > + > > + pthread_mutex_lock(&ainfo->bind_map_mutex); > > + obj = igt_map_search(ainfo->bind_map, &handle); > > + if (obj) { > > + /* > > + * User may call alloc() couple of times, check object is the > > + * same. For free() there's simple case, just remove from > > + * bind_map. > > + */ > > + if (bind_op == TO_BIND) { > > + igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true); > > + } else if (bind_op == TO_UNBIND) { > > + if (obj->bind_op == TO_BIND) > > + igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func); > > + else if (obj->bind_op == BOUND) > > + obj->bind_op = bind_op; > > + } > > + } else { > > + /* Ignore to unbind bo which wasn't previously inserted */ > > + if (bind_op == TO_UNBIND) > > + goto out; > > + > > + obj = calloc(1, sizeof(*obj)); > > + obj->handle = handle; > > + obj->offset = offset; > > + obj->size = size; > > + obj->bind_op = bind_op; > > + igt_map_insert(ainfo->bind_map, &obj->handle, obj); > > + } > > +out: > > + pthread_mutex_unlock(&ainfo->bind_map_mutex); > > +} > > + > > /** > > * __intel_allocator_alloc: > > * @allocator_handle: handle to an allocator > > @@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, > > igt_assert(handle_request(&req, &resp) == 0); > > igt_assert(resp.response_type == RESP_ALLOC); > > + track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND); > > + > > return resp.alloc.offset; > > } > > @@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle) > > igt_assert(handle_request(&req, &resp) == 0); > > igt_assert(resp.response_type == RESP_FREE); > > + track_object(allocator_handle, handle, 0, 0, TO_UNBIND); > > + > > return resp.free.freed; > > } > > @@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle) > > } > > } > > +static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out) > > +{ > > + struct allocator_object *obj; > > + struct igt_map_entry *pos; > > + struct igt_list_head obj_list; > > + struct xe_object *entry, *tmp; > > + > > + IGT_INIT_LIST_HEAD(&obj_list); > > + > > + pthread_mutex_lock(&ainfo->bind_map_mutex); > > + igt_map_foreach(ainfo->bind_map, pos) { > > + obj = pos->data; > > + > > + if (obj->bind_op == BOUND) > > + continue; > > + > > + bind_info("= [vm: %u] %s => %u %lx %lx\n", > > + ainfo->vm, > > + obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND", > > + obj->handle, obj->offset, > > + obj->size); > > + > > + entry = malloc(sizeof(*entry)); > > + entry->handle = obj->handle; > > + entry->offset = obj->offset; > > + entry->size = obj->size; > > + entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND : > > + XE_OBJECT_UNBIND; > > + igt_list_add(&entry->link, &obj_list); > > + > > + /* > > + * We clean bind_map even before calling bind/unbind > > + * as all binding operations asserts in case of error. > > + */ > > + if (obj->bind_op == TO_BIND) > > + obj->bind_op = BOUND; > > + else > > + igt_map_remove(ainfo->bind_map, &obj->handle, > > + map_entry_free_func); > > I don't quite understand why we can clean up the map even before the actual > bind/unbind happens. If an assert fails, it means that vm_(un)bind failed, > so the actual operation didn't succeed, and that state change is incorrect. > I believe that there's a reason we can do it this way, I just don't > understand it. I allocate separate list of xe_objects which is an argument to xe_bind_unbind_async(). As list is detached (separate) from the bind_map I may apriori do cleanup in the map. If bind/unbind is unsuccessful outdated bind_map is the smallest problem here. On assert path igt_fail() calls intel_allocator_init() which just frees contents on ahnd_map[]->bind_map. In children there's simpler because they just dies. Real problem is we still have dangling vm (no xe_vm_destroy()). So I decided to update the bind_map before calling bind/unbind as on failure doesn't matter what it will contain. -- Zbigniew > > Apart from that one thing, the patch looks good to me. > > All the best, > Karolina > > > + } > > + pthread_mutex_unlock(&ainfo->bind_map_mutex); > > + > > + xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out); > > + > > + igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) { > > + igt_list_del(&entry->link); > > + free(entry); > > + } > > +} > > + > > +/** > > + * intel_allocator_bind: > > + * @allocator_handle: handle to an allocator > > + * @sync_in: syncobj (fence-in) > > + * @sync_out: syncobj (fence-out) > > + * > > + * Function binds and unbinds all objects added to the allocator which weren't > > + * previously binded/unbinded. > > + * > > + **/ > > +void intel_allocator_bind(uint64_t allocator_handle, > > + uint32_t sync_in, uint32_t sync_out) > > +{ > > + struct ahnd_info *ainfo; > > + > > + pthread_mutex_lock(&ahnd_map_mutex); > > + ainfo = igt_map_search(ahnd_map, &allocator_handle); > > + pthread_mutex_unlock(&ahnd_map_mutex); > > + igt_assert(ainfo); > > + > > + /* > > + * We collect bind/unbind operations on alloc()/free() to do group > > + * operation getting @sync_in as syncobj handle (fence-in). If user > > + * passes 0 as @sync_out we bind/unbind synchronously. > > + */ > > + __xe_op_bind(ainfo, sync_in, sync_out); > > +} > > + > > static int equal_handles(const void *key1, const void *key2) > > { > > const struct handle_entry *h1 = key1, *h2 = key2; > > @@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators) > > igt_map_destroy(map, map_entry_free_func); > > } > > +static void __free_ahnd_map(void) > > +{ > > + struct igt_map_entry *pos; > > + struct ahnd_info *ainfo; > > + > > + if (!ahnd_map) > > + return; > > + > > + igt_map_foreach(ahnd_map, pos) { > > + ainfo = pos->data; > > + igt_map_destroy(ainfo->bind_map, map_entry_free_func); > > + } > > + > > + igt_map_destroy(ahnd_map, map_entry_free_func); > > +} > > + > > /** > > * intel_allocator_init: > > * > > @@ -1400,12 +1652,15 @@ void intel_allocator_init(void) > > __free_maps(handles, true); > > __free_maps(ctx_map, false); > > __free_maps(vm_map, false); > > + __free_ahnd_map(); > > atomic_init(&next_handle, 1); > > handles = igt_map_create(hash_handles, equal_handles); > > ctx_map = igt_map_create(hash_instance, equal_ctx); > > vm_map = igt_map_create(hash_instance, equal_vm); > > - igt_assert(handles && ctx_map && vm_map); > > + pthread_mutex_init(&ahnd_map_mutex, NULL); > > + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); > > + igt_assert(handles && ctx_map && vm_map && ahnd_map); > > channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE); > > } > > diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h > > index 3ec74f6191..f9ff7f1cc9 100644 > > --- a/lib/intel_allocator.h > > +++ b/lib/intel_allocator.h > > @@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle, > > void intel_allocator_print(uint64_t allocator_handle); > > +void intel_allocator_bind(uint64_t allocator_handle, > > + uint32_t sync_in, uint32_t sync_out); > > + > > #define ALLOC_INVALID_ADDRESS (-1ull) > > #define INTEL_ALLOCATOR_NONE 0 > > #define INTEL_ALLOCATOR_RELOC 1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D0C210E4BB for ; Wed, 12 Jul 2023 10:03:06 +0000 (UTC) Message-ID: <2f2f3482-d83f-5f78-5092-9800b0617e2a@intel.com> Date: Wed, 12 Jul 2023 12:02:06 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-15-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-15-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 14/17] tests/xe_ccs: Check if flatccs is working with block-copy for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > This is ported to xe copy of i915 gem_ccs test. Ported means all driver > dependent calls - like working on regions, binding and execution were > replaced by xe counterparts. I wondered to add conditionals for xe > in gem_ccs but this would decrease test readability so I dropped > this idea. > > Signed-off-by: Zbigniew Kempczyński > --- > v3: Drop unused macro, use system_memory() instead REGION_SMEM > in xe test (Karolina) > --- > tests/meson.build | 1 + > tests/xe/xe_ccs.c | 757 ++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 758 insertions(+) > create mode 100644 tests/xe/xe_ccs.c > > diff --git a/tests/meson.build b/tests/meson.build > index d56e4c89da..da8653fabc 100644 > --- a/tests/meson.build > +++ b/tests/meson.build > @@ -263,6 +263,7 @@ i915_progs = [ > ] > > xe_progs = [ > + 'xe_ccs', > 'xe_create', > 'xe_compute', > 'xe_dma_buf_sync', > diff --git a/tests/xe/xe_ccs.c b/tests/xe/xe_ccs.c > new file mode 100644 > index 0000000000..ee653790bf > --- /dev/null > +++ b/tests/xe/xe_ccs.c > @@ -0,0 +1,757 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2023 Intel Corporation > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include "drm.h" > +#include "igt.h" > +#include "igt_syncobj.h" > +#include "intel_blt.h" > +#include "intel_mocs.h" > +#include "xe/xe_ioctl.h" > +#include "xe/xe_query.h" > +#include "xe/xe_util.h" > +/** > + * TEST: xe ccs > + * Description: Exercise gen12 blitter with and without flatccs compression on Xe > + * Run type: FULL > + * > + * SUBTEST: block-copy-compressed > + * Description: Check block-copy flatccs compressed blit > + * > + * SUBTEST: block-copy-uncompressed > + * Description: Check block-copy uncompressed blit > + * > + * SUBTEST: block-multicopy-compressed > + * Description: Check block-multicopy flatccs compressed blit > + * > + * SUBTEST: block-multicopy-inplace > + * Description: Check block-multicopy flatccs inplace decompression blit > + * > + * SUBTEST: ctrl-surf-copy > + * Description: Check flatccs data can be copied from/to surface > + * > + * SUBTEST: ctrl-surf-copy-new-ctx > + * Description: Check flatccs data are physically tagged and visible in vm > + * > + * SUBTEST: suspend-resume > + * Description: Check flatccs data persists after suspend / resume (S0) > + */ > + > +IGT_TEST_DESCRIPTION("Exercise gen12 blitter with and without flatccs compression on Xe"); > + > +static struct param { > + int compression_format; > + int tiling; > + bool write_png; > + bool print_bb; > + bool print_surface_info; > + int width; > + int height; > +} param = { > + .compression_format = 0, > + .tiling = -1, > + .write_png = false, > + .print_bb = false, > + .print_surface_info = false, > + .width = 512, > + .height = 512, > +}; > + > +struct test_config { > + bool compression; > + bool inplace; > + bool surfcopy; > + bool new_ctx; > + bool suspend_resume; > +}; > + > +static void set_surf_object(struct blt_ctrl_surf_copy_object *obj, > + uint32_t handle, uint32_t region, uint64_t size, > + uint8_t mocs, enum blt_access_type access_type) > +{ > + obj->handle = handle; > + obj->region = region; > + obj->size = size; > + obj->mocs = mocs; > + obj->access_type = access_type; > +} My comment about extracting helpers was about this function, compare_nxn() and dump_corruption_info(). Do you think it would be possible to share them across xe_css and gem_ccs? Other changes look good to me. All the best, Karolina > + > +#define PRINT_SURFACE_INFO(name, obj) do { \ > + if (param.print_surface_info) \ > + blt_surface_info((name), (obj)); } while (0) > + > +#define WRITE_PNG(fd, id, name, obj, w, h) do { \ > + if (param.write_png) \ > + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0) > + > +static int compare_nxn(const struct blt_copy_object *surf1, > + const struct blt_copy_object *surf2, > + int xsize, int ysize, int bx, int by) > +{ > + int x, y, corrupted; > + uint32_t pos, px1, px2; > + > + corrupted = 0; > + for (y = 0; y < ysize; y++) { > + for (x = 0; x < xsize; x++) { > + pos = bx * xsize + by * ysize * surf1->pitch / 4; > + pos += x + y * surf1->pitch / 4; > + px1 = surf1->ptr[pos]; > + px2 = surf2->ptr[pos]; > + if (px1 != px2) > + corrupted++; > + } > + } > + > + return corrupted; > +} > + > +static void dump_corruption_info(const struct blt_copy_object *surf1, > + const struct blt_copy_object *surf2) > +{ > + const int xsize = 8, ysize = 8; > + int w, h, bx, by, corrupted; > + > + igt_assert(surf1->x1 == surf2->x1 && surf1->x2 == surf2->x2); > + igt_assert(surf1->y1 == surf2->y1 && surf1->y2 == surf2->y2); > + w = surf1->x2; > + h = surf1->y2; > + > + igt_info("dump corruption - width: %d, height: %d, sizex: %x, sizey: %x\n", > + surf1->x2, surf1->y2, xsize, ysize); > + > + for (by = 0; by < h / ysize; by++) { > + for (bx = 0; bx < w / xsize; bx++) { > + corrupted = compare_nxn(surf1, surf2, xsize, ysize, bx, by); > + if (corrupted == 0) > + igt_info("."); > + else > + igt_info("%c", '0' + corrupted); > + } > + igt_info("\n"); > + } > +} > + > +static void surf_copy(int xe, > + intel_ctx_t *ctx, > + uint64_t ahnd, > + const struct blt_copy_object *src, > + const struct blt_copy_object *mid, > + const struct blt_copy_object *dst, > + int run_id, bool suspend_resume) > +{ > + struct blt_copy_data blt = {}; > + struct blt_block_copy_data_ext ext = {}; > + struct blt_ctrl_surf_copy_data surf = {}; > + uint32_t bb1, bb2, ccs, ccs2, *ccsmap, *ccsmap2; > + uint64_t bb_size, ccssize = mid->size / CCS_RATIO; > + uint32_t *ccscopy; > + uint8_t uc_mocs = intel_get_uc_mocs(xe); > + uint32_t sysmem = system_memory(xe); > + int result; > + > + igt_assert(mid->compression); > + ccscopy = (uint32_t *) malloc(ccssize); > + ccs = xe_bo_create_flags(xe, 0, ccssize, sysmem); > + ccs2 = xe_bo_create_flags(xe, 0, ccssize, sysmem); > + > + blt_ctrl_surf_copy_init(xe, &surf); > + surf.print_bb = param.print_bb; > + set_surf_object(&surf.src, mid->handle, mid->region, mid->size, > + uc_mocs, BLT_INDIRECT_ACCESS); > + set_surf_object(&surf.dst, ccs, sysmem, ccssize, uc_mocs, DIRECT_ACCESS); > + bb_size = xe_get_default_alignment(xe); > + bb1 = xe_bo_create_flags(xe, 0, bb_size, sysmem); > + blt_set_batch(&surf.bb, bb1, bb_size, sysmem); > + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); > + intel_ctx_xe_sync(ctx, true); > + > + ccsmap = xe_bo_map(xe, ccs, surf.dst.size); > + memcpy(ccscopy, ccsmap, ccssize); > + > + if (suspend_resume) { > + char *orig, *orig2, *newsum, *newsum2; > + > + orig = g_compute_checksum_for_data(G_CHECKSUM_SHA1, > + (void *)ccsmap, surf.dst.size); > + orig2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1, > + (void *)mid->ptr, mid->size); > + > + igt_system_suspend_autoresume(SUSPEND_STATE_FREEZE, SUSPEND_TEST_NONE); > + > + set_surf_object(&surf.dst, ccs2, system_memory(xe), ccssize, > + 0, DIRECT_ACCESS); > + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); > + intel_ctx_xe_sync(ctx, true); > + > + ccsmap2 = xe_bo_map(xe, ccs2, surf.dst.size); > + newsum = g_compute_checksum_for_data(G_CHECKSUM_SHA1, > + (void *)ccsmap2, surf.dst.size); > + newsum2 = g_compute_checksum_for_data(G_CHECKSUM_SHA1, > + (void *)mid->ptr, mid->size); > + > + munmap(ccsmap2, ccssize); > + igt_assert(!strcmp(orig, newsum)); > + igt_assert(!strcmp(orig2, newsum2)); > + g_free(orig); > + g_free(orig2); > + g_free(newsum); > + g_free(newsum2); > + } > + > + /* corrupt ccs */ > + for (int i = 0; i < surf.dst.size / sizeof(uint32_t); i++) > + ccsmap[i] = i; > + set_surf_object(&surf.src, ccs, sysmem, ccssize, > + uc_mocs, DIRECT_ACCESS); > + set_surf_object(&surf.dst, mid->handle, mid->region, mid->size, > + uc_mocs, INDIRECT_ACCESS); > + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); > + intel_ctx_xe_sync(ctx, true); > + > + blt_copy_init(xe, &blt); > + blt.color_depth = CD_32bit; > + blt.print_bb = param.print_bb; > + blt_set_copy_object(&blt.src, mid); > + blt_set_copy_object(&blt.dst, dst); > + blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D); > + blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D); > + bb2 = xe_bo_create_flags(xe, 0, bb_size, sysmem); > + blt_set_batch(&blt.bb, bb2, bb_size, sysmem); > + blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext); > + intel_ctx_xe_sync(ctx, true); > + WRITE_PNG(xe, run_id, "corrupted", &blt.dst, dst->x2, dst->y2); > + result = memcmp(src->ptr, dst->ptr, src->size); > + igt_assert(result != 0); > + > + /* retrieve back ccs */ > + memcpy(ccsmap, ccscopy, ccssize); > + blt_ctrl_surf_copy(xe, ctx, NULL, ahnd, &surf); > + > + blt_block_copy(xe, ctx, NULL, ahnd, &blt, &ext); > + intel_ctx_xe_sync(ctx, true); > + WRITE_PNG(xe, run_id, "corrected", &blt.dst, dst->x2, dst->y2); > + result = memcmp(src->ptr, dst->ptr, src->size); > + if (result) > + dump_corruption_info(src, dst); > + > + munmap(ccsmap, ccssize); > + gem_close(xe, ccs); > + gem_close(xe, ccs2); > + gem_close(xe, bb1); > + gem_close(xe, bb2); > + > + igt_assert_f(result == 0, > + "Source and destination surfaces are different after " > + "restoring source ccs data\n"); > +} > + > +struct blt_copy3_data { > + int xe; > + struct blt_copy_object src; > + struct blt_copy_object mid; > + struct blt_copy_object dst; > + struct blt_copy_object final; > + struct blt_copy_batch bb; > + enum blt_color_depth color_depth; > + > + /* debug stuff */ > + bool print_bb; > +}; > + > +struct blt_block_copy3_data_ext { > + struct blt_block_copy_object_ext src; > + struct blt_block_copy_object_ext mid; > + struct blt_block_copy_object_ext dst; > + struct blt_block_copy_object_ext final; > +}; > + > +static int blt_block_copy3(int xe, > + const intel_ctx_t *ctx, > + uint64_t ahnd, > + const struct blt_copy3_data *blt3, > + const struct blt_block_copy3_data_ext *ext3) > +{ > + struct blt_copy_data blt0; > + struct blt_block_copy_data_ext ext0; > + uint64_t bb_offset, alignment; > + uint64_t bb_pos = 0; > + int ret; > + > + igt_assert_f(ahnd, "block-copy3 supports softpin only\n"); > + igt_assert_f(blt3, "block-copy3 requires data to do blit\n"); > + > + alignment = xe_get_default_alignment(xe); > + get_offset(ahnd, blt3->src.handle, blt3->src.size, alignment); > + get_offset(ahnd, blt3->mid.handle, blt3->mid.size, alignment); > + get_offset(ahnd, blt3->dst.handle, blt3->dst.size, alignment); > + get_offset(ahnd, blt3->final.handle, blt3->final.size, alignment); > + bb_offset = get_offset(ahnd, blt3->bb.handle, blt3->bb.size, alignment); > + > + /* First blit src -> mid */ > + blt_copy_init(xe, &blt0); > + blt0.src = blt3->src; > + blt0.dst = blt3->mid; > + blt0.bb = blt3->bb; > + blt0.color_depth = blt3->color_depth; > + blt0.print_bb = blt3->print_bb; > + ext0.src = ext3->src; > + ext0.dst = ext3->mid; > + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false); > + > + /* Second blit mid -> dst */ > + blt_copy_init(xe, &blt0); > + blt0.src = blt3->mid; > + blt0.dst = blt3->dst; > + blt0.bb = blt3->bb; > + blt0.color_depth = blt3->color_depth; > + blt0.print_bb = blt3->print_bb; > + ext0.src = ext3->mid; > + ext0.dst = ext3->dst; > + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, false); > + > + /* Third blit dst -> final */ > + blt_copy_init(xe, &blt0); > + blt0.src = blt3->dst; > + blt0.dst = blt3->final; > + blt0.bb = blt3->bb; > + blt0.color_depth = blt3->color_depth; > + blt0.print_bb = blt3->print_bb; > + ext0.src = ext3->dst; > + ext0.dst = ext3->final; > + bb_pos = emit_blt_block_copy(xe, ahnd, &blt0, &ext0, bb_pos, true); > + > + intel_ctx_xe_exec(ctx, ahnd, bb_offset); > + > + return ret; > +} > + > +static void block_copy(int xe, > + intel_ctx_t *ctx, > + uint32_t region1, uint32_t region2, > + enum blt_tiling_type mid_tiling, > + const struct test_config *config) > +{ > + struct blt_copy_data blt = {}; > + struct blt_block_copy_data_ext ext = {}, *pext = &ext; > + struct blt_copy_object *src, *mid, *dst; > + const uint32_t bpp = 32; > + uint64_t bb_size = xe_get_default_alignment(xe); > + uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC); > + uint32_t run_id = mid_tiling; > + uint32_t mid_region = region2, bb; > + uint32_t width = param.width, height = param.height; > + enum blt_compression mid_compression = config->compression; > + int mid_compression_format = param.compression_format; > + enum blt_compression_type comp_type = COMPRESSION_TYPE_3D; > + uint8_t uc_mocs = intel_get_uc_mocs(xe); > + int result; > + > + bb = xe_bo_create_flags(xe, 0, bb_size, region1); > + > + if (!blt_uses_extended_block_copy(xe)) > + pext = NULL; > + > + blt_copy_init(xe, &blt); > + > + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, > + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); > + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs, > + mid_tiling, mid_compression, comp_type, true); > + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, > + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); > + igt_assert(src->size == dst->size); > + PRINT_SURFACE_INFO("src", src); > + PRINT_SURFACE_INFO("mid", mid); > + PRINT_SURFACE_INFO("dst", dst); > + > + blt_surface_fill_rect(xe, src, width, height); > + WRITE_PNG(xe, run_id, "src", src, width, height); > + > + blt.color_depth = CD_32bit; > + blt.print_bb = param.print_bb; > + blt_set_copy_object(&blt.src, src); > + blt_set_copy_object(&blt.dst, mid); > + blt_set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D); > + blt_set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D); > + blt_set_batch(&blt.bb, bb, bb_size, region1); > + blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext); > + intel_ctx_xe_sync(ctx, true); > + > + /* We expect mid != src if there's compression */ > + if (mid->compression) > + igt_assert(memcmp(src->ptr, mid->ptr, src->size) != 0); > + > + WRITE_PNG(xe, run_id, "mid", &blt.dst, width, height); > + > + if (config->surfcopy && pext) { > + struct drm_xe_engine_class_instance inst = { > + .engine_class = DRM_XE_ENGINE_CLASS_COPY, > + }; > + intel_ctx_t *surf_ctx = ctx; > + uint64_t surf_ahnd = ahnd; > + uint32_t vm, engine; > + > + if (config->new_ctx) { > + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > + engine = xe_engine_create(xe, vm, &inst, 0); > + surf_ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0); > + surf_ahnd = intel_allocator_open(xe, surf_ctx->vm, > + INTEL_ALLOCATOR_RELOC); > + } > + surf_copy(xe, surf_ctx, surf_ahnd, src, mid, dst, run_id, > + config->suspend_resume); > + > + if (surf_ctx != ctx) { > + xe_engine_destroy(xe, engine); > + xe_vm_destroy(xe, vm); > + free(surf_ctx); > + put_ahnd(surf_ahnd); > + } > + } > + > + blt_copy_init(xe, &blt); > + blt.color_depth = CD_32bit; > + blt.print_bb = param.print_bb; > + blt_set_copy_object(&blt.src, mid); > + blt_set_copy_object(&blt.dst, dst); > + blt_set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D); > + blt_set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D); > + if (config->inplace) { > + blt_set_object(&blt.dst, mid->handle, dst->size, mid->region, 0, > + T_LINEAR, COMPRESSION_DISABLED, comp_type); > + blt.dst.ptr = mid->ptr; > + } > + > + blt_set_batch(&blt.bb, bb, bb_size, region1); > + blt_block_copy(xe, ctx, NULL, ahnd, &blt, pext); > + intel_ctx_xe_sync(ctx, true); > + > + WRITE_PNG(xe, run_id, "dst", &blt.dst, width, height); > + > + result = memcmp(src->ptr, blt.dst.ptr, src->size); > + > + /* Politely clean vm */ > + put_offset(ahnd, src->handle); > + put_offset(ahnd, mid->handle); > + put_offset(ahnd, dst->handle); > + put_offset(ahnd, bb); > + intel_allocator_bind(ahnd, 0, 0); > + blt_destroy_object(xe, src); > + blt_destroy_object(xe, mid); > + blt_destroy_object(xe, dst); > + gem_close(xe, bb); > + put_ahnd(ahnd); > + > + igt_assert_f(!result, "source and destination surfaces differs!\n"); > +} > + > +static void block_multicopy(int xe, > + intel_ctx_t *ctx, > + uint32_t region1, uint32_t region2, > + enum blt_tiling_type mid_tiling, > + const struct test_config *config) > +{ > + struct blt_copy3_data blt3 = {}; > + struct blt_copy_data blt = {}; > + struct blt_block_copy3_data_ext ext3 = {}, *pext3 = &ext3; > + struct blt_copy_object *src, *mid, *dst, *final; > + const uint32_t bpp = 32; > + uint64_t bb_size = xe_get_default_alignment(xe); > + uint64_t ahnd = intel_allocator_open(xe, ctx->vm, INTEL_ALLOCATOR_RELOC); > + uint32_t run_id = mid_tiling; > + uint32_t mid_region = region2, bb; > + uint32_t width = param.width, height = param.height; > + enum blt_compression mid_compression = config->compression; > + int mid_compression_format = param.compression_format; > + enum blt_compression_type comp_type = COMPRESSION_TYPE_3D; > + uint8_t uc_mocs = intel_get_uc_mocs(xe); > + int result; > + > + bb = xe_bo_create_flags(xe, 0, bb_size, region1); > + > + if (!blt_uses_extended_block_copy(xe)) > + pext3 = NULL; > + > + blt_copy_init(xe, &blt); > + > + src = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, > + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); > + mid = blt_create_object(&blt, mid_region, width, height, bpp, uc_mocs, > + mid_tiling, mid_compression, comp_type, true); > + dst = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, > + mid_tiling, COMPRESSION_DISABLED, comp_type, true); > + final = blt_create_object(&blt, region1, width, height, bpp, uc_mocs, > + T_LINEAR, COMPRESSION_DISABLED, comp_type, true); > + igt_assert(src->size == dst->size); > + PRINT_SURFACE_INFO("src", src); > + PRINT_SURFACE_INFO("mid", mid); > + PRINT_SURFACE_INFO("dst", dst); > + PRINT_SURFACE_INFO("final", final); > + > + blt_surface_fill_rect(xe, src, width, height); > + > + blt3.color_depth = CD_32bit; > + blt3.print_bb = param.print_bb; > + blt_set_copy_object(&blt3.src, src); > + blt_set_copy_object(&blt3.mid, mid); > + blt_set_copy_object(&blt3.dst, dst); > + blt_set_copy_object(&blt3.final, final); > + > + if (config->inplace) { > + blt_set_object(&blt3.dst, mid->handle, dst->size, mid->region, > + mid->mocs, mid_tiling, COMPRESSION_DISABLED, > + comp_type); > + blt3.dst.ptr = mid->ptr; > + } > + > + blt_set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D); > + blt_set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D); > + blt_set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D); > + blt_set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D); > + blt_set_batch(&blt3.bb, bb, bb_size, region1); > + > + blt_block_copy3(xe, ctx, ahnd, &blt3, pext3); > + intel_ctx_xe_sync(ctx, true); > + > + WRITE_PNG(xe, run_id, "src", &blt3.src, width, height); > + if (!config->inplace) > + WRITE_PNG(xe, run_id, "mid", &blt3.mid, width, height); > + WRITE_PNG(xe, run_id, "dst", &blt3.dst, width, height); > + WRITE_PNG(xe, run_id, "final", &blt3.final, width, height); > + > + result = memcmp(src->ptr, blt3.final.ptr, src->size); > + > + put_offset(ahnd, src->handle); > + put_offset(ahnd, mid->handle); > + put_offset(ahnd, dst->handle); > + put_offset(ahnd, final->handle); > + put_offset(ahnd, bb); > + intel_allocator_bind(ahnd, 0, 0); > + blt_destroy_object(xe, src); > + blt_destroy_object(xe, mid); > + blt_destroy_object(xe, dst); > + blt_destroy_object(xe, final); > + gem_close(xe, bb); > + put_ahnd(ahnd); > + > + igt_assert_f(!result, "source and destination surfaces differs!\n"); > +} > + > +enum copy_func { > + BLOCK_COPY, > + BLOCK_MULTICOPY, > +}; > + > +static const struct { > + const char *suffix; > + void (*copyfn)(int fd, > + intel_ctx_t *ctx, > + uint32_t region1, uint32_t region2, > + enum blt_tiling_type btype, > + const struct test_config *config); > +} copyfns[] = { > + [BLOCK_COPY] = { "", block_copy }, > + [BLOCK_MULTICOPY] = { "-multicopy", block_multicopy }, > +}; > + > +static void block_copy_test(int xe, > + const struct test_config *config, > + struct igt_collection *set, > + enum copy_func copy_function) > +{ > + struct drm_xe_engine_class_instance inst = { > + .engine_class = DRM_XE_ENGINE_CLASS_COPY, > + }; > + intel_ctx_t *ctx; > + struct igt_collection *regions; > + uint32_t vm, engine; > + int tiling; > + > + if (config->compression && !blt_block_copy_supports_compression(xe)) > + return; > + > + if (config->inplace && !config->compression) > + return; > + > + for_each_tiling(tiling) { > + if (!blt_block_copy_supports_tiling(xe, tiling) || > + (param.tiling >= 0 && param.tiling != tiling)) > + continue; > + > + for_each_variation_r(regions, 2, set) { > + uint32_t region1, region2; > + char *regtxt; > + > + region1 = igt_collection_get_value(regions, 0); > + region2 = igt_collection_get_value(regions, 1); > + > + /* Compressed surface must be in device memory */ > + if (config->compression && !XE_IS_VRAM_MEMORY_REGION(xe, region2)) > + continue; > + > + regtxt = xe_memregion_dynamic_subtest_name(xe, regions); > + > + igt_dynamic_f("%s-%s-compfmt%d-%s%s", > + blt_tiling_name(tiling), > + config->compression ? > + "compressed" : "uncompressed", > + param.compression_format, regtxt, > + copyfns[copy_function].suffix) { > + uint32_t sync_bind, sync_out; > + > + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > + engine = xe_engine_create(xe, vm, &inst, 0); > + sync_bind = syncobj_create(xe, 0); > + sync_out = syncobj_create(xe, 0); > + ctx = intel_ctx_xe(xe, vm, engine, > + 0, sync_bind, sync_out); > + > + copyfns[copy_function].copyfn(xe, ctx, > + region1, region2, > + tiling, config); > + > + xe_engine_destroy(xe, engine); > + xe_vm_destroy(xe, vm); > + syncobj_destroy(xe, sync_bind); > + syncobj_destroy(xe, sync_out); > + free(ctx); > + } > + > + free(regtxt); > + } > + } > +} > + > +static int opt_handler(int opt, int opt_index, void *data) > +{ > + switch (opt) { > + case 'b': > + param.print_bb = true; > + igt_debug("Print bb: %d\n", param.print_bb); > + break; > + case 'f': > + param.compression_format = atoi(optarg); > + igt_debug("Compression format: %d\n", param.compression_format); > + igt_assert((param.compression_format & ~0x1f) == 0); > + break; > + case 'p': > + param.write_png = true; > + igt_debug("Write png: %d\n", param.write_png); > + break; > + case 's': > + param.print_surface_info = true; > + igt_debug("Print surface info: %d\n", param.print_surface_info); > + break; > + case 't': > + param.tiling = atoi(optarg); > + igt_debug("Tiling: %d\n", param.tiling); > + break; > + case 'W': > + param.width = atoi(optarg); > + igt_debug("Width: %d\n", param.width); > + break; > + case 'H': > + param.height = atoi(optarg); > + igt_debug("Height: %d\n", param.height); > + break; > + default: > + return IGT_OPT_HANDLER_ERROR; > + } > + > + return IGT_OPT_HANDLER_SUCCESS; > +} > + > +const char *help_str = > + " -b\tPrint bb\n" > + " -f\tCompression format (0-31)\n" > + " -p\tWrite PNG\n" > + " -s\tPrint surface info\n" > + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64)\n" > + " -W\tWidth (default 512)\n" > + " -H\tHeight (default 512)" > + ; > + > +igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL) > +{ > + struct igt_collection *set; > + int xe; > + > + igt_fixture { > + xe = drm_open_driver(DRIVER_XE); > + igt_require(blt_has_block_copy(xe)); > + > + xe_device_get(xe); > + > + set = xe_get_memory_region_set(xe, > + XE_MEM_REGION_CLASS_SYSMEM, > + XE_MEM_REGION_CLASS_VRAM); > + } > + > + igt_describe("Check block-copy uncompressed blit"); > + igt_subtest_with_dynamic("block-copy-uncompressed") { > + struct test_config config = {}; > + > + block_copy_test(xe, &config, set, BLOCK_COPY); > + } > + > + igt_describe("Check block-copy flatccs compressed blit"); > + igt_subtest_with_dynamic("block-copy-compressed") { > + struct test_config config = { .compression = true }; > + > + block_copy_test(xe, &config, set, BLOCK_COPY); > + } > + > + igt_describe("Check block-multicopy flatccs compressed blit"); > + igt_subtest_with_dynamic("block-multicopy-compressed") { > + struct test_config config = { .compression = true }; > + > + block_copy_test(xe, &config, set, BLOCK_MULTICOPY); > + } > + > + igt_describe("Check block-multicopy flatccs inplace decompression blit"); > + igt_subtest_with_dynamic("block-multicopy-inplace") { > + struct test_config config = { .compression = true, > + .inplace = true }; > + > + block_copy_test(xe, &config, set, BLOCK_MULTICOPY); > + } > + > + igt_describe("Check flatccs data can be copied from/to surface"); > + igt_subtest_with_dynamic("ctrl-surf-copy") { > + struct test_config config = { .compression = true, > + .surfcopy = true }; > + > + block_copy_test(xe, &config, set, BLOCK_COPY); > + } > + > + igt_describe("Check flatccs data are physically tagged and visible" > + " in different contexts"); > + igt_subtest_with_dynamic("ctrl-surf-copy-new-ctx") { > + struct test_config config = { .compression = true, > + .surfcopy = true, > + .new_ctx = true }; > + > + block_copy_test(xe, &config, set, BLOCK_COPY); > + } > + > + igt_describe("Check flatccs data persists after suspend / resume (S0)"); > + igt_subtest_with_dynamic("suspend-resume") { > + struct test_config config = { .compression = true, > + .surfcopy = true, > + .suspend_resume = true }; > + > + block_copy_test(xe, &config, set, BLOCK_COPY); > + } > + > + igt_fixture { > + xe_device_put(xe); > + close(xe); > + } > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 325DC10E4CC for ; Wed, 12 Jul 2023 10:18:44 +0000 (UTC) Message-ID: <68097bdb-c02e-a669-bd29-8b9d796b9439@intel.com> Date: Wed, 12 Jul 2023 12:18:23 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-16-zbigniew.kempczynski@intel.com> From: Karolina Stolarek In-Reply-To: <20230711112009.122482-16-zbigniew.kempczynski@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 15/17] tests/xe_exercise_blt: Check blitter library fast-copy for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > Port this test to work on xe. Instead of adding conditional code for > xe code which would decrease readability this is new test for xe. > > Signed-off-by: Zbigniew Kempczyński > --- > v3: - Explicitely release offsets and unbind (Karolina) > - Use has-fast-copy instead of copied has-block-copy check (Karolina) > --- > tests/meson.build | 1 + > tests/xe/xe_exercise_blt.c | 377 +++++++++++++++++++++++++++++++++++++ > 2 files changed, 378 insertions(+) > create mode 100644 tests/xe/xe_exercise_blt.c > > diff --git a/tests/meson.build b/tests/meson.build > index da8653fabc..3eddb2fb4e 100644 > --- a/tests/meson.build > +++ b/tests/meson.build > @@ -276,6 +276,7 @@ xe_progs = [ > 'xe_exec_reset', > 'xe_exec_store', > 'xe_exec_threads', > + 'xe_exercise_blt', > 'xe_gpgpu_fill', > 'xe_guc_pc', > 'xe_huc_copy', > diff --git a/tests/xe/xe_exercise_blt.c b/tests/xe/xe_exercise_blt.c > new file mode 100644 > index 0000000000..693e80d0b7 > --- /dev/null > +++ b/tests/xe/xe_exercise_blt.c > @@ -0,0 +1,377 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2023 Intel Corporation > + */ > + > +#include "igt.h" > +#include "drm.h" > +#include "lib/intel_chipset.h" > +#include "intel_blt.h" > +#include "intel_mocs.h" > +#include "xe/xe_ioctl.h" > +#include "xe/xe_query.h" > +#include "xe/xe_util.h" > + > +/** > + * TEST: xe exercise blt > + * Description: Exercise blitter commands on Xe > + * Feature: blitter > + * Run type: FULL > + * Test category: GEM_Legacy > + * > + * SUBTEST: fast-copy > + * Description: > + * Check fast-copy blit > + * blitter > + * > + * SUBTEST: fast-copy-emit > + * Description: > + * Check multiple fast-copy in one batch > + * blitter > + */ > + > +IGT_TEST_DESCRIPTION("Exercise blitter commands on Xe"); > + > +static struct param { > + int tiling; > + bool write_png; > + bool print_bb; > + bool print_surface_info; > + int width; > + int height; > +} param = { > + .tiling = -1, > + .write_png = false, > + .print_bb = false, > + .print_surface_info = false, > + .width = 512, > + .height = 512, > +}; > + > +#define PRINT_SURFACE_INFO(name, obj) do { \ > + if (param.print_surface_info) \ > + blt_surface_info((name), (obj)); } while (0) > + > +#define WRITE_PNG(fd, id, name, obj, w, h) do { \ > + if (param.write_png) \ > + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0) > + > +struct blt_fast_copy_data { > + int xe; > + struct blt_copy_object src; > + struct blt_copy_object mid; > + struct blt_copy_object dst; > + > + struct blt_copy_batch bb; > + enum blt_color_depth color_depth; > + > + /* debug stuff */ > + bool print_bb; > +}; > + > +static int fast_copy_one_bb(int xe, > + const intel_ctx_t *ctx, > + uint64_t ahnd, > + const struct blt_fast_copy_data *blt) > +{ > + struct blt_copy_data blt_tmp; > + uint64_t bb_offset, alignment; > + uint64_t bb_pos = 0; > + int ret = 0; > + > + alignment = xe_get_default_alignment(xe); > + > + get_offset(ahnd, blt->src.handle, blt->src.size, alignment); > + get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment); > + get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); > + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); > + > + /* First blit */ > + blt_copy_init(xe, &blt_tmp); > + blt_tmp.src = blt->src; > + blt_tmp.dst = blt->mid; > + blt_tmp.bb = blt->bb; > + blt_tmp.color_depth = blt->color_depth; > + blt_tmp.print_bb = blt->print_bb; > + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, false); > + > + /* Second blit */ > + blt_copy_init(xe, &blt_tmp); > + blt_tmp.src = blt->mid; > + blt_tmp.dst = blt->dst; > + blt_tmp.bb = blt->bb; > + blt_tmp.color_depth = blt->color_depth; > + blt_tmp.print_bb = blt->print_bb; > + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, true); > + > + intel_ctx_xe_exec(ctx, ahnd, bb_offset); > + > + return ret; > +} > + > +static void fast_copy_emit(int xe, const intel_ctx_t *ctx, > + uint32_t region1, uint32_t region2, > + enum blt_tiling_type mid_tiling) > +{ > + struct blt_copy_data bltinit = {}; > + struct blt_fast_copy_data blt = {}; > + struct blt_copy_object *src, *mid, *dst; > + const uint32_t bpp = 32; > + uint64_t bb_size = xe_get_default_alignment(xe); > + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > + uint32_t bb, width = param.width, height = param.height; > + int result; > + > + bb = xe_bo_create_flags(xe, 0, bb_size, region1); > + > + blt_copy_init(xe, &bltinit); > + src = blt_create_object(&bltinit, region1, width, height, bpp, 0, > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > + mid = blt_create_object(&bltinit, region2, width, height, bpp, 0, > + mid_tiling, COMPRESSION_DISABLED, 0, true); > + dst = blt_create_object(&bltinit, region1, width, height, bpp, 0, > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > + igt_assert(src->size == dst->size); > + > + PRINT_SURFACE_INFO("src", src); > + PRINT_SURFACE_INFO("mid", mid); > + PRINT_SURFACE_INFO("dst", dst); > + > + blt_surface_fill_rect(xe, src, width, height); > + WRITE_PNG(xe, mid_tiling, "src", src, width, height); > + > + memset(&blt, 0, sizeof(blt)); Could we use blt_copy_init() here? Thanks, Karolina > + blt.color_depth = CD_32bit; > + blt.print_bb = param.print_bb; > + blt_set_copy_object(&blt.src, src); > + blt_set_copy_object(&blt.mid, mid); > + blt_set_copy_object(&blt.dst, dst); > + blt_set_batch(&blt.bb, bb, bb_size, region1); > + > + fast_copy_one_bb(xe, ctx, ahnd, &blt); > + > + WRITE_PNG(xe, mid_tiling, "mid", &blt.mid, width, height); > + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height); > + > + result = memcmp(src->ptr, blt.dst.ptr, src->size); > + > + blt_destroy_object(xe, src); > + blt_destroy_object(xe, mid); > + blt_destroy_object(xe, dst); > + gem_close(xe, bb); > + put_ahnd(ahnd); > + > + munmap(&bb, bb_size); > + > + igt_assert_f(!result, "source and destination surfaces differs!\n"); > +} > + > +static void fast_copy(int xe, const intel_ctx_t *ctx, > + uint32_t region1, uint32_t region2, > + enum blt_tiling_type mid_tiling) > +{ > + struct blt_copy_data blt = {}; > + struct blt_copy_object *src, *mid, *dst; > + const uint32_t bpp = 32; > + uint64_t bb_size = xe_get_default_alignment(xe); > + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0, > + INTEL_ALLOCATOR_SIMPLE, > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > + uint32_t bb; > + uint32_t width = param.width, height = param.height; > + int result; > + > + bb = xe_bo_create_flags(xe, 0, bb_size, region1); > + > + blt_copy_init(xe, &blt); > + src = blt_create_object(&blt, region1, width, height, bpp, 0, > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > + mid = blt_create_object(&blt, region2, width, height, bpp, 0, > + mid_tiling, COMPRESSION_DISABLED, 0, true); > + dst = blt_create_object(&blt, region1, width, height, bpp, 0, > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > + igt_assert(src->size == dst->size); > + > + blt_surface_fill_rect(xe, src, width, height); > + > + blt.color_depth = CD_32bit; > + blt.print_bb = param.print_bb; > + blt_set_copy_object(&blt.src, src); > + blt_set_copy_object(&blt.dst, mid); > + blt_set_batch(&blt.bb, bb, bb_size, region1); > + > + blt_fast_copy(xe, ctx, NULL, ahnd, &blt); > + > + WRITE_PNG(xe, mid_tiling, "src", &blt.src, width, height); > + WRITE_PNG(xe, mid_tiling, "mid", &blt.dst, width, height); > + > + blt_copy_init(xe, &blt); > + blt.color_depth = CD_32bit; > + blt.print_bb = param.print_bb; > + blt_set_copy_object(&blt.src, mid); > + blt_set_copy_object(&blt.dst, dst); > + blt_set_batch(&blt.bb, bb, bb_size, region1); > + > + blt_fast_copy(xe, ctx, NULL, ahnd, &blt); > + > + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height); > + > + result = memcmp(src->ptr, blt.dst.ptr, src->size); > + > + put_offset(ahnd, src->handle); > + put_offset(ahnd, mid->handle); > + put_offset(ahnd, dst->handle); > + put_offset(ahnd, bb); > + intel_allocator_bind(ahnd, 0, 0); > + blt_destroy_object(xe, src); > + blt_destroy_object(xe, mid); > + blt_destroy_object(xe, dst); > + gem_close(xe, bb); > + put_ahnd(ahnd); > + > + igt_assert_f(!result, "source and destination surfaces differs!\n"); > +} > + > +enum fast_copy_func { > + FAST_COPY, > + FAST_COPY_EMIT > +}; > + > +static char > + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling, > + enum fast_copy_func func) > +{ > + char *name; > + uint32_t len; > + > + len = asprintf(&name, "%s-%s%s", blt_tiling_name(tiling), regtxt, > + func == FAST_COPY_EMIT ? "-emit" : ""); > + > + igt_assert_f(len >= 0, "asprintf failed!\n"); > + > + return name; > +} > + > +static void fast_copy_test(int xe, > + struct igt_collection *set, > + enum fast_copy_func func) > +{ > + struct drm_xe_engine_class_instance inst = { > + .engine_class = DRM_XE_ENGINE_CLASS_COPY, > + }; > + struct igt_collection *regions; > + void (*copy_func)(int xe, const intel_ctx_t *ctx, > + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling); > + intel_ctx_t *ctx; > + int tiling; > + > + for_each_tiling(tiling) { > + if (!blt_fast_copy_supports_tiling(xe, tiling)) > + continue; > + > + for_each_variation_r(regions, 2, set) { > + uint32_t region1, region2; > + uint32_t vm, engine; > + char *regtxt, *test_name; > + > + region1 = igt_collection_get_value(regions, 0); > + region2 = igt_collection_get_value(regions, 1); > + > + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > + engine = xe_engine_create(xe, vm, &inst, 0); > + ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0); > + > + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit; > + regtxt = xe_memregion_dynamic_subtest_name(xe, regions); > + test_name = full_subtest_str(regtxt, tiling, func); > + > + igt_dynamic_f("%s", test_name) { > + copy_func(xe, ctx, > + region1, region2, > + tiling); > + } > + > + free(regtxt); > + free(test_name); > + xe_engine_destroy(xe, engine); > + xe_vm_destroy(xe, vm); > + free(ctx); > + } > + } > +} > + > +static int opt_handler(int opt, int opt_index, void *data) > +{ > + switch (opt) { > + case 'b': > + param.print_bb = true; > + igt_debug("Print bb: %d\n", param.print_bb); > + break; > + case 'p': > + param.write_png = true; > + igt_debug("Write png: %d\n", param.write_png); > + break; > + case 's': > + param.print_surface_info = true; > + igt_debug("Print surface info: %d\n", param.print_surface_info); > + break; > + case 't': > + param.tiling = atoi(optarg); > + igt_debug("Tiling: %d\n", param.tiling); > + break; > + case 'W': > + param.width = atoi(optarg); > + igt_debug("Width: %d\n", param.width); > + break; > + case 'H': > + param.height = atoi(optarg); > + igt_debug("Height: %d\n", param.height); > + break; > + default: > + return IGT_OPT_HANDLER_ERROR; > + } > + > + return IGT_OPT_HANDLER_SUCCESS; > +} > + > +const char *help_str = > + " -b\tPrint bb\n" > + " -p\tWrite PNG\n" > + " -s\tPrint surface info\n" > + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n" > + " -W\tWidth (default 512)\n" > + " -H\tHeight (default 512)" > + ; > + > +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL) > +{ > + struct igt_collection *set; > + int xe; > + > + igt_fixture { > + xe = drm_open_driver(DRIVER_XE); > + igt_require(blt_has_fast_copy(xe)); > + > + xe_device_get(xe); > + > + set = xe_get_memory_region_set(xe, > + XE_MEM_REGION_CLASS_SYSMEM, > + XE_MEM_REGION_CLASS_VRAM); > + } > + > + igt_describe("Check fast-copy blit"); > + igt_subtest_with_dynamic("fast-copy") { > + fast_copy_test(xe, set, FAST_COPY); > + } > + > + igt_describe("Check multiple fast-copy in one batch"); > + igt_subtest_with_dynamic("fast-copy-emit") { > + fast_copy_test(xe, set, FAST_COPY_EMIT); > + } > + > + igt_fixture { > + drm_close_driver(xe); > + } > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id D01A410E4CC for ; Wed, 12 Jul 2023 10:22:27 +0000 (UTC) Message-ID: <65ad802e-bac4-f827-cd3b-82410a478ddb@intel.com> Date: Wed, 12 Jul 2023 12:22:02 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-14-zbigniew.kempczynski@intel.com> <20230712094345.rgmvtef4qf6ieq4c@zkempczy-mobl2> From: Karolina Stolarek In-Reply-To: <20230712094345.rgmvtef4qf6ieq4c@zkempczy-mobl2> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 13/17] lib/intel_blt: Extend blitter library to support xe driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 12.07.2023 11:43, Zbigniew Kempczyński wrote: > On Wed, Jul 12, 2023 at 11:22:00AM +0200, Karolina Stolarek wrote: >> On 11.07.2023 13:20, Zbigniew Kempczyński wrote: >>> Use already written for i915 blitter library in xe development. >>> Add appropriate code paths which are unique for those drivers. >>> >>> Signed-off-by: Zbigniew Kempczyński >>> --- >>> v3: Extract common helpers for getting mapping and alignment (Karolina) >>> --- >>> lib/intel_blt.c | 235 ++++++++++++++++++++++++++++++------------------ >>> lib/intel_blt.h | 2 +- >>> 2 files changed, 150 insertions(+), 87 deletions(-) >>> >>> diff --git a/lib/intel_blt.c b/lib/intel_blt.c >>> index f2f86e4947..5387a60ee3 100644 >>> --- a/lib/intel_blt.c >>> +++ b/lib/intel_blt.c >>> @@ -9,9 +9,13 @@ >>> #include >>> #include >>> #include "drm.h" >>> -#include "igt.h" >>> #include "i915/gem_create.h" >>> +#include "igt.h" >>> +#include "igt_syncobj.h" >>> #include "intel_blt.h" >>> +#include "xe/xe_ioctl.h" >>> +#include "xe/xe_query.h" >>> +#include "xe/xe_util.h" >>> #define BITRANGE(start, end) (end - start + 1) >>> #define GET_CMDS_INFO(__fd) intel_get_cmds_info(intel_get_drm_devid(__fd)) >>> @@ -468,24 +472,40 @@ static int __special_mode(const struct blt_copy_data *blt) >>> return SM_NONE; >>> } >>> -static int __memory_type(uint32_t region) >>> +static int __memory_type(int fd, enum intel_driver driver, uint32_t region) >>> { >>> - igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || >>> - IS_SYSTEM_MEMORY_REGION(region), >>> - "Invalid region: %x\n", region); >>> + if (driver == INTEL_DRIVER_I915) { >>> + igt_assert_f(IS_DEVICE_MEMORY_REGION(region) || >>> + IS_SYSTEM_MEMORY_REGION(region), >>> + "Invalid region: %x\n", region); >>> + } else { >>> + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, region) || >>> + XE_IS_SYSMEM_MEMORY_REGION(fd, region), >>> + "Invalid region: %x\n", region); >>> + } >>> - if (IS_DEVICE_MEMORY_REGION(region)) >>> + if (driver == INTEL_DRIVER_I915 && IS_DEVICE_MEMORY_REGION(region)) >>> return TM_LOCAL_MEM; >>> + else if (driver == INTEL_DRIVER_XE && XE_IS_VRAM_MEMORY_REGION(fd, region)) >>> + return TM_LOCAL_MEM; >>> + >>> return TM_SYSTEM_MEM; >>> } >>> -static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj) >>> +static enum blt_aux_mode __aux_mode(int fd, >>> + enum intel_driver driver, >>> + const struct blt_copy_object *obj) >>> { >>> - if (obj->compression == COMPRESSION_ENABLED) { >>> + if (driver == INTEL_DRIVER_I915 && obj->compression == COMPRESSION_ENABLED) { >>> igt_assert_f(IS_DEVICE_MEMORY_REGION(obj->region), >>> "XY_BLOCK_COPY_BLT supports compression " >>> "on device memory only\n"); >>> return AM_AUX_CCS_E; >>> + } else if (driver == INTEL_DRIVER_XE && obj->compression == COMPRESSION_ENABLED) { >>> + igt_assert_f(XE_IS_VRAM_MEMORY_REGION(fd, obj->region), >>> + "XY_BLOCK_COPY_BLT supports compression " >>> + "on device memory only\n"); >>> + return AM_AUX_CCS_E; >>> } >>> return AM_AUX_NONE; >>> @@ -508,9 +528,9 @@ static void fill_data(struct gen12_block_copy_data *data, >>> data->dw00.length = extended_command ? 20 : 10; >>> if (__special_mode(blt) == SM_FULL_RESOLVE) >>> - data->dw01.dst_aux_mode = __aux_mode(&blt->src); >>> + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); >>> else >>> - data->dw01.dst_aux_mode = __aux_mode(&blt->dst); >>> + data->dw01.dst_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->dst); >>> data->dw01.dst_pitch = blt->dst.pitch - 1; >>> data->dw01.dst_mocs = blt->dst.mocs; >>> @@ -531,13 +551,13 @@ static void fill_data(struct gen12_block_copy_data *data, >>> data->dw06.dst_x_offset = blt->dst.x_offset; >>> data->dw06.dst_y_offset = blt->dst.y_offset; >>> - data->dw06.dst_target_memory = __memory_type(blt->dst.region); >>> + data->dw06.dst_target_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); >>> data->dw07.src_x1 = blt->src.x1; >>> data->dw07.src_y1 = blt->src.y1; >>> data->dw08.src_pitch = blt->src.pitch - 1; >>> - data->dw08.src_aux_mode = __aux_mode(&blt->src); >>> + data->dw08.src_aux_mode = __aux_mode(blt->fd, blt->driver, &blt->src); >>> data->dw08.src_mocs = blt->src.mocs; >>> data->dw08.src_compression = blt->src.compression; >>> data->dw08.src_tiling = __block_tiling(blt->src.tiling); >>> @@ -550,7 +570,7 @@ static void fill_data(struct gen12_block_copy_data *data, >>> data->dw11.src_x_offset = blt->src.x_offset; >>> data->dw11.src_y_offset = blt->src.y_offset; >>> - data->dw11.src_target_memory = __memory_type(blt->src.region); >>> + data->dw11.src_target_memory = __memory_type(blt->fd, blt->driver, blt->src.region); >>> } >>> static void fill_data_ext(struct gen12_block_copy_data_ext *dext, >>> @@ -692,6 +712,24 @@ static void dump_bb_ext(struct gen12_block_copy_data_ext *data) >>> data->dw21.src_array_index); >>> } >>> +static uint64_t get_default_alignment(int fd, enum intel_driver driver) >>> +{ >>> + if (driver == INTEL_DRIVER_XE) >>> + return xe_get_default_alignment(fd); >>> + >>> + return gem_detect_safe_alignment(fd); >>> +} >>> + >>> +static void *bo_map(int fd, uint32_t handle, uint64_t size, >>> + enum intel_driver driver) >>> +{ >>> + if (driver == INTEL_DRIVER_XE) >>> + return xe_bo_map(fd, handle, size); >>> + >>> + return gem_mmap__device_coherent(fd, handle, 0, size, >>> + PROT_READ | PROT_WRITE); >>> +} >>> + >>> /** >>> * blt_copy_init: >>> * @fd: drm fd >>> @@ -739,7 +777,7 @@ uint64_t emit_blt_block_copy(int fd, >>> igt_assert_f(ahnd, "block-copy supports softpin only\n"); >>> igt_assert_f(blt, "block-copy requires data to do blit\n"); >>> - alignment = gem_detect_safe_alignment(fd); >>> + alignment = get_default_alignment(fd, blt->driver); >>> src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment) >>> + blt->src.plane_offset; >>> dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment) >>> @@ -748,8 +786,7 @@ uint64_t emit_blt_block_copy(int fd, >>> fill_data(&data, blt, src_offset, dst_offset, ext); >>> - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, >>> - PROT_READ | PROT_WRITE); >>> + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); >>> igt_assert(bb_pos + sizeof(data) < blt->bb.size); >>> memcpy(bb + bb_pos, &data, sizeof(data)); >>> @@ -812,29 +849,35 @@ int blt_block_copy(int fd, >>> igt_assert_f(ahnd, "block-copy supports softpin only\n"); >>> igt_assert_f(blt, "block-copy requires data to do blit\n"); >>> + igt_assert_neq(blt->driver, 0); >>> - alignment = gem_detect_safe_alignment(fd); >>> + alignment = get_default_alignment(fd, blt->driver); >>> src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); >>> dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); >>> bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); >>> emit_blt_block_copy(fd, ahnd, blt, ext, 0, true); >>> - obj[0].offset = CANONICAL(dst_offset); >>> - obj[1].offset = CANONICAL(src_offset); >>> - obj[2].offset = CANONICAL(bb_offset); >>> - obj[0].handle = blt->dst.handle; >>> - obj[1].handle = blt->src.handle; >>> - obj[2].handle = blt->bb.handle; >>> - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | >>> - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - execbuf.buffer_count = 3; >>> - execbuf.buffers_ptr = to_user_pointer(obj); >>> - execbuf.rsvd1 = ctx ? ctx->id : 0; >>> - execbuf.flags = e ? e->flags : I915_EXEC_BLT; >>> - ret = __gem_execbuf(fd, &execbuf); >>> + if (blt->driver == INTEL_DRIVER_XE) { >>> + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); >>> + } else { >>> + obj[0].offset = CANONICAL(dst_offset); >>> + obj[1].offset = CANONICAL(src_offset); >>> + obj[2].offset = CANONICAL(bb_offset); >>> + obj[0].handle = blt->dst.handle; >>> + obj[1].handle = blt->src.handle; >>> + obj[2].handle = blt->bb.handle; >>> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | >>> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + execbuf.buffer_count = 3; >>> + execbuf.buffers_ptr = to_user_pointer(obj); >>> + execbuf.rsvd1 = ctx ? ctx->id : 0; >>> + execbuf.flags = e ? e->flags : I915_EXEC_BLT; >>> + >>> + ret = __gem_execbuf(fd, &execbuf); >>> + } >>> return ret; >>> } >>> @@ -950,7 +993,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, >>> igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); >>> igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); >>> - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); >>> + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); >>> data.dw00.client = 0x2; >>> data.dw00.opcode = 0x48; >>> @@ -973,8 +1016,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, >>> data.dw04.dst_address_hi = dst_offset >> 32; >>> data.dw04.dst_mocs = surf->dst.mocs; >>> - bb = gem_mmap__device_coherent(fd, surf->bb.handle, 0, surf->bb.size, >>> - PROT_READ | PROT_WRITE); >>> + bb = bo_map(fd, surf->bb.handle, surf->bb.size, surf->driver); >>> igt_assert(bb_pos + sizeof(data) < surf->bb.size); >>> memcpy(bb + bb_pos, &data, sizeof(data)); >>> @@ -1002,7 +1044,7 @@ uint64_t emit_blt_ctrl_surf_copy(int fd, >>> /** >>> * blt_ctrl_surf_copy: >>> - * @fd: drm fd >>> + * @blt: bldrm fd >> >> Emm, the argument seem to still be fd, and there's no blt. A typo? > > I'm not sure how this appeared here. Will fix and send in v4. > >> >> Thanks for adding the helpers, the code looks nice and tidy (although I'm >> scared of __special_mode and the like, but there's no better way to do it). > > Yes, I also don't see better way to handle two different drivers here. > But I believe conditional is readable and easily understandable. It is readable, so I'm fine with leaving it as it is. All the best, Karolina > > -- > Zbigniew > >> >> All the best, >> Karolina >> >>> * @ctx: intel_ctx_t context >>> * @e: blitter engine for @ctx >>> * @ahnd: allocator handle >>> @@ -1026,32 +1068,37 @@ int blt_ctrl_surf_copy(int fd, >>> igt_assert_f(ahnd, "ctrl-surf-copy supports softpin only\n"); >>> igt_assert_f(surf, "ctrl-surf-copy requires data to do ctrl-surf-copy blit\n"); >>> + igt_assert_neq(surf->driver, 0); >>> - alignment = max_t(uint64_t, gem_detect_safe_alignment(fd), 1ull << 16); >>> + alignment = max_t(uint64_t, get_default_alignment(fd, surf->driver), 1ull << 16); >>> src_offset = get_offset(ahnd, surf->src.handle, surf->src.size, alignment); >>> dst_offset = get_offset(ahnd, surf->dst.handle, surf->dst.size, alignment); >>> bb_offset = get_offset(ahnd, surf->bb.handle, surf->bb.size, alignment); >>> emit_blt_ctrl_surf_copy(fd, ahnd, surf, 0, true); >>> - obj[0].offset = CANONICAL(dst_offset); >>> - obj[1].offset = CANONICAL(src_offset); >>> - obj[2].offset = CANONICAL(bb_offset); >>> - obj[0].handle = surf->dst.handle; >>> - obj[1].handle = surf->src.handle; >>> - obj[2].handle = surf->bb.handle; >>> - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | >>> - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - execbuf.buffer_count = 3; >>> - execbuf.buffers_ptr = to_user_pointer(obj); >>> - execbuf.flags = e ? e->flags : I915_EXEC_BLT; >>> - execbuf.rsvd1 = ctx ? ctx->id : 0; >>> - gem_execbuf(fd, &execbuf); >>> - put_offset(ahnd, surf->dst.handle); >>> - put_offset(ahnd, surf->src.handle); >>> - put_offset(ahnd, surf->bb.handle); >>> + if (surf->driver == INTEL_DRIVER_XE) { >>> + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); >>> + } else { >>> + obj[0].offset = CANONICAL(dst_offset); >>> + obj[1].offset = CANONICAL(src_offset); >>> + obj[2].offset = CANONICAL(bb_offset); >>> + obj[0].handle = surf->dst.handle; >>> + obj[1].handle = surf->src.handle; >>> + obj[2].handle = surf->bb.handle; >>> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | >>> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + execbuf.buffer_count = 3; >>> + execbuf.buffers_ptr = to_user_pointer(obj); >>> + execbuf.flags = e ? e->flags : I915_EXEC_BLT; >>> + execbuf.rsvd1 = ctx ? ctx->id : 0; >>> + gem_execbuf(fd, &execbuf); >>> + put_offset(ahnd, surf->dst.handle); >>> + put_offset(ahnd, surf->src.handle); >>> + put_offset(ahnd, surf->bb.handle); >>> + } >>> return 0; >>> } >>> @@ -1208,7 +1255,7 @@ uint64_t emit_blt_fast_copy(int fd, >>> uint32_t bbe = MI_BATCH_BUFFER_END; >>> uint32_t *bb; >>> - alignment = gem_detect_safe_alignment(fd); >>> + alignment = get_default_alignment(fd, blt->driver); >>> data.dw00.client = 0x2; >>> data.dw00.opcode = 0x42; >>> @@ -1218,8 +1265,8 @@ uint64_t emit_blt_fast_copy(int fd, >>> data.dw01.dst_pitch = blt->dst.pitch; >>> data.dw01.color_depth = __fast_color_depth(blt->color_depth); >>> - data.dw01.dst_memory = __memory_type(blt->dst.region); >>> - data.dw01.src_memory = __memory_type(blt->src.region); >>> + data.dw01.dst_memory = __memory_type(blt->fd, blt->driver, blt->dst.region); >>> + data.dw01.src_memory = __memory_type(blt->fd, blt->driver, blt->src.region); >>> data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0; >>> data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0; >>> @@ -1246,8 +1293,7 @@ uint64_t emit_blt_fast_copy(int fd, >>> data.dw08.src_address_lo = src_offset; >>> data.dw09.src_address_hi = src_offset >> 32; >>> - bb = gem_mmap__device_coherent(fd, blt->bb.handle, 0, blt->bb.size, >>> - PROT_READ | PROT_WRITE); >>> + bb = bo_map(fd, blt->bb.handle, blt->bb.size, blt->driver); >>> igt_assert(bb_pos + sizeof(data) < blt->bb.size); >>> memcpy(bb + bb_pos, &data, sizeof(data)); >>> @@ -1297,32 +1343,39 @@ int blt_fast_copy(int fd, >>> uint64_t dst_offset, src_offset, bb_offset, alignment; >>> int ret; >>> - alignment = gem_detect_safe_alignment(fd); >>> + igt_assert_f(ahnd, "fast-copy supports softpin only\n"); >>> + igt_assert_f(blt, "fast-copy requires data to do fast-copy blit\n"); >>> + igt_assert_neq(blt->driver, 0); >>> + alignment = get_default_alignment(fd, blt->driver); >>> src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment); >>> dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); >>> bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); >>> emit_blt_fast_copy(fd, ahnd, blt, 0, true); >>> - obj[0].offset = CANONICAL(dst_offset); >>> - obj[1].offset = CANONICAL(src_offset); >>> - obj[2].offset = CANONICAL(bb_offset); >>> - obj[0].handle = blt->dst.handle; >>> - obj[1].handle = blt->src.handle; >>> - obj[2].handle = blt->bb.handle; >>> - obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | >>> - EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> - execbuf.buffer_count = 3; >>> - execbuf.buffers_ptr = to_user_pointer(obj); >>> - execbuf.rsvd1 = ctx ? ctx->id : 0; >>> - execbuf.flags = e ? e->flags : I915_EXEC_BLT; >>> - ret = __gem_execbuf(fd, &execbuf); >>> - put_offset(ahnd, blt->dst.handle); >>> - put_offset(ahnd, blt->src.handle); >>> - put_offset(ahnd, blt->bb.handle); >>> + if (blt->driver == INTEL_DRIVER_XE) { >>> + intel_ctx_xe_exec(ctx, ahnd, CANONICAL(bb_offset)); >>> + } else { >>> + obj[0].offset = CANONICAL(dst_offset); >>> + obj[1].offset = CANONICAL(src_offset); >>> + obj[2].offset = CANONICAL(bb_offset); >>> + obj[0].handle = blt->dst.handle; >>> + obj[1].handle = blt->src.handle; >>> + obj[2].handle = blt->bb.handle; >>> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE | >>> + EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + obj[1].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + obj[2].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS; >>> + execbuf.buffer_count = 3; >>> + execbuf.buffers_ptr = to_user_pointer(obj); >>> + execbuf.rsvd1 = ctx ? ctx->id : 0; >>> + execbuf.flags = e ? e->flags : I915_EXEC_BLT; >>> + ret = __gem_execbuf(fd, &execbuf); >>> + put_offset(ahnd, blt->dst.handle); >>> + put_offset(ahnd, blt->src.handle); >>> + put_offset(ahnd, blt->bb.handle); >>> + } >>> return ret; >>> } >>> @@ -1366,16 +1419,21 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region, >>> obj = calloc(1, sizeof(*obj)); >>> obj->size = size; >>> - igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, >>> - &size, region) == 0); >>> + >>> + if (blt->driver == INTEL_DRIVER_XE) { >>> + size = ALIGN(size, xe_get_default_alignment(blt->fd)); >>> + handle = xe_bo_create_flags(blt->fd, 0, size, region); >>> + } else { >>> + igt_assert(__gem_create_in_memory_regions(blt->fd, &handle, >>> + &size, region) == 0); >>> + } >>> blt_set_object(obj, handle, size, region, mocs, tiling, >>> compression, compression_type); >>> blt_set_geom(obj, stride, 0, 0, width, height, 0, 0); >>> if (create_mapping) >>> - obj->ptr = gem_mmap__device_coherent(blt->fd, handle, 0, size, >>> - PROT_READ | PROT_WRITE); >>> + obj->ptr = bo_map(blt->fd, handle, size, blt->driver); >>> return obj; >>> } >>> @@ -1518,14 +1576,19 @@ void blt_surface_to_png(int fd, uint32_t run_id, const char *fileid, >>> int format; >>> int stride = obj->tiling ? obj->pitch * 4 : obj->pitch; >>> char filename[FILENAME_MAX]; >>> + bool is_xe = is_xe_device(fd); >>> snprintf(filename, FILENAME_MAX-1, "%d-%s-%s-%ux%u-%s.png", >>> run_id, fileid, blt_tiling_name(obj->tiling), width, height, >>> obj->compression ? "compressed" : "uncompressed"); >>> - if (!map) >>> - map = gem_mmap__device_coherent(fd, obj->handle, 0, >>> - obj->size, PROT_READ); >>> + if (!map) { >>> + if (is_xe) >>> + map = xe_bo_map(fd, obj->handle, obj->size); >>> + else >>> + map = gem_mmap__device_coherent(fd, obj->handle, 0, >>> + obj->size, PROT_READ); >>> + } >>> format = CAIRO_FORMAT_RGB24; >>> surface = cairo_image_surface_create_for_data(map, >>> format, width, height, >>> diff --git a/lib/intel_blt.h b/lib/intel_blt.h >>> index 7516ce8ac7..944e2b4ae7 100644 >>> --- a/lib/intel_blt.h >>> +++ b/lib/intel_blt.h >>> @@ -8,7 +8,7 @@ >>> /** >>> * SECTION:intel_blt >>> - * @short_description: i915 blitter library >>> + * @short_description: i915/xe blitter library >>> * @title: Blitter library >>> * @include: intel_blt.h >>> * From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 56A8710E4D0 for ; Wed, 12 Jul 2023 10:40:12 +0000 (UTC) Message-ID: <437559c5-8676-2430-220a-bfa8b2575959@intel.com> Date: Wed, 12 Jul 2023 12:39:42 +0200 Content-Language: en-US To: =?UTF-8?Q?Zbigniew_Kempczy=c5=84ski?= References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-11-zbigniew.kempczynski@intel.com> <01576293-301d-c3c7-29f1-2f23a04fe2ae@intel.com> <20230712093357.atvsv7m4chl6iebn@zkempczy-mobl2> From: Karolina Stolarek In-Reply-To: <20230712093357.atvsv7m4chl6iebn@zkempczy-mobl2> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit MIME-Version: 1.0 Subject: Re: [igt-dev] [PATCH i-g-t v3 10/17] lib/intel_allocator: Add intel_allocator_bind() List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On 12.07.2023 11:33, Zbigniew Kempczyński wrote: > On Wed, Jul 12, 2023 at 11:13:24AM +0200, Karolina Stolarek wrote: >> On 11.07.2023 13:20, Zbigniew Kempczyński wrote: >>> Synchronize allocator state to vm. >>> >>> This change allows xe user to execute vm-bind/unbind for allocator >>> alloc()/free() operations which occurred since last binding/unbinding. >>> Before doing exec user should call intel_allocator_bind() to ensure >>> all vma's are in place. >>> >>> Signed-off-by: Zbigniew Kempczyński >>> --- >>> v2: Rewrite tracking mechanism: previous code uses bind map embedded >>> in allocator structure. Unfortunately this wasn't good idea >>> - for xe binding everything was fine, but it regress multiprocess/ >>> multithreaded allocations. Main reason of this was children >>> processes couldn't get its reference as this memory was allocated >>> on allocator thread (separate process). Currently each child >>> contains its own separate tracking maps for ahnd and for each >>> ahnd bind map. >>> v3: - Don't use priv field (we may clean bind_map apriori as failing >>> asserts and outdated bind_map is not a problem anymore). >>> - Use only vm on tracking ahnd (Karolina) >>> - Add braces to avoid checkpatch complaining (Karolina) >>> - Use igt_assert_f() instead conditional block (Karolina) >>> --- >>> lib/igt_core.c | 5 + >>> lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++- >>> lib/intel_allocator.h | 3 + >>> 3 files changed, 265 insertions(+), 2 deletions(-) >>> >>> diff --git a/lib/igt_core.c b/lib/igt_core.c >>> index 2ae2cb6883..041e4b3288 100644 >>> --- a/lib/igt_core.c >>> +++ b/lib/igt_core.c >>> @@ -74,6 +74,7 @@ >>> #include "igt_sysrq.h" >>> #include "igt_rc.h" >>> #include "igt_list.h" >>> +#include "igt_map.h" >>> #include "igt_device_scan.h" >>> #include "igt_thread.h" >>> #include "runnercomms.h" >>> @@ -320,6 +321,8 @@ bool test_multi_fork_child; >>> /* For allocator purposes */ >>> pid_t child_pid = -1; >>> __thread pid_t child_tid = -1; >>> +struct igt_map *ahnd_map; >>> +pthread_mutex_t ahnd_map_mutex; >>> enum { >>> /* >>> @@ -2523,6 +2526,8 @@ bool __igt_fork(void) >>> case 0: >>> test_child = true; >>> pthread_mutex_init(&print_mutex, NULL); >>> + pthread_mutex_init(&ahnd_map_mutex, NULL); >>> + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); >>> child_pid = getpid(); >>> child_tid = -1; >>> exit_handler_count = 0; >>> diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c >>> index cf964ccc41..f0a9b7fb53 100644 >>> --- a/lib/intel_allocator.c >>> +++ b/lib/intel_allocator.c >>> @@ -17,8 +17,8 @@ >>> #include "intel_allocator.h" >>> #include "intel_allocator_msgchannel.h" >>> #include "xe/xe_query.h" >>> +#include "xe/xe_util.h" >>> -//#define ALLOCDBG >>> #ifdef ALLOCDBG >>> #define alloc_info igt_info >>> #define alloc_debug igt_debug >>> @@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type) >>> #define alloc_debug(...) {} >>> #endif >>> +#ifdef ALLOCBINDDBG >>> +#define bind_info igt_info >>> +#define bind_debug igt_debug >>> +#else >>> +#define bind_info(...) {} >>> +#define bind_debug(...) {} >>> +#endif >>> + >>> /* >>> * We limit allocator space to avoid hang when batch would be >>> * pinned in the last page. >>> @@ -64,6 +72,30 @@ struct handle_entry { >>> struct allocator *al; >>> }; >>> +/* For tracking alloc()/free() for Xe */ >>> +struct ahnd_info { >>> + int fd; >>> + uint64_t ahnd; >>> + uint32_t vm; >>> + enum intel_driver driver; >>> + struct igt_map *bind_map; >>> + pthread_mutex_t bind_map_mutex; >>> +}; >>> + >>> +enum allocator_bind_op { >>> + BOUND, >>> + TO_BIND, >>> + TO_UNBIND, >>> +}; >>> + >>> +struct allocator_object { >>> + uint32_t handle; >>> + uint64_t offset; >>> + uint64_t size; >>> + >>> + enum allocator_bind_op bind_op; >>> +}; >>> + >>> struct intel_allocator * >>> intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); >>> struct intel_allocator * >>> @@ -122,6 +154,13 @@ static pid_t allocator_pid = -1; >>> extern pid_t child_pid; >>> extern __thread pid_t child_tid; >>> +/* >>> + * Track alloc()/free() requires storing in local process which has >>> + * an access to real drm fd it can work on. >>> + */ >>> +extern struct igt_map *ahnd_map; >>> +extern pthread_mutex_t ahnd_map_mutex; >>> + >>> /* >>> * - for parent process we have child_pid == -1 >>> * - for child which calls intel_allocator_init() allocator_pid == child_pid >>> @@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void) >>> } >>> } >>> +static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm) >>> +{ >>> + struct ahnd_info *ainfo; >>> + >>> + pthread_mutex_lock(&ahnd_map_mutex); >>> + ainfo = igt_map_search(ahnd_map, &ahnd); >>> + if (!ainfo) { >>> + ainfo = malloc(sizeof(*ainfo)); >>> + ainfo->fd = fd; >>> + ainfo->ahnd = ahnd; >>> + ainfo->vm = vm; >>> + ainfo->driver = get_intel_driver(fd); >>> + ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32); >>> + pthread_mutex_init(&ainfo->bind_map_mutex, NULL); >>> + bind_debug("[TRACK AHND] pid: %d, tid: %d, create >> + "ahnd: %llx, vm: %u, driver: %d, ahnd_map: %p, bind_map: %p>\n", >>> + getpid(), gettid(), ainfo->fd, >>> + (long long)ainfo->ahnd, ainfo->vm, >>> + ainfo->driver, ahnd_map, ainfo->bind_map); >>> + igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo); >>> + } >>> + >>> + pthread_mutex_unlock(&ahnd_map_mutex); >>> +} >>> + >>> +static void untrack_ahnd(uint64_t ahnd) >>> +{ >>> + struct ahnd_info *ainfo; >>> + >>> + pthread_mutex_lock(&ahnd_map_mutex); >>> + ainfo = igt_map_search(ahnd_map, &ahnd); >>> + if (ainfo) { >>> + bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n", >>> + getpid(), gettid(), (long long)ahnd); >>> + igt_map_remove(ahnd_map, &ahnd, map_entry_free_func); >>> + } >>> + pthread_mutex_unlock(&ahnd_map_mutex); >>> +} >>> + >>> static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, >>> uint32_t vm, >>> uint64_t start, uint64_t end, >>> @@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, >>> igt_assert(resp.open.allocator_handle); >>> igt_assert(resp.response_type == RESP_OPEN); >>> + /* >>> + * Igts mostly uses ctx as id when opening the allocator (i915 legacy). >>> + * If ctx is passed let's use it as an vm id, otherwise use vm. >>> + */ >>> + track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm); >>> + >>> return resp.open.allocator_handle; >>> } >>> @@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle) >>> igt_assert(handle_request(&req, &resp) == 0); >>> igt_assert(resp.response_type == RESP_CLOSE); >>> + untrack_ahnd(allocator_handle); >>> + >>> return resp.close.is_empty; >>> } >>> @@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle, >>> *endp = resp.address_range.end; >>> } >>> +static bool is_same(struct allocator_object *obj, >>> + uint32_t handle, uint64_t offset, uint64_t size, >>> + enum allocator_bind_op bind_op) >>> +{ >>> + return obj->handle == handle && obj->offset == offset && obj->size == size && >>> + (obj->bind_op == bind_op || obj->bind_op == BOUND); >>> +} >>> + >>> +static void track_object(uint64_t allocator_handle, uint32_t handle, >>> + uint64_t offset, uint64_t size, >>> + enum allocator_bind_op bind_op) >>> +{ >>> + struct ahnd_info *ainfo; >>> + struct allocator_object *obj; >>> + >>> + bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n", >>> + bind_op == TO_BIND ? "BIND" : "UNBIND", >>> + getpid(), gettid(), >>> + (long long)allocator_handle, >>> + handle, (long long)offset, (long long)size); >>> + >>> + if (offset == ALLOC_INVALID_ADDRESS) { >>> + bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n", >>> + (long long)offset); >>> + return; >>> + } >>> + >>> + pthread_mutex_lock(&ahnd_map_mutex); >>> + ainfo = igt_map_search(ahnd_map, &allocator_handle); >>> + pthread_mutex_unlock(&ahnd_map_mutex); >>> + igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n", >>> + (long long)allocator_handle); >>> + >>> + if (ainfo->driver == INTEL_DRIVER_I915) >>> + return; /* no-op for i915, at least for now */ >>> + >>> + pthread_mutex_lock(&ainfo->bind_map_mutex); >>> + obj = igt_map_search(ainfo->bind_map, &handle); >>> + if (obj) { >>> + /* >>> + * User may call alloc() couple of times, check object is the >>> + * same. For free() there's simple case, just remove from >>> + * bind_map. >>> + */ >>> + if (bind_op == TO_BIND) { >>> + igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true); >>> + } else if (bind_op == TO_UNBIND) { >>> + if (obj->bind_op == TO_BIND) >>> + igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func); >>> + else if (obj->bind_op == BOUND) >>> + obj->bind_op = bind_op; >>> + } >>> + } else { >>> + /* Ignore to unbind bo which wasn't previously inserted */ >>> + if (bind_op == TO_UNBIND) >>> + goto out; >>> + >>> + obj = calloc(1, sizeof(*obj)); >>> + obj->handle = handle; >>> + obj->offset = offset; >>> + obj->size = size; >>> + obj->bind_op = bind_op; >>> + igt_map_insert(ainfo->bind_map, &obj->handle, obj); >>> + } >>> +out: >>> + pthread_mutex_unlock(&ainfo->bind_map_mutex); >>> +} >>> + >>> /** >>> * __intel_allocator_alloc: >>> * @allocator_handle: handle to an allocator >>> @@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, >>> igt_assert(handle_request(&req, &resp) == 0); >>> igt_assert(resp.response_type == RESP_ALLOC); >>> + track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND); >>> + >>> return resp.alloc.offset; >>> } >>> @@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle) >>> igt_assert(handle_request(&req, &resp) == 0); >>> igt_assert(resp.response_type == RESP_FREE); >>> + track_object(allocator_handle, handle, 0, 0, TO_UNBIND); >>> + >>> return resp.free.freed; >>> } >>> @@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle) >>> } >>> } >>> +static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out) >>> +{ >>> + struct allocator_object *obj; >>> + struct igt_map_entry *pos; >>> + struct igt_list_head obj_list; >>> + struct xe_object *entry, *tmp; >>> + >>> + IGT_INIT_LIST_HEAD(&obj_list); >>> + >>> + pthread_mutex_lock(&ainfo->bind_map_mutex); >>> + igt_map_foreach(ainfo->bind_map, pos) { >>> + obj = pos->data; >>> + >>> + if (obj->bind_op == BOUND) >>> + continue; >>> + >>> + bind_info("= [vm: %u] %s => %u %lx %lx\n", >>> + ainfo->vm, >>> + obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND", >>> + obj->handle, obj->offset, >>> + obj->size); >>> + >>> + entry = malloc(sizeof(*entry)); >>> + entry->handle = obj->handle; >>> + entry->offset = obj->offset; >>> + entry->size = obj->size; >>> + entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND : >>> + XE_OBJECT_UNBIND; >>> + igt_list_add(&entry->link, &obj_list); >>> + >>> + /* >>> + * We clean bind_map even before calling bind/unbind >>> + * as all binding operations asserts in case of error. >>> + */ >>> + if (obj->bind_op == TO_BIND) >>> + obj->bind_op = BOUND; >>> + else >>> + igt_map_remove(ainfo->bind_map, &obj->handle, >>> + map_entry_free_func); >> >> I don't quite understand why we can clean up the map even before the actual >> bind/unbind happens. If an assert fails, it means that vm_(un)bind failed, >> so the actual operation didn't succeed, and that state change is incorrect. >> I believe that there's a reason we can do it this way, I just don't >> understand it. > > I allocate separate list of xe_objects which is an argument to > xe_bind_unbind_async(). As list is detached (separate) from the bind_map > I may apriori do cleanup in the map. If bind/unbind is unsuccessful > outdated bind_map is the smallest problem here. I'm aware they are separate entities, I just wonder what is the benefit of doing it here. Are there any dangers of removing that binding before it's actually unbound? All the best, Karolina > On assert path igt_fail() > calls intel_allocator_init() which just frees contents on ahnd_map[]->bind_map. > In children there's simpler because they just dies. Real problem is we > still have dangling vm (no xe_vm_destroy()). > So I decided to update the bind_map before calling bind/unbind as on failure > doesn't matter what it will contain. > > -- > Zbigniew > >> >> Apart from that one thing, the patch looks good to me. >> >> All the best, >> Karolina >> >>> + } >>> + pthread_mutex_unlock(&ainfo->bind_map_mutex); >>> + >>> + xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out); >>> + >>> + igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) { >>> + igt_list_del(&entry->link); >>> + free(entry); >>> + } >>> +} >>> + >>> +/** >>> + * intel_allocator_bind: >>> + * @allocator_handle: handle to an allocator >>> + * @sync_in: syncobj (fence-in) >>> + * @sync_out: syncobj (fence-out) >>> + * >>> + * Function binds and unbinds all objects added to the allocator which weren't >>> + * previously binded/unbinded. >>> + * >>> + **/ >>> +void intel_allocator_bind(uint64_t allocator_handle, >>> + uint32_t sync_in, uint32_t sync_out) >>> +{ >>> + struct ahnd_info *ainfo; >>> + >>> + pthread_mutex_lock(&ahnd_map_mutex); >>> + ainfo = igt_map_search(ahnd_map, &allocator_handle); >>> + pthread_mutex_unlock(&ahnd_map_mutex); >>> + igt_assert(ainfo); >>> + >>> + /* >>> + * We collect bind/unbind operations on alloc()/free() to do group >>> + * operation getting @sync_in as syncobj handle (fence-in). If user >>> + * passes 0 as @sync_out we bind/unbind synchronously. >>> + */ >>> + __xe_op_bind(ainfo, sync_in, sync_out); >>> +} >>> + >>> static int equal_handles(const void *key1, const void *key2) >>> { >>> const struct handle_entry *h1 = key1, *h2 = key2; >>> @@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators) >>> igt_map_destroy(map, map_entry_free_func); >>> } >>> +static void __free_ahnd_map(void) >>> +{ >>> + struct igt_map_entry *pos; >>> + struct ahnd_info *ainfo; >>> + >>> + if (!ahnd_map) >>> + return; >>> + >>> + igt_map_foreach(ahnd_map, pos) { >>> + ainfo = pos->data; >>> + igt_map_destroy(ainfo->bind_map, map_entry_free_func); >>> + } >>> + >>> + igt_map_destroy(ahnd_map, map_entry_free_func); >>> +} >>> + >>> /** >>> * intel_allocator_init: >>> * >>> @@ -1400,12 +1652,15 @@ void intel_allocator_init(void) >>> __free_maps(handles, true); >>> __free_maps(ctx_map, false); >>> __free_maps(vm_map, false); >>> + __free_ahnd_map(); >>> atomic_init(&next_handle, 1); >>> handles = igt_map_create(hash_handles, equal_handles); >>> ctx_map = igt_map_create(hash_instance, equal_ctx); >>> vm_map = igt_map_create(hash_instance, equal_vm); >>> - igt_assert(handles && ctx_map && vm_map); >>> + pthread_mutex_init(&ahnd_map_mutex, NULL); >>> + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); >>> + igt_assert(handles && ctx_map && vm_map && ahnd_map); >>> channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE); >>> } >>> diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h >>> index 3ec74f6191..f9ff7f1cc9 100644 >>> --- a/lib/intel_allocator.h >>> +++ b/lib/intel_allocator.h >>> @@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle, >>> void intel_allocator_print(uint64_t allocator_handle); >>> +void intel_allocator_bind(uint64_t allocator_handle, >>> + uint32_t sync_in, uint32_t sync_out); >>> + >>> #define ALLOC_INVALID_ADDRESS (-1ull) >>> #define INTEL_ALLOCATOR_NONE 0 >>> #define INTEL_ALLOCATOR_RELOC 1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA98710E599 for ; Wed, 12 Jul 2023 17:03:13 +0000 (UTC) Date: Wed, 12 Jul 2023 19:03:03 +0200 From: Zbigniew =?utf-8?Q?Kempczy=C5=84ski?= To: Karolina Stolarek Message-ID: <20230712170303.ywauy7iekte2w2gq@zkempczy-mobl2> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-11-zbigniew.kempczynski@intel.com> <01576293-301d-c3c7-29f1-2f23a04fe2ae@intel.com> <20230712093357.atvsv7m4chl6iebn@zkempczy-mobl2> <437559c5-8676-2430-220a-bfa8b2575959@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <437559c5-8676-2430-220a-bfa8b2575959@intel.com> Subject: Re: [igt-dev] [PATCH i-g-t v3 10/17] lib/intel_allocator: Add intel_allocator_bind() List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On Wed, Jul 12, 2023 at 12:39:42PM +0200, Karolina Stolarek wrote: > On 12.07.2023 11:33, Zbigniew Kempczyński wrote: > > On Wed, Jul 12, 2023 at 11:13:24AM +0200, Karolina Stolarek wrote: > > > On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > > > > Synchronize allocator state to vm. > > > > > > > > This change allows xe user to execute vm-bind/unbind for allocator > > > > alloc()/free() operations which occurred since last binding/unbinding. > > > > Before doing exec user should call intel_allocator_bind() to ensure > > > > all vma's are in place. > > > > > > > > Signed-off-by: Zbigniew Kempczyński > > > > --- > > > > v2: Rewrite tracking mechanism: previous code uses bind map embedded > > > > in allocator structure. Unfortunately this wasn't good idea > > > > - for xe binding everything was fine, but it regress multiprocess/ > > > > multithreaded allocations. Main reason of this was children > > > > processes couldn't get its reference as this memory was allocated > > > > on allocator thread (separate process). Currently each child > > > > contains its own separate tracking maps for ahnd and for each > > > > ahnd bind map. > > > > v3: - Don't use priv field (we may clean bind_map apriori as failing > > > > asserts and outdated bind_map is not a problem anymore). > > > > - Use only vm on tracking ahnd (Karolina) > > > > - Add braces to avoid checkpatch complaining (Karolina) > > > > - Use igt_assert_f() instead conditional block (Karolina) > > > > --- > > > > lib/igt_core.c | 5 + > > > > lib/intel_allocator.c | 259 +++++++++++++++++++++++++++++++++++++++++- > > > > lib/intel_allocator.h | 3 + > > > > 3 files changed, 265 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/lib/igt_core.c b/lib/igt_core.c > > > > index 2ae2cb6883..041e4b3288 100644 > > > > --- a/lib/igt_core.c > > > > +++ b/lib/igt_core.c > > > > @@ -74,6 +74,7 @@ > > > > #include "igt_sysrq.h" > > > > #include "igt_rc.h" > > > > #include "igt_list.h" > > > > +#include "igt_map.h" > > > > #include "igt_device_scan.h" > > > > #include "igt_thread.h" > > > > #include "runnercomms.h" > > > > @@ -320,6 +321,8 @@ bool test_multi_fork_child; > > > > /* For allocator purposes */ > > > > pid_t child_pid = -1; > > > > __thread pid_t child_tid = -1; > > > > +struct igt_map *ahnd_map; > > > > +pthread_mutex_t ahnd_map_mutex; > > > > enum { > > > > /* > > > > @@ -2523,6 +2526,8 @@ bool __igt_fork(void) > > > > case 0: > > > > test_child = true; > > > > pthread_mutex_init(&print_mutex, NULL); > > > > + pthread_mutex_init(&ahnd_map_mutex, NULL); > > > > + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); > > > > child_pid = getpid(); > > > > child_tid = -1; > > > > exit_handler_count = 0; > > > > diff --git a/lib/intel_allocator.c b/lib/intel_allocator.c > > > > index cf964ccc41..f0a9b7fb53 100644 > > > > --- a/lib/intel_allocator.c > > > > +++ b/lib/intel_allocator.c > > > > @@ -17,8 +17,8 @@ > > > > #include "intel_allocator.h" > > > > #include "intel_allocator_msgchannel.h" > > > > #include "xe/xe_query.h" > > > > +#include "xe/xe_util.h" > > > > -//#define ALLOCDBG > > > > #ifdef ALLOCDBG > > > > #define alloc_info igt_info > > > > #define alloc_debug igt_debug > > > > @@ -45,6 +45,14 @@ static inline const char *reqstr(enum reqtype request_type) > > > > #define alloc_debug(...) {} > > > > #endif > > > > +#ifdef ALLOCBINDDBG > > > > +#define bind_info igt_info > > > > +#define bind_debug igt_debug > > > > +#else > > > > +#define bind_info(...) {} > > > > +#define bind_debug(...) {} > > > > +#endif > > > > + > > > > /* > > > > * We limit allocator space to avoid hang when batch would be > > > > * pinned in the last page. > > > > @@ -64,6 +72,30 @@ struct handle_entry { > > > > struct allocator *al; > > > > }; > > > > +/* For tracking alloc()/free() for Xe */ > > > > +struct ahnd_info { > > > > + int fd; > > > > + uint64_t ahnd; > > > > + uint32_t vm; > > > > + enum intel_driver driver; > > > > + struct igt_map *bind_map; > > > > + pthread_mutex_t bind_map_mutex; > > > > +}; > > > > + > > > > +enum allocator_bind_op { > > > > + BOUND, > > > > + TO_BIND, > > > > + TO_UNBIND, > > > > +}; > > > > + > > > > +struct allocator_object { > > > > + uint32_t handle; > > > > + uint64_t offset; > > > > + uint64_t size; > > > > + > > > > + enum allocator_bind_op bind_op; > > > > +}; > > > > + > > > > struct intel_allocator * > > > > intel_allocator_reloc_create(int fd, uint64_t start, uint64_t end); > > > > struct intel_allocator * > > > > @@ -122,6 +154,13 @@ static pid_t allocator_pid = -1; > > > > extern pid_t child_pid; > > > > extern __thread pid_t child_tid; > > > > +/* > > > > + * Track alloc()/free() requires storing in local process which has > > > > + * an access to real drm fd it can work on. > > > > + */ > > > > +extern struct igt_map *ahnd_map; > > > > +extern pthread_mutex_t ahnd_map_mutex; > > > > + > > > > /* > > > > * - for parent process we have child_pid == -1 > > > > * - for child which calls intel_allocator_init() allocator_pid == child_pid > > > > @@ -837,6 +876,45 @@ void intel_allocator_multiprocess_stop(void) > > > > } > > > > } > > > > +static void track_ahnd(int fd, uint64_t ahnd, uint32_t vm) > > > > +{ > > > > + struct ahnd_info *ainfo; > > > > + > > > > + pthread_mutex_lock(&ahnd_map_mutex); > > > > + ainfo = igt_map_search(ahnd_map, &ahnd); > > > > + if (!ainfo) { > > > > + ainfo = malloc(sizeof(*ainfo)); > > > > + ainfo->fd = fd; > > > > + ainfo->ahnd = ahnd; > > > > + ainfo->vm = vm; > > > > + ainfo->driver = get_intel_driver(fd); > > > > + ainfo->bind_map = igt_map_create(igt_map_hash_32, igt_map_equal_32); > > > > + pthread_mutex_init(&ainfo->bind_map_mutex, NULL); > > > > + bind_debug("[TRACK AHND] pid: %d, tid: %d, create > > > + "ahnd: %llx, vm: %u, driver: %d, ahnd_map: %p, bind_map: %p>\n", > > > > + getpid(), gettid(), ainfo->fd, > > > > + (long long)ainfo->ahnd, ainfo->vm, > > > > + ainfo->driver, ahnd_map, ainfo->bind_map); > > > > + igt_map_insert(ahnd_map, &ainfo->ahnd, ainfo); > > > > + } > > > > + > > > > + pthread_mutex_unlock(&ahnd_map_mutex); > > > > +} > > > > + > > > > +static void untrack_ahnd(uint64_t ahnd) > > > > +{ > > > > + struct ahnd_info *ainfo; > > > > + > > > > + pthread_mutex_lock(&ahnd_map_mutex); > > > > + ainfo = igt_map_search(ahnd_map, &ahnd); > > > > + if (ainfo) { > > > > + bind_debug("[UNTRACK AHND]: pid: %d, tid: %d, removing ahnd: %llx\n", > > > > + getpid(), gettid(), (long long)ahnd); > > > > + igt_map_remove(ahnd_map, &ahnd, map_entry_free_func); > > > > + } > > > > + pthread_mutex_unlock(&ahnd_map_mutex); > > > > +} > > > > + > > > > static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > > > > uint32_t vm, > > > > uint64_t start, uint64_t end, > > > > @@ -895,6 +973,12 @@ static uint64_t __intel_allocator_open_full(int fd, uint32_t ctx, > > > > igt_assert(resp.open.allocator_handle); > > > > igt_assert(resp.response_type == RESP_OPEN); > > > > + /* > > > > + * Igts mostly uses ctx as id when opening the allocator (i915 legacy). > > > > + * If ctx is passed let's use it as an vm id, otherwise use vm. > > > > + */ > > > > + track_ahnd(fd, resp.open.allocator_handle, ctx ?: vm); > > > > + > > > > return resp.open.allocator_handle; > > > > } > > > > @@ -1001,6 +1085,8 @@ bool intel_allocator_close(uint64_t allocator_handle) > > > > igt_assert(handle_request(&req, &resp) == 0); > > > > igt_assert(resp.response_type == RESP_CLOSE); > > > > + untrack_ahnd(allocator_handle); > > > > + > > > > return resp.close.is_empty; > > > > } > > > > @@ -1034,6 +1120,74 @@ void intel_allocator_get_address_range(uint64_t allocator_handle, > > > > *endp = resp.address_range.end; > > > > } > > > > +static bool is_same(struct allocator_object *obj, > > > > + uint32_t handle, uint64_t offset, uint64_t size, > > > > + enum allocator_bind_op bind_op) > > > > +{ > > > > + return obj->handle == handle && obj->offset == offset && obj->size == size && > > > > + (obj->bind_op == bind_op || obj->bind_op == BOUND); > > > > +} > > > > + > > > > +static void track_object(uint64_t allocator_handle, uint32_t handle, > > > > + uint64_t offset, uint64_t size, > > > > + enum allocator_bind_op bind_op) > > > > +{ > > > > + struct ahnd_info *ainfo; > > > > + struct allocator_object *obj; > > > > + > > > > + bind_debug("[TRACK OBJECT]: [%s] pid: %d, tid: %d, ahnd: %llx, handle: %u, offset: %llx, size: %llx\n", > > > > + bind_op == TO_BIND ? "BIND" : "UNBIND", > > > > + getpid(), gettid(), > > > > + (long long)allocator_handle, > > > > + handle, (long long)offset, (long long)size); > > > > + > > > > + if (offset == ALLOC_INVALID_ADDRESS) { > > > > + bind_debug("[TRACK OBJECT] => invalid address %llx, skipping tracking\n", > > > > + (long long)offset); > > > > + return; > > > > + } > > > > + > > > > + pthread_mutex_lock(&ahnd_map_mutex); > > > > + ainfo = igt_map_search(ahnd_map, &allocator_handle); > > > > + pthread_mutex_unlock(&ahnd_map_mutex); > > > > + igt_assert_f(ainfo, "[TRACK OBJECT] => MISSING ahnd %llx <=\n", > > > > + (long long)allocator_handle); > > > > + > > > > + if (ainfo->driver == INTEL_DRIVER_I915) > > > > + return; /* no-op for i915, at least for now */ > > > > + > > > > + pthread_mutex_lock(&ainfo->bind_map_mutex); > > > > + obj = igt_map_search(ainfo->bind_map, &handle); > > > > + if (obj) { > > > > + /* > > > > + * User may call alloc() couple of times, check object is the > > > > + * same. For free() there's simple case, just remove from > > > > + * bind_map. > > > > + */ > > > > + if (bind_op == TO_BIND) { > > > > + igt_assert_eq(is_same(obj, handle, offset, size, bind_op), true); > > > > + } else if (bind_op == TO_UNBIND) { > > > > + if (obj->bind_op == TO_BIND) > > > > + igt_map_remove(ainfo->bind_map, &obj->handle, map_entry_free_func); > > > > + else if (obj->bind_op == BOUND) > > > > + obj->bind_op = bind_op; > > > > + } > > > > + } else { > > > > + /* Ignore to unbind bo which wasn't previously inserted */ > > > > + if (bind_op == TO_UNBIND) > > > > + goto out; > > > > + > > > > + obj = calloc(1, sizeof(*obj)); > > > > + obj->handle = handle; > > > > + obj->offset = offset; > > > > + obj->size = size; > > > > + obj->bind_op = bind_op; > > > > + igt_map_insert(ainfo->bind_map, &obj->handle, obj); > > > > + } > > > > +out: > > > > + pthread_mutex_unlock(&ainfo->bind_map_mutex); > > > > +} > > > > + > > > > /** > > > > * __intel_allocator_alloc: > > > > * @allocator_handle: handle to an allocator > > > > @@ -1065,6 +1219,8 @@ uint64_t __intel_allocator_alloc(uint64_t allocator_handle, uint32_t handle, > > > > igt_assert(handle_request(&req, &resp) == 0); > > > > igt_assert(resp.response_type == RESP_ALLOC); > > > > + track_object(allocator_handle, handle, resp.alloc.offset, size, TO_BIND); > > > > + > > > > return resp.alloc.offset; > > > > } > > > > @@ -1142,6 +1298,8 @@ bool intel_allocator_free(uint64_t allocator_handle, uint32_t handle) > > > > igt_assert(handle_request(&req, &resp) == 0); > > > > igt_assert(resp.response_type == RESP_FREE); > > > > + track_object(allocator_handle, handle, 0, 0, TO_UNBIND); > > > > + > > > > return resp.free.freed; > > > > } > > > > @@ -1326,6 +1484,84 @@ void intel_allocator_print(uint64_t allocator_handle) > > > > } > > > > } > > > > +static void __xe_op_bind(struct ahnd_info *ainfo, uint32_t sync_in, uint32_t sync_out) > > > > +{ > > > > + struct allocator_object *obj; > > > > + struct igt_map_entry *pos; > > > > + struct igt_list_head obj_list; > > > > + struct xe_object *entry, *tmp; > > > > + > > > > + IGT_INIT_LIST_HEAD(&obj_list); > > > > + > > > > + pthread_mutex_lock(&ainfo->bind_map_mutex); > > > > + igt_map_foreach(ainfo->bind_map, pos) { > > > > + obj = pos->data; > > > > + > > > > + if (obj->bind_op == BOUND) > > > > + continue; > > > > + > > > > + bind_info("= [vm: %u] %s => %u %lx %lx\n", > > > > + ainfo->vm, > > > > + obj->bind_op == TO_BIND ? "TO BIND" : "TO UNBIND", > > > > + obj->handle, obj->offset, > > > > + obj->size); > > > > + > > > > + entry = malloc(sizeof(*entry)); > > > > + entry->handle = obj->handle; > > > > + entry->offset = obj->offset; > > > > + entry->size = obj->size; > > > > + entry->bind_op = obj->bind_op == TO_BIND ? XE_OBJECT_BIND : > > > > + XE_OBJECT_UNBIND; > > > > + igt_list_add(&entry->link, &obj_list); > > > > + > > > > + /* > > > > + * We clean bind_map even before calling bind/unbind > > > > + * as all binding operations asserts in case of error. > > > > + */ > > > > + if (obj->bind_op == TO_BIND) > > > > + obj->bind_op = BOUND; > > > > + else > > > > + igt_map_remove(ainfo->bind_map, &obj->handle, > > > > + map_entry_free_func); > > > > > > I don't quite understand why we can clean up the map even before the actual > > > bind/unbind happens. If an assert fails, it means that vm_(un)bind failed, > > > so the actual operation didn't succeed, and that state change is incorrect. > > > I believe that there's a reason we can do it this way, I just don't > > > understand it. > > > > I allocate separate list of xe_objects which is an argument to > > xe_bind_unbind_async(). As list is detached (separate) from the bind_map > > I may apriori do cleanup in the map. If bind/unbind is unsuccessful > > outdated bind_map is the smallest problem here. > > I'm aware they are separate entities, I just wonder what is the benefit of > doing it here. Are there any dangers of removing that binding before it's > actually unbound? Benefit is that I don't need to track xe_object -> allocator_object or keep backward reference to update the bind_map. Unsuccessful bind/unbind asserts and what the bind_map contains doesn't matter. We enter failure path so igt core is cleaning up preparing to run next subtest. >From my perspective if user is properly handling offsets and calls intel_allocator_bind() before the exec operation no assert can occur. I did profound test in api_intel_allocator@two-level-inception adding vm for xe and binding/unbinding calling intel_allocator_bind(). For RELOC stress test worked properly (there's no risk of reusing offset returned to the pool by other child/thread). For SIMPLE we may encounter situation where one offset is returned in some child/thread, unbind didn't happened yet, another child/thread allocated getting same offset so binding it will fail (vm still has unbounded offset). As RELOC doesn't reuse same offset (until wrapping around) no risk of overlapping occurs (almost ;). Anyway - it is possible to extend the allocator to be more "transactional" and aware what offsets are still not unbounded but I decided to not add this (at least) now. Especially for RELOC (mostly used) it doesn't add too much value. And for SIMPLE it requires deferred releasing after unbind is complete (what is also problematic if you want to allow user to pass its own syncobjs). -- Zbigniew > > All the best, > Karolina > > > On assert path igt_fail() > > calls intel_allocator_init() which just frees contents on ahnd_map[]->bind_map. > > In children there's simpler because they just dies. Real problem is we > > still have dangling vm (no xe_vm_destroy()). > > So I decided to update the bind_map before calling bind/unbind as on failure > > doesn't matter what it will contain. > > > > -- > > Zbigniew > > > > > > > > Apart from that one thing, the patch looks good to me. > > > > > > All the best, > > > Karolina > > > > > > > + } > > > > + pthread_mutex_unlock(&ainfo->bind_map_mutex); > > > > + > > > > + xe_bind_unbind_async(ainfo->fd, ainfo->vm, 0, &obj_list, sync_in, sync_out); > > > > + > > > > + igt_list_for_each_entry_safe(entry, tmp, &obj_list, link) { > > > > + igt_list_del(&entry->link); > > > > + free(entry); > > > > + } > > > > +} > > > > + > > > > +/** > > > > + * intel_allocator_bind: > > > > + * @allocator_handle: handle to an allocator > > > > + * @sync_in: syncobj (fence-in) > > > > + * @sync_out: syncobj (fence-out) > > > > + * > > > > + * Function binds and unbinds all objects added to the allocator which weren't > > > > + * previously binded/unbinded. > > > > + * > > > > + **/ > > > > +void intel_allocator_bind(uint64_t allocator_handle, > > > > + uint32_t sync_in, uint32_t sync_out) > > > > +{ > > > > + struct ahnd_info *ainfo; > > > > + > > > > + pthread_mutex_lock(&ahnd_map_mutex); > > > > + ainfo = igt_map_search(ahnd_map, &allocator_handle); > > > > + pthread_mutex_unlock(&ahnd_map_mutex); > > > > + igt_assert(ainfo); > > > > + > > > > + /* > > > > + * We collect bind/unbind operations on alloc()/free() to do group > > > > + * operation getting @sync_in as syncobj handle (fence-in). If user > > > > + * passes 0 as @sync_out we bind/unbind synchronously. > > > > + */ > > > > + __xe_op_bind(ainfo, sync_in, sync_out); > > > > +} > > > > + > > > > static int equal_handles(const void *key1, const void *key2) > > > > { > > > > const struct handle_entry *h1 = key1, *h2 = key2; > > > > @@ -1383,6 +1619,22 @@ static void __free_maps(struct igt_map *map, bool close_allocators) > > > > igt_map_destroy(map, map_entry_free_func); > > > > } > > > > +static void __free_ahnd_map(void) > > > > +{ > > > > + struct igt_map_entry *pos; > > > > + struct ahnd_info *ainfo; > > > > + > > > > + if (!ahnd_map) > > > > + return; > > > > + > > > > + igt_map_foreach(ahnd_map, pos) { > > > > + ainfo = pos->data; > > > > + igt_map_destroy(ainfo->bind_map, map_entry_free_func); > > > > + } > > > > + > > > > + igt_map_destroy(ahnd_map, map_entry_free_func); > > > > +} > > > > + > > > > /** > > > > * intel_allocator_init: > > > > * > > > > @@ -1400,12 +1652,15 @@ void intel_allocator_init(void) > > > > __free_maps(handles, true); > > > > __free_maps(ctx_map, false); > > > > __free_maps(vm_map, false); > > > > + __free_ahnd_map(); > > > > atomic_init(&next_handle, 1); > > > > handles = igt_map_create(hash_handles, equal_handles); > > > > ctx_map = igt_map_create(hash_instance, equal_ctx); > > > > vm_map = igt_map_create(hash_instance, equal_vm); > > > > - igt_assert(handles && ctx_map && vm_map); > > > > + pthread_mutex_init(&ahnd_map_mutex, NULL); > > > > + ahnd_map = igt_map_create(igt_map_hash_64, igt_map_equal_64); > > > > + igt_assert(handles && ctx_map && vm_map && ahnd_map); > > > > channel = intel_allocator_get_msgchannel(CHANNEL_SYSVIPC_MSGQUEUE); > > > > } > > > > diff --git a/lib/intel_allocator.h b/lib/intel_allocator.h > > > > index 3ec74f6191..f9ff7f1cc9 100644 > > > > --- a/lib/intel_allocator.h > > > > +++ b/lib/intel_allocator.h > > > > @@ -210,6 +210,9 @@ bool intel_allocator_reserve_if_not_allocated(uint64_t allocator_handle, > > > > void intel_allocator_print(uint64_t allocator_handle); > > > > +void intel_allocator_bind(uint64_t allocator_handle, > > > > + uint32_t sync_in, uint32_t sync_out); > > > > + > > > > #define ALLOC_INVALID_ADDRESS (-1ull) > > > > #define INTEL_ALLOCATOR_NONE 0 > > > > #define INTEL_ALLOCATOR_RELOC 1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 97B0610E599 for ; Wed, 12 Jul 2023 17:08:05 +0000 (UTC) Date: Wed, 12 Jul 2023 19:05:00 +0200 From: Zbigniew =?utf-8?Q?Kempczy=C5=84ski?= To: Karolina Stolarek Message-ID: <20230712170500.igoh3elboazqenfy@zkempczy-mobl2> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <20230711112009.122482-16-zbigniew.kempczynski@intel.com> <68097bdb-c02e-a669-bd29-8b9d796b9439@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <68097bdb-c02e-a669-bd29-8b9d796b9439@intel.com> Subject: Re: [igt-dev] [PATCH i-g-t v3 15/17] tests/xe_exercise_blt: Check blitter library fast-copy for Xe List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On Wed, Jul 12, 2023 at 12:18:23PM +0200, Karolina Stolarek wrote: > On 11.07.2023 13:20, Zbigniew Kempczyński wrote: > > Port this test to work on xe. Instead of adding conditional code for > > xe code which would decrease readability this is new test for xe. > > > > Signed-off-by: Zbigniew Kempczyński > > --- > > v3: - Explicitely release offsets and unbind (Karolina) > > - Use has-fast-copy instead of copied has-block-copy check (Karolina) > > --- > > tests/meson.build | 1 + > > tests/xe/xe_exercise_blt.c | 377 +++++++++++++++++++++++++++++++++++++ > > 2 files changed, 378 insertions(+) > > create mode 100644 tests/xe/xe_exercise_blt.c > > > > diff --git a/tests/meson.build b/tests/meson.build > > index da8653fabc..3eddb2fb4e 100644 > > --- a/tests/meson.build > > +++ b/tests/meson.build > > @@ -276,6 +276,7 @@ xe_progs = [ > > 'xe_exec_reset', > > 'xe_exec_store', > > 'xe_exec_threads', > > + 'xe_exercise_blt', > > 'xe_gpgpu_fill', > > 'xe_guc_pc', > > 'xe_huc_copy', > > diff --git a/tests/xe/xe_exercise_blt.c b/tests/xe/xe_exercise_blt.c > > new file mode 100644 > > index 0000000000..693e80d0b7 > > --- /dev/null > > +++ b/tests/xe/xe_exercise_blt.c > > @@ -0,0 +1,377 @@ > > +// SPDX-License-Identifier: MIT > > +/* > > + * Copyright © 2023 Intel Corporation > > + */ > > + > > +#include "igt.h" > > +#include "drm.h" > > +#include "lib/intel_chipset.h" > > +#include "intel_blt.h" > > +#include "intel_mocs.h" > > +#include "xe/xe_ioctl.h" > > +#include "xe/xe_query.h" > > +#include "xe/xe_util.h" > > + > > +/** > > + * TEST: xe exercise blt > > + * Description: Exercise blitter commands on Xe > > + * Feature: blitter > > + * Run type: FULL > > + * Test category: GEM_Legacy > > + * > > + * SUBTEST: fast-copy > > + * Description: > > + * Check fast-copy blit > > + * blitter > > + * > > + * SUBTEST: fast-copy-emit > > + * Description: > > + * Check multiple fast-copy in one batch > > + * blitter > > + */ > > + > > +IGT_TEST_DESCRIPTION("Exercise blitter commands on Xe"); > > + > > +static struct param { > > + int tiling; > > + bool write_png; > > + bool print_bb; > > + bool print_surface_info; > > + int width; > > + int height; > > +} param = { > > + .tiling = -1, > > + .write_png = false, > > + .print_bb = false, > > + .print_surface_info = false, > > + .width = 512, > > + .height = 512, > > +}; > > + > > +#define PRINT_SURFACE_INFO(name, obj) do { \ > > + if (param.print_surface_info) \ > > + blt_surface_info((name), (obj)); } while (0) > > + > > +#define WRITE_PNG(fd, id, name, obj, w, h) do { \ > > + if (param.write_png) \ > > + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0) > > + > > +struct blt_fast_copy_data { > > + int xe; > > + struct blt_copy_object src; > > + struct blt_copy_object mid; > > + struct blt_copy_object dst; > > + > > + struct blt_copy_batch bb; > > + enum blt_color_depth color_depth; > > + > > + /* debug stuff */ > > + bool print_bb; > > +}; > > + > > +static int fast_copy_one_bb(int xe, > > + const intel_ctx_t *ctx, > > + uint64_t ahnd, > > + const struct blt_fast_copy_data *blt) > > +{ > > + struct blt_copy_data blt_tmp; > > + uint64_t bb_offset, alignment; > > + uint64_t bb_pos = 0; > > + int ret = 0; > > + > > + alignment = xe_get_default_alignment(xe); > > + > > + get_offset(ahnd, blt->src.handle, blt->src.size, alignment); > > + get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment); > > + get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment); > > + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment); > > + > > + /* First blit */ > > + blt_copy_init(xe, &blt_tmp); > > + blt_tmp.src = blt->src; > > + blt_tmp.dst = blt->mid; > > + blt_tmp.bb = blt->bb; > > + blt_tmp.color_depth = blt->color_depth; > > + blt_tmp.print_bb = blt->print_bb; > > + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, false); > > + > > + /* Second blit */ > > + blt_copy_init(xe, &blt_tmp); > > + blt_tmp.src = blt->mid; > > + blt_tmp.dst = blt->dst; > > + blt_tmp.bb = blt->bb; > > + blt_tmp.color_depth = blt->color_depth; > > + blt_tmp.print_bb = blt->print_bb; > > + bb_pos = emit_blt_fast_copy(xe, ahnd, &blt_tmp, bb_pos, true); > > + > > + intel_ctx_xe_exec(ctx, ahnd, bb_offset); > > + > > + return ret; > > +} > > + > > +static void fast_copy_emit(int xe, const intel_ctx_t *ctx, > > + uint32_t region1, uint32_t region2, > > + enum blt_tiling_type mid_tiling) > > +{ > > + struct blt_copy_data bltinit = {}; > > + struct blt_fast_copy_data blt = {}; > > + struct blt_copy_object *src, *mid, *dst; > > + const uint32_t bpp = 32; > > + uint64_t bb_size = xe_get_default_alignment(xe); > > + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0, > > + INTEL_ALLOCATOR_SIMPLE, > > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > > + uint32_t bb, width = param.width, height = param.height; > > + int result; > > + > > + bb = xe_bo_create_flags(xe, 0, bb_size, region1); > > + > > + blt_copy_init(xe, &bltinit); > > + src = blt_create_object(&bltinit, region1, width, height, bpp, 0, > > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > > + mid = blt_create_object(&bltinit, region2, width, height, bpp, 0, > > + mid_tiling, COMPRESSION_DISABLED, 0, true); > > + dst = blt_create_object(&bltinit, region1, width, height, bpp, 0, > > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > > + igt_assert(src->size == dst->size); > > + > > + PRINT_SURFACE_INFO("src", src); > > + PRINT_SURFACE_INFO("mid", mid); > > + PRINT_SURFACE_INFO("dst", dst); > > + > > + blt_surface_fill_rect(xe, src, width, height); > > + WRITE_PNG(xe, mid_tiling, "src", src, width, height); > > + > > + memset(&blt, 0, sizeof(blt)); > > Could we use blt_copy_init() here? > No :) That's you local structure incompatibile with blt_copy_data. -- Zbigniew > Thanks, > Karolina > > > + blt.color_depth = CD_32bit; > > + blt.print_bb = param.print_bb; > > + blt_set_copy_object(&blt.src, src); > > + blt_set_copy_object(&blt.mid, mid); > > + blt_set_copy_object(&blt.dst, dst); > > + blt_set_batch(&blt.bb, bb, bb_size, region1); > > + > > + fast_copy_one_bb(xe, ctx, ahnd, &blt); > > + > > + WRITE_PNG(xe, mid_tiling, "mid", &blt.mid, width, height); > > + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height); > > + > > + result = memcmp(src->ptr, blt.dst.ptr, src->size); > > + > > + blt_destroy_object(xe, src); > > + blt_destroy_object(xe, mid); > > + blt_destroy_object(xe, dst); > > + gem_close(xe, bb); > > + put_ahnd(ahnd); > > + > > + munmap(&bb, bb_size); > > + > > + igt_assert_f(!result, "source and destination surfaces differs!\n"); > > +} > > + > > +static void fast_copy(int xe, const intel_ctx_t *ctx, > > + uint32_t region1, uint32_t region2, > > + enum blt_tiling_type mid_tiling) > > +{ > > + struct blt_copy_data blt = {}; > > + struct blt_copy_object *src, *mid, *dst; > > + const uint32_t bpp = 32; > > + uint64_t bb_size = xe_get_default_alignment(xe); > > + uint64_t ahnd = intel_allocator_open_full(xe, ctx->vm, 0, 0, > > + INTEL_ALLOCATOR_SIMPLE, > > + ALLOC_STRATEGY_LOW_TO_HIGH, 0); > > + uint32_t bb; > > + uint32_t width = param.width, height = param.height; > > + int result; > > + > > + bb = xe_bo_create_flags(xe, 0, bb_size, region1); > > + > > + blt_copy_init(xe, &blt); > > + src = blt_create_object(&blt, region1, width, height, bpp, 0, > > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > > + mid = blt_create_object(&blt, region2, width, height, bpp, 0, > > + mid_tiling, COMPRESSION_DISABLED, 0, true); > > + dst = blt_create_object(&blt, region1, width, height, bpp, 0, > > + T_LINEAR, COMPRESSION_DISABLED, 0, true); > > + igt_assert(src->size == dst->size); > > + > > + blt_surface_fill_rect(xe, src, width, height); > > + > > + blt.color_depth = CD_32bit; > > + blt.print_bb = param.print_bb; > > + blt_set_copy_object(&blt.src, src); > > + blt_set_copy_object(&blt.dst, mid); > > + blt_set_batch(&blt.bb, bb, bb_size, region1); > > + > > + blt_fast_copy(xe, ctx, NULL, ahnd, &blt); > > + > > + WRITE_PNG(xe, mid_tiling, "src", &blt.src, width, height); > > + WRITE_PNG(xe, mid_tiling, "mid", &blt.dst, width, height); > > + > > + blt_copy_init(xe, &blt); > > + blt.color_depth = CD_32bit; > > + blt.print_bb = param.print_bb; > > + blt_set_copy_object(&blt.src, mid); > > + blt_set_copy_object(&blt.dst, dst); > > + blt_set_batch(&blt.bb, bb, bb_size, region1); > > + > > + blt_fast_copy(xe, ctx, NULL, ahnd, &blt); > > + > > + WRITE_PNG(xe, mid_tiling, "dst", &blt.dst, width, height); > > + > > + result = memcmp(src->ptr, blt.dst.ptr, src->size); > > + > > + put_offset(ahnd, src->handle); > > + put_offset(ahnd, mid->handle); > > + put_offset(ahnd, dst->handle); > > + put_offset(ahnd, bb); > > + intel_allocator_bind(ahnd, 0, 0); > > + blt_destroy_object(xe, src); > > + blt_destroy_object(xe, mid); > > + blt_destroy_object(xe, dst); > > + gem_close(xe, bb); > > + put_ahnd(ahnd); > > + > > + igt_assert_f(!result, "source and destination surfaces differs!\n"); > > +} > > + > > +enum fast_copy_func { > > + FAST_COPY, > > + FAST_COPY_EMIT > > +}; > > + > > +static char > > + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling, > > + enum fast_copy_func func) > > +{ > > + char *name; > > + uint32_t len; > > + > > + len = asprintf(&name, "%s-%s%s", blt_tiling_name(tiling), regtxt, > > + func == FAST_COPY_EMIT ? "-emit" : ""); > > + > > + igt_assert_f(len >= 0, "asprintf failed!\n"); > > + > > + return name; > > +} > > + > > +static void fast_copy_test(int xe, > > + struct igt_collection *set, > > + enum fast_copy_func func) > > +{ > > + struct drm_xe_engine_class_instance inst = { > > + .engine_class = DRM_XE_ENGINE_CLASS_COPY, > > + }; > > + struct igt_collection *regions; > > + void (*copy_func)(int xe, const intel_ctx_t *ctx, > > + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling); > > + intel_ctx_t *ctx; > > + int tiling; > > + > > + for_each_tiling(tiling) { > > + if (!blt_fast_copy_supports_tiling(xe, tiling)) > > + continue; > > + > > + for_each_variation_r(regions, 2, set) { > > + uint32_t region1, region2; > > + uint32_t vm, engine; > > + char *regtxt, *test_name; > > + > > + region1 = igt_collection_get_value(regions, 0); > > + region2 = igt_collection_get_value(regions, 1); > > + > > + vm = xe_vm_create(xe, DRM_XE_VM_CREATE_ASYNC_BIND_OPS, 0); > > + engine = xe_engine_create(xe, vm, &inst, 0); > > + ctx = intel_ctx_xe(xe, vm, engine, 0, 0, 0); > > + > > + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit; > > + regtxt = xe_memregion_dynamic_subtest_name(xe, regions); > > + test_name = full_subtest_str(regtxt, tiling, func); > > + > > + igt_dynamic_f("%s", test_name) { > > + copy_func(xe, ctx, > > + region1, region2, > > + tiling); > > + } > > + > > + free(regtxt); > > + free(test_name); > > + xe_engine_destroy(xe, engine); > > + xe_vm_destroy(xe, vm); > > + free(ctx); > > + } > > + } > > +} > > + > > +static int opt_handler(int opt, int opt_index, void *data) > > +{ > > + switch (opt) { > > + case 'b': > > + param.print_bb = true; > > + igt_debug("Print bb: %d\n", param.print_bb); > > + break; > > + case 'p': > > + param.write_png = true; > > + igt_debug("Write png: %d\n", param.write_png); > > + break; > > + case 's': > > + param.print_surface_info = true; > > + igt_debug("Print surface info: %d\n", param.print_surface_info); > > + break; > > + case 't': > > + param.tiling = atoi(optarg); > > + igt_debug("Tiling: %d\n", param.tiling); > > + break; > > + case 'W': > > + param.width = atoi(optarg); > > + igt_debug("Width: %d\n", param.width); > > + break; > > + case 'H': > > + param.height = atoi(optarg); > > + igt_debug("Height: %d\n", param.height); > > + break; > > + default: > > + return IGT_OPT_HANDLER_ERROR; > > + } > > + > > + return IGT_OPT_HANDLER_SUCCESS; > > +} > > + > > +const char *help_str = > > + " -b\tPrint bb\n" > > + " -p\tWrite PNG\n" > > + " -s\tPrint surface info\n" > > + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n" > > + " -W\tWidth (default 512)\n" > > + " -H\tHeight (default 512)" > > + ; > > + > > +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL) > > +{ > > + struct igt_collection *set; > > + int xe; > > + > > + igt_fixture { > > + xe = drm_open_driver(DRIVER_XE); > > + igt_require(blt_has_fast_copy(xe)); > > + > > + xe_device_get(xe); > > + > > + set = xe_get_memory_region_set(xe, > > + XE_MEM_REGION_CLASS_SYSMEM, > > + XE_MEM_REGION_CLASS_VRAM); > > + } > > + > > + igt_describe("Check fast-copy blit"); > > + igt_subtest_with_dynamic("fast-copy") { > > + fast_copy_test(xe, set, FAST_COPY); > > + } > > + > > + igt_describe("Check multiple fast-copy in one batch"); > > + igt_subtest_with_dynamic("fast-copy-emit") { > > + fast_copy_test(xe, set, FAST_COPY_EMIT); > > + } > > + > > + igt_fixture { > > + drm_close_driver(xe); > > + } > > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Content-Type: multipart/alternative; boundary="===============3786772691755864516==" MIME-Version: 1.0 From: Patchwork To: =?utf-8?q?Zbigniew_Kempczy=C5=84ski?= Date: Fri, 14 Jul 2023 04:48:28 -0000 Message-ID: <168931010825.13877.3427584235221570994@emeril.freedesktop.org> References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> In-Reply-To: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> Subject: [igt-dev] =?utf-8?b?4pyTIEZpLkNJLklHVDogc3VjY2VzcyBmb3IgRXh0ZW5k?= =?utf-8?q?_intel=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: igt-dev@lists.freedesktop.org Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: --===============3786772691755864516== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit == Series Details == Series: Extend intel_blt to work on Xe (rev3) URL : https://patchwork.freedesktop.org/series/120162/ State : success == Summary == CI Bug Log - changes from CI_DRM_13369_full -> IGTPW_9383_full ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html Participating hosts (9 -> 9) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in IGTPW_9383_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@api_intel_bb@crc32: - shard-tglu: NOTRUN -> [SKIP][1] ([i915#6230]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@api_intel_bb@crc32.html * igt@device_reset@unbind-cold-reset-rebind: - shard-rkl: NOTRUN -> [SKIP][2] ([i915#7701]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@device_reset@unbind-cold-reset-rebind.html - shard-dg2: NOTRUN -> [SKIP][3] ([i915#7701]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@device_reset@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-hang@bcs0: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +19 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@drm_fdinfo@busy-hang@bcs0.html * igt@drm_fdinfo@most-busy-idle-check-all@rcs0: - shard-rkl: [PASS][5] -> [FAIL][6] ([i915#7742]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@drm_fdinfo@virtual-busy-all.html * igt@gem_bad_reloc@negative-reloc-bltcopy: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#3281]) +5 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@gem_bad_reloc@negative-reloc-bltcopy.html * igt@gem_basic@multigpu-create-close: - shard-rkl: NOTRUN -> [SKIP][9] ([i915#7697]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@gem_basic@multigpu-create-close.html * igt@gem_ccs@block-copy-compressed: - shard-tglu: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#5325]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@gem_ccs@block-copy-compressed.html * igt@gem_ccs@ctrl-surf-copy-new-ctx: - shard-mtlp: NOTRUN -> [SKIP][11] ([i915#5325]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@gem_ccs@ctrl-surf-copy-new-ctx.html * igt@gem_close_race@multigpu-basic-process: - shard-dg2: NOTRUN -> [SKIP][12] ([i915#7697]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@gem_close_race@multigpu-basic-process.html * igt@gem_create@create-ext-cpu-access-big: - shard-tglu: NOTRUN -> [SKIP][13] ([i915#6335]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@gem_create@create-ext-cpu-access-big.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][14] -> [FAIL][15] ([i915#6268]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_ctx_param@set-priority-not-supported: - shard-dg2: NOTRUN -> [SKIP][16] ([fdo#109314]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-11/igt@gem_ctx_param@set-priority-not-supported.html - shard-rkl: NOTRUN -> [SKIP][17] ([fdo#109314]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@gem_ctx_param@set-priority-not-supported.html * igt@gem_ctx_persistence@saturated-hostile@vecs0: - shard-mtlp: [PASS][18] -> [FAIL][19] ([i915#7816]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@gem_ctx_persistence@saturated-hostile@vecs0.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@gem_ctx_persistence@saturated-hostile@vecs0.html * igt@gem_eio@in-flight-contexts-1us: - shard-mtlp: [PASS][20] -> [ABORT][21] ([i915#8503]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@gem_eio@in-flight-contexts-1us.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@gem_eio@in-flight-contexts-1us.html * igt@gem_eio@kms: - shard-dg2: [PASS][22] -> [INCOMPLETE][23] ([i915#7892]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-8/igt@gem_eio@kms.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@gem_eio@kms.html * igt@gem_exec_balancer@bonded-true-hang: - shard-dg2: NOTRUN -> [SKIP][24] ([i915#4812]) +2 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@gem_exec_balancer@bonded-true-hang.html * igt@gem_exec_fair@basic-none@bcs0: - shard-tglu: NOTRUN -> [FAIL][25] ([i915#2842]) +4 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@gem_exec_fair@basic-none@bcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-glk: [PASS][26] -> [FAIL][27] ([i915#2842]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk7/igt@gem_exec_fair@basic-pace@vcs0.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-throttle: - shard-dg2: NOTRUN -> [SKIP][28] ([i915#3539]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-2/igt@gem_exec_fair@basic-throttle.html * igt@gem_exec_fence@submit67: - shard-mtlp: NOTRUN -> [SKIP][29] ([i915#4812]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_exec_fence@submit67.html * igt@gem_exec_params@secure-non-root: - shard-tglu: NOTRUN -> [SKIP][30] ([fdo#112283]) [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@gem_exec_params@secure-non-root.html * igt@gem_exec_reloc@basic-write-gtt-active: - shard-dg2: NOTRUN -> [SKIP][31] ([i915#3281]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@gem_exec_reloc@basic-write-gtt-active.html - shard-rkl: NOTRUN -> [SKIP][32] ([i915#3281]) +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@gem_exec_reloc@basic-write-gtt-active.html * igt@gem_exec_whisper@basic-forked: - shard-mtlp: NOTRUN -> [FAIL][33] ([i915#6363]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@gem_exec_whisper@basic-forked.html * igt@gem_exec_whisper@basic-forked-all: - shard-mtlp: [PASS][34] -> [FAIL][35] ([i915#6363]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@gem_exec_whisper@basic-forked-all.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@gem_exec_whisper@basic-forked-all.html * igt@gem_lmem_swapping@heavy-verify-random-ccs: - shard-tglu: NOTRUN -> [SKIP][36] ([i915#4613]) +2 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@gem_lmem_swapping@heavy-verify-random-ccs.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#4613]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl1/igt@gem_lmem_swapping@parallel-multi.html * igt@gem_lmem_swapping@parallel-random: - shard-mtlp: NOTRUN -> [SKIP][38] ([i915#4613]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@gem_lmem_swapping@parallel-random.html * igt@gem_lmem_swapping@smem-oom@lmem0: - shard-dg2: [PASS][39] -> [TIMEOUT][40] ([i915#5493]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@gem_media_vme: - shard-tglu: NOTRUN -> [SKIP][41] ([i915#284]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@gem_media_vme.html * igt@gem_mmap_wc@write: - shard-mtlp: NOTRUN -> [SKIP][42] ([i915#4083]) +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@gem_mmap_wc@write.html - shard-dg2: NOTRUN -> [SKIP][43] ([i915#4083]) +3 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@gem_mmap_wc@write.html * igt@gem_partial_pwrite_pread@reads: - shard-mtlp: NOTRUN -> [SKIP][44] ([i915#3282]) +3 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_partial_pwrite_pread@reads.html * igt@gem_partial_pwrite_pread@writes-after-reads: - shard-rkl: NOTRUN -> [SKIP][45] ([i915#3282]) +2 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@gem_partial_pwrite_pread@writes-after-reads.html * igt@gem_pxp@create-regular-buffer: - shard-mtlp: NOTRUN -> [SKIP][46] ([i915#4270]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@gem_pxp@create-regular-buffer.html * igt@gem_pxp@fail-invalid-protected-context: - shard-tglu: NOTRUN -> [SKIP][47] ([i915#4270]) +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@gem_pxp@fail-invalid-protected-context.html * igt@gem_readwrite@beyond-eob: - shard-dg2: NOTRUN -> [SKIP][48] ([i915#3282]) +3 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@gem_readwrite@beyond-eob.html * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs: - shard-mtlp: NOTRUN -> [SKIP][49] ([i915#8428]) +3 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html * igt@gem_set_tiling_vs_pwrite: - shard-dg2: NOTRUN -> [SKIP][50] ([i915#4079]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@gem_set_tiling_vs_pwrite.html * igt@gem_tiled_fence_blits@basic: - shard-dg2: NOTRUN -> [SKIP][51] ([i915#4077]) +3 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@gem_tiled_fence_blits@basic.html * igt@gem_tiled_pread_basic: - shard-mtlp: NOTRUN -> [SKIP][52] ([i915#4079]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@gem_tiled_pread_basic.html * igt@gem_userptr_blits@coherency-unsync: - shard-mtlp: NOTRUN -> [SKIP][53] ([i915#3297]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_userptr_blits@coherency-unsync.html * igt@gem_userptr_blits@invalid-mmap-offset-unsync: - shard-dg2: NOTRUN -> [SKIP][54] ([i915#3297]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html - shard-rkl: NOTRUN -> [SKIP][55] ([i915#3297]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy: - shard-dg2: NOTRUN -> [SKIP][56] ([i915#3297] / [i915#4880]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html * igt@gem_userptr_blits@nohangcheck: - shard-mtlp: [PASS][57] -> [FAIL][58] ([i915#7916]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@gem_userptr_blits@nohangcheck.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@gem_userptr_blits@nohangcheck.html * igt@gen7_exec_parse@load-register-reg: - shard-dg2: NOTRUN -> [SKIP][59] ([fdo#109289]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@gen7_exec_parse@load-register-reg.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-mtlp: NOTRUN -> [SKIP][60] ([fdo#109289]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@gen7_exec_parse@oacontrol-tracking.html * igt@gen9_exec_parse@bb-large: - shard-dg2: NOTRUN -> [SKIP][61] ([i915#2856]) [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@gen9_exec_parse@bb-large.html - shard-rkl: NOTRUN -> [SKIP][62] ([i915#2527]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@gen9_exec_parse@bb-large.html * igt@i915_hangman@gt-engine-error@vcs0: - shard-mtlp: [PASS][63] -> [FAIL][64] ([i915#7069]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@i915_hangman@gt-engine-error@vcs0.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@i915_hangman@gt-engine-error@vcs0.html * igt@i915_module_load@load: - shard-rkl: NOTRUN -> [SKIP][65] ([i915#6227]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@i915_module_load@load.html * igt@i915_pm_backlight@bad-brightness: - shard-dg2: NOTRUN -> [SKIP][66] ([i915#5354] / [i915#7561]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@i915_pm_backlight@bad-brightness.html * igt@i915_pm_dc@dc5-psr: - shard-tglu: NOTRUN -> [SKIP][67] ([i915#658]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-3/igt@i915_pm_dc@dc5-psr.html * igt@i915_pm_dc@dc9-dpms: - shard-apl: [PASS][68] -> [SKIP][69] ([fdo#109271]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl3/igt@i915_pm_dc@dc9-dpms.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl7/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_lpsp@screens-disabled: - shard-mtlp: NOTRUN -> [SKIP][70] ([i915#8430]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@i915_pm_lpsp@screens-disabled.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-dg2: [PASS][71] -> [SKIP][72] ([i915#1397]) +1 similar issue [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress.html * igt@i915_pm_rpm@pc8-residency: - shard-mtlp: NOTRUN -> [SKIP][73] ([fdo#109293]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@i915_pm_rpm@pc8-residency.html * igt@i915_pm_rpm@system-suspend-execbuf: - shard-tglu: NOTRUN -> [FAIL][74] ([i915#7940]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@i915_pm_rpm@system-suspend-execbuf.html * igt@i915_suspend@basic-s3-without-i915: - shard-dg2: [PASS][75] -> [FAIL][76] ([fdo#103375] / [i915#6121]) +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-2/igt@i915_suspend@basic-s3-without-i915.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@i915_suspend@basic-s3-without-i915.html - shard-tglu: NOTRUN -> [INCOMPLETE][77] ([i915#7443] / [i915#8102]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-3/igt@i915_suspend@basic-s3-without-i915.html * igt@i915_suspend@debugfs-reader: - shard-apl: [PASS][78] -> [ABORT][79] ([i915#180] / [i915#8213]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl4/igt@i915_suspend@debugfs-reader.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl7/igt@i915_suspend@debugfs-reader.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-snb: NOTRUN -> [DMESG-WARN][80] ([i915#8841]) +4 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb4/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - shard-mtlp: NOTRUN -> [SKIP][81] ([i915#4212]) [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - shard-dg2: NOTRUN -> [SKIP][82] ([i915#4215] / [i915#5190]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-10/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_async_flips@crc@pipe-a-hdmi-a-3: - shard-dg2: NOTRUN -> [FAIL][83] ([i915#8247]) +3 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html * igt@kms_big_fb@4-tiled-16bpp-rotate-90: - shard-mtlp: NOTRUN -> [SKIP][84] ([fdo#111614]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html * igt@kms_big_fb@4-tiled-8bpp-rotate-270: - shard-dg2: NOTRUN -> [SKIP][85] ([fdo#111614]) +1 similar issue [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-mtlp: [PASS][86] -> [FAIL][87] ([i915#3743]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-tglu: NOTRUN -> [SKIP][88] ([fdo#111615] / [i915#5286]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-rkl: NOTRUN -> [SKIP][89] ([i915#5286]) +1 similar issue [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html - shard-mtlp: [PASS][90] -> [FAIL][91] ([i915#5138]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][92] ([fdo#111614] / [i915#3638]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-mtlp: NOTRUN -> [FAIL][93] ([i915#3743]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@y-tiled-8bpp-rotate-90: - shard-tglu: NOTRUN -> [SKIP][94] ([fdo#111614]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-90: - shard-rkl: NOTRUN -> [SKIP][95] ([fdo#110723]) +2 similar issues [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html * igt@kms_big_fb@yf-tiled-addfb-size-overflow: - shard-dg2: NOTRUN -> [SKIP][96] ([i915#5190]) +5 similar issues [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html - shard-tglu: NOTRUN -> [SKIP][97] ([fdo#111615]) +1 similar issue [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html - shard-mtlp: NOTRUN -> [SKIP][98] ([i915#6187]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-mtlp: NOTRUN -> [SKIP][99] ([fdo#111615]) +4 similar issues [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: - shard-dg2: NOTRUN -> [SKIP][100] ([i915#4538] / [i915#5190]) +3 similar issues [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs: - shard-mtlp: NOTRUN -> [SKIP][101] ([i915#3886] / [i915#6095]) +5 similar issues [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc: - shard-rkl: NOTRUN -> [SKIP][102] ([i915#5354] / [i915#6095]) +4 similar issues [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs: - shard-dg2: NOTRUN -> [SKIP][103] ([i915#3689] / [i915#5354]) +12 similar issues [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html * igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc: - shard-tglu: NOTRUN -> [SKIP][104] ([i915#5354] / [i915#6095]) +8 similar issues [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-3/igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-rkl: NOTRUN -> [SKIP][105] ([i915#3886] / [i915#5354] / [i915#6095]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs: - shard-tglu: NOTRUN -> [SKIP][106] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +2 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-7/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs: - shard-rkl: NOTRUN -> [SKIP][107] ([i915#3734] / [i915#5354] / [i915#6095]) +1 similar issue [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs: - shard-tglu: NOTRUN -> [SKIP][108] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-5/igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs: - shard-dg2: NOTRUN -> [SKIP][109] ([i915#5354]) +18 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html - shard-rkl: NOTRUN -> [SKIP][110] ([i915#5354]) +8 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc: - shard-dg2: NOTRUN -> [SKIP][111] ([i915#3689] / [i915#3886] / [i915#5354]) +3 similar issues [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc: - shard-tglu: NOTRUN -> [SKIP][112] ([i915#3689] / [i915#5354] / [i915#6095]) +9 similar issues [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-5/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: - shard-mtlp: NOTRUN -> [SKIP][113] ([i915#6095]) +16 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html * igt@kms_chamelium_audio@dp-audio: - shard-tglu: NOTRUN -> [SKIP][114] ([i915#7828]) +3 similar issues [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_chamelium_audio@dp-audio.html - shard-mtlp: NOTRUN -> [SKIP][115] ([i915#7828]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-8/igt@kms_chamelium_audio@dp-audio.html * igt@kms_chamelium_color@ctm-0-50: - shard-tglu: NOTRUN -> [SKIP][116] ([fdo#111827]) +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-6/igt@kms_chamelium_color@ctm-0-50.html * igt@kms_chamelium_color@ctm-0-75: - shard-mtlp: NOTRUN -> [SKIP][117] ([fdo#111827]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@kms_chamelium_color@ctm-0-75.html * igt@kms_chamelium_color@ctm-blue-to-red: - shard-dg2: NOTRUN -> [SKIP][118] ([fdo#111827]) [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_chamelium_color@ctm-blue-to-red.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: - shard-rkl: NOTRUN -> [SKIP][119] ([i915#7828]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html * igt@kms_chamelium_frames@hdmi-cmp-planar-formats: - shard-dg2: NOTRUN -> [SKIP][120] ([i915#7828]) +1 similar issue [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html * igt@kms_content_protection@legacy: - shard-dg2: NOTRUN -> [SKIP][121] ([i915#7118]) +2 similar issues [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-2/igt@kms_content_protection@legacy.html * igt@kms_content_protection@mei_interface: - shard-mtlp: NOTRUN -> [SKIP][122] ([i915#8063]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_content_protection@mei_interface.html * igt@kms_content_protection@uevent: - shard-rkl: NOTRUN -> [SKIP][123] ([i915#7118]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@cursor-onscreen-512x170: - shard-rkl: NOTRUN -> [SKIP][124] ([fdo#109279] / [i915#3359]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_cursor_crc@cursor-onscreen-512x170.html * igt@kms_cursor_crc@cursor-onscreen-512x512: - shard-tglu: NOTRUN -> [SKIP][125] ([i915#3359]) +1 similar issue [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_cursor_crc@cursor-onscreen-512x512.html * igt@kms_cursor_crc@cursor-random-32x10: - shard-mtlp: NOTRUN -> [SKIP][126] ([i915#8814]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_cursor_crc@cursor-random-32x10.html * igt@kms_cursor_crc@cursor-random-512x512: - shard-mtlp: NOTRUN -> [SKIP][127] ([i915#3359]) [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_cursor_crc@cursor-random-512x512.html * igt@kms_cursor_crc@cursor-sliding-512x512: - shard-dg2: NOTRUN -> [SKIP][128] ([i915#3359]) +2 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_cursor_crc@cursor-sliding-512x512.html - shard-rkl: NOTRUN -> [SKIP][129] ([i915#3359]) +1 similar issue [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-512x512.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-mtlp: NOTRUN -> [SKIP][130] ([i915#3546]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@cursora-vs-flipb-legacy: - shard-tglu: NOTRUN -> [SKIP][131] ([fdo#109274]) +3 similar issues [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-9/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle: - shard-dg2: NOTRUN -> [SKIP][132] ([fdo#109274] / [i915#5354]) +1 similar issue [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html - shard-rkl: NOTRUN -> [SKIP][133] ([fdo#111825]) +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-dg2: NOTRUN -> [SKIP][134] ([fdo#109274] / [fdo#111767] / [i915#5354]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html - shard-rkl: NOTRUN -> [SKIP][135] ([fdo#111767] / [fdo#111825]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][136] -> [FAIL][137] ([i915#2346]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html - shard-glk: [PASS][138] -> [FAIL][139] ([i915#2346]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1: - shard-rkl: NOTRUN -> [SKIP][140] ([i915#3804]) [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html * igt@kms_dp_aux_dev: - shard-tglu: NOTRUN -> [SKIP][141] ([i915#1257]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@kms_dp_aux_dev.html * igt@kms_dsc@dsc-with-bpc-formats: - shard-tglu: NOTRUN -> [SKIP][142] ([i915#3555] / [i915#3840]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-9/igt@kms_dsc@dsc-with-bpc-formats.html * igt@kms_dsc@dsc-with-output-formats: - shard-mtlp: NOTRUN -> [SKIP][143] ([i915#3840]) [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_dsc@dsc-with-output-formats.html * igt@kms_fbcon_fbt@psr: - shard-dg2: NOTRUN -> [SKIP][144] ([i915#3469]) [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@kms_fbcon_fbt@psr.html - shard-rkl: NOTRUN -> [SKIP][145] ([fdo#110189] / [i915#3955]) [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_fbcon_fbt@psr.html * igt@kms_flip@2x-blocking-absolute-wf_vblank: - shard-tglu: NOTRUN -> [SKIP][146] ([fdo#109274] / [i915#3637]) +2 similar issues [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_flip@2x-blocking-absolute-wf_vblank.html * igt@kms_flip@2x-flip-vs-blocking-wf-vblank: - shard-snb: NOTRUN -> [SKIP][147] ([fdo#109271] / [fdo#111767]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb5/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html * igt@kms_flip@2x-flip-vs-fences-interruptible: - shard-mtlp: NOTRUN -> [SKIP][148] ([i915#8381]) [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_flip@2x-flip-vs-fences-interruptible.html * igt@kms_flip@2x-plain-flip-fb-recreate: - shard-apl: NOTRUN -> [SKIP][149] ([fdo#109271]) +24 similar issues [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl6/igt@kms_flip@2x-plain-flip-fb-recreate.html * igt@kms_flip@2x-plain-flip-interruptible: - shard-mtlp: NOTRUN -> [SKIP][150] ([i915#3637]) [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_flip@2x-plain-flip-interruptible.html * igt@kms_flip@2x-wf_vblank-ts-check-interruptible: - shard-dg2: NOTRUN -> [SKIP][151] ([fdo#109274]) [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-8/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode: - shard-rkl: NOTRUN -> [SKIP][152] ([i915#2672]) [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][153] ([i915#2672]) +1 similar issue [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode: - shard-mtlp: NOTRUN -> [SKIP][154] ([i915#8810]) [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html * igt@kms_force_connector_basic@prune-stale-modes: - shard-mtlp: NOTRUN -> [SKIP][155] ([i915#5274]) [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_force_connector_basic@prune-stale-modes.html - shard-dg2: NOTRUN -> [SKIP][156] ([i915#5274]) [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - shard-mtlp: NOTRUN -> [SKIP][157] ([i915#8708]) +1 similar issue [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: - shard-dg2: [PASS][158] -> [FAIL][159] ([i915#6880]) [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt: - shard-rkl: NOTRUN -> [SKIP][160] ([i915#3023]) +4 similar issues [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc: - shard-dg2: NOTRUN -> [SKIP][161] ([i915#8708]) +5 similar issues [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html - shard-rkl: NOTRUN -> [SKIP][162] ([fdo#111825] / [i915#1825]) +8 similar issues [162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite: - shard-tglu: NOTRUN -> [SKIP][163] ([fdo#109280]) +14 similar issues [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4: - shard-tglu: NOTRUN -> [SKIP][164] ([i915#5439]) [164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu: - shard-tglu: NOTRUN -> [SKIP][165] ([fdo#110189]) +12 similar issues [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render: - shard-dg2: NOTRUN -> [SKIP][166] ([i915#3458]) +3 similar issues [166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu: - shard-mtlp: NOTRUN -> [SKIP][167] ([i915#1825]) +10 similar issues [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html * igt@kms_hdr@bpc-switch: - shard-tglu: NOTRUN -> [SKIP][168] ([i915#3555] / [i915#8228]) [168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-7/igt@kms_hdr@bpc-switch.html * igt@kms_hdr@bpc-switch-suspend: - shard-rkl: NOTRUN -> [SKIP][169] ([i915#3555] / [i915#8228]) [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_hdr@static-toggle: - shard-dg2: NOTRUN -> [SKIP][170] ([i915#3555] / [i915#8228]) +1 similar issue [170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_hdr@static-toggle.html * igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c: - shard-tglu: NOTRUN -> [SKIP][171] ([fdo#109289]) +1 similar issue [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-7/igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c.html * igt@kms_plane_scaling@intel-max-src-size: - shard-dg2: NOTRUN -> [SKIP][172] ([i915#6953]) [172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_plane_scaling@intel-max-src-size.html * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1: - shard-snb: NOTRUN -> [SKIP][173] ([fdo#109271]) +101 similar issues [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1.html * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1: - shard-tglu: NOTRUN -> [SKIP][174] ([i915#5176]) +15 similar issues [174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1.html * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][175] ([i915#5176]) +7 similar issues [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2.html * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3: - shard-dg2: NOTRUN -> [SKIP][176] ([i915#5235]) +15 similar issues [176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3.html * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1: - shard-mtlp: NOTRUN -> [SKIP][177] ([i915#5235]) +3 similar issues [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2: - shard-rkl: NOTRUN -> [SKIP][178] ([i915#5235]) +3 similar issues [178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html * igt@kms_psr2_sf@cursor-plane-move-continuous-sf: - shard-apl: NOTRUN -> [SKIP][179] ([fdo#109271] / [i915#658]) [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl6/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-dg2: NOTRUN -> [SKIP][180] ([i915#658]) +1 similar issue [180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html - shard-mtlp: NOTRUN -> [SKIP][181] ([i915#4348]) [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-tglu: NOTRUN -> [SKIP][182] ([fdo#109642] / [fdo#111068] / [i915#658]) +1 similar issue [182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@primary_mmap_cpu: - shard-dg2: NOTRUN -> [SKIP][183] ([i915#1072]) +4 similar issues [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-3/igt@kms_psr@primary_mmap_cpu.html - shard-rkl: NOTRUN -> [SKIP][184] ([i915#1072]) +2 similar issues [184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_psr@primary_mmap_cpu.html * igt@kms_psr@psr2_cursor_blt: - shard-mtlp: [PASS][185] -> [FAIL][186] ([i915#8726]) [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@kms_psr@psr2_cursor_blt.html [186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@kms_psr@psr2_cursor_blt.html * igt@kms_psr@psr2_cursor_mmap_gtt: - shard-mtlp: NOTRUN -> [SKIP][187] ([i915#4077]) +2 similar issues [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_psr@psr2_cursor_mmap_gtt.html * igt@kms_rmfb@close-fd@pipe-a-edp-1: - shard-mtlp: [PASS][188] -> [DMESG-WARN][189] ([i915#1982]) [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-1/igt@kms_rmfb@close-fd@pipe-a-edp-1.html [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@kms_rmfb@close-fd@pipe-a-edp-1.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270: - shard-mtlp: NOTRUN -> [SKIP][190] ([i915#4235]) [190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html * igt@kms_scaling_modes@scaling-mode-full: - shard-tglu: NOTRUN -> [SKIP][191] ([i915#3555]) +2 similar issues [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_scaling_modes@scaling-mode-full.html * igt@kms_tiled_display@basic-test-pattern: - shard-tglu: NOTRUN -> [SKIP][192] ([i915#8623]) [192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@kms_tiled_display@basic-test-pattern.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-mtlp: NOTRUN -> [SKIP][193] ([i915#8623]) [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_vblank@pipe-c-query-forked-busy: - shard-rkl: NOTRUN -> [SKIP][194] ([i915#4070] / [i915#6768]) [194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@kms_vblank@pipe-c-query-forked-busy.html * igt@kms_vblank@pipe-d-wait-idle: - shard-rkl: NOTRUN -> [SKIP][195] ([i915#4070] / [i915#533] / [i915#6768]) [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_vblank@pipe-d-wait-idle.html * igt@kms_writeback@writeback-pixel-formats: - shard-tglu: NOTRUN -> [SKIP][196] ([i915#2437]) [196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-6/igt@kms_writeback@writeback-pixel-formats.html * igt@perf@oa-exponents@0-rcs0: - shard-glk: [PASS][197] -> [ABORT][198] ([i915#5213] / [i915#7941]) [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@perf@oa-exponents@0-rcs0.html [198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk6/igt@perf@oa-exponents@0-rcs0.html * igt@perf_pmu@event-wait@rcs0: - shard-mtlp: NOTRUN -> [SKIP][199] ([i915#8807]) [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@perf_pmu@event-wait@rcs0.html * igt@perf_pmu@rc6@other-idle-gt0: - shard-dg2: NOTRUN -> [SKIP][200] ([i915#8516]) [200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-8/igt@perf_pmu@rc6@other-idle-gt0.html - shard-tglu: NOTRUN -> [SKIP][201] ([i915#8516]) [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@perf_pmu@rc6@other-idle-gt0.html * igt@perf_pmu@render-node-busy-idle@ccs0: - shard-mtlp: [PASS][202] -> [FAIL][203] ([i915#4349]) +7 similar issues [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@perf_pmu@render-node-busy-idle@ccs0.html [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@perf_pmu@render-node-busy-idle@ccs0.html * igt@prime_vgem@basic-gtt: - shard-mtlp: NOTRUN -> [SKIP][204] ([i915#3708] / [i915#4077]) [204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@fence-wait@ccs0: - shard-mtlp: [PASS][205] -> [DMESG-WARN][206] ([i915#8875]) [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@prime_vgem@fence-wait@ccs0.html [206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@prime_vgem@fence-wait@ccs0.html * igt@prime_vgem@fence-wait@vecs0: - shard-mtlp: [PASS][207] -> [ABORT][208] ([i915#8875]) [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@prime_vgem@fence-wait@vecs0.html [208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@prime_vgem@fence-wait@vecs0.html * igt@sysfs_heartbeat_interval@nopreempt@bcs0: - shard-mtlp: [PASS][209] -> [FAIL][210] ([i915#6015]) +1 similar issue [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html [210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html * igt@sysfs_preempt_timeout@timeout@vecs0: - shard-mtlp: [PASS][211] -> [ABORT][212] ([i915#8521]) [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html [212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@sysfs_preempt_timeout@timeout@vecs0.html * igt@v3d/v3d_perfmon@create-perfmon-exceed: - shard-mtlp: NOTRUN -> [SKIP][213] ([i915#2575]) +5 similar issues [213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@v3d/v3d_perfmon@create-perfmon-exceed.html * igt@v3d/v3d_submit_cl@valid-submission: - shard-tglu: NOTRUN -> [SKIP][214] ([fdo#109315] / [i915#2575]) +4 similar issues [214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@v3d/v3d_submit_cl@valid-submission.html * igt@v3d/v3d_submit_csd@bad-multisync-in-sync: - shard-dg2: NOTRUN -> [SKIP][215] ([i915#2575]) +2 similar issues [215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html - shard-rkl: NOTRUN -> [SKIP][216] ([fdo#109315]) +2 similar issues [216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html * igt@vc4/vc4_mmap@mmap-bo: - shard-dg2: NOTRUN -> [SKIP][217] ([i915#7711]) +3 similar issues [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@vc4/vc4_mmap@mmap-bo.html - shard-rkl: NOTRUN -> [SKIP][218] ([i915#7711]) +2 similar issues [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@vc4/vc4_mmap@mmap-bo.html * igt@vc4/vc4_perfmon@create-perfmon-exceed: - shard-mtlp: NOTRUN -> [SKIP][219] ([i915#7711]) +3 similar issues [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@vc4/vc4_perfmon@create-perfmon-exceed.html * igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged: - shard-tglu: NOTRUN -> [SKIP][220] ([i915#2575]) +4 similar issues [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged.html * igt@vgem_basic@bad-pad: - shard-mtlp: [PASS][221] -> [DMESG-WARN][222] ([i915#2017]) [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@vgem_basic@bad-pad.html [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-6/igt@vgem_basic@bad-pad.html * igt@vgem_basic@sysfs: - shard-snb: [PASS][223] -> [ABORT][224] ([i915#8878]) [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-snb7/igt@vgem_basic@sysfs.html [224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb2/igt@vgem_basic@sysfs.html #### Possible fixes #### * igt@gem_create@hog-create@smem0: - shard-dg2: [FAIL][225] ([i915#5892] / [i915#8758]) -> [PASS][226] [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@gem_create@hog-create@smem0.html [226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@gem_create@hog-create@smem0.html * igt@gem_eio@hibernate: - {shard-dg1}: [ABORT][227] ([i915#4391] / [i915#7975] / [i915#8213]) -> [PASS][228] [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-14/igt@gem_eio@hibernate.html [228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-16/igt@gem_eio@hibernate.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [FAIL][229] ([i915#2842]) -> [PASS][230] [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html [230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-rkl: [FAIL][231] ([i915#2842]) -> [PASS][232] +3 similar issues [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-4/igt@gem_exec_fair@basic-throttle@rcs0.html [232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_whisper@basic-contexts-forked-all: - shard-mtlp: [ABORT][233] ([i915#8131]) -> [PASS][234] [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-forked-all.html [234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-forked-all.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-mtlp: [FAIL][235] ([i915#6363]) -> [PASS][236] [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-5/igt@gem_exec_whisper@basic-fds-priority-all.html [236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-1/igt@gem_exec_whisper@basic-fds-priority-all.html * igt@gem_lmem_swapping@smem-oom@lmem0: - {shard-dg1}: [DMESG-WARN][237] ([i915#4936] / [i915#5493]) -> [PASS][238] [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html [238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html * igt@i915_hangman@engine-engine-hang@vcs0: - shard-mtlp: [FAIL][239] ([i915#7069]) -> [PASS][240] [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@i915_hangman@engine-engine-hang@vcs0.html [240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@i915_hangman@engine-engine-hang@vcs0.html * igt@i915_module_load@reload-with-fault-injection: - shard-mtlp: [ABORT][241] ([i915#8489] / [i915#8668]) -> [PASS][242] [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html [242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html * igt@i915_pm_dc@dc9-dpms: - shard-tglu: [SKIP][243] ([i915#4281]) -> [PASS][244] [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-6/igt@i915_pm_dc@dc9-dpms.html [244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - {shard-dg1}: [FAIL][245] ([i915#3591]) -> [PASS][246] +1 similar issue [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_pm_rpm@cursor-dpms: - shard-tglu: [FAIL][247] ([i915#7940]) -> [PASS][248] +1 similar issue [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-4/igt@i915_pm_rpm@cursor-dpms.html [248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-10/igt@i915_pm_rpm@cursor-dpms.html * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - {shard-dg1}: [SKIP][249] ([i915#1397]) -> [PASS][250] [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-15/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html [250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-19/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-rkl: [SKIP][251] ([i915#1397]) -> [PASS][252] +1 similar issue [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html [252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-2/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait: - shard-dg2: [SKIP][253] ([i915#1397]) -> [PASS][254] +2 similar issues [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html [254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html * igt@i915_selftest@live@gt_mocs: - shard-mtlp: [DMESG-FAIL][255] ([i915#7059]) -> [PASS][256] [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@i915_selftest@live@gt_mocs.html [256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@i915_selftest@live@gt_mocs.html * igt@i915_selftest@live@hangcheck: - shard-dg2: [ABORT][257] ([i915#7913]) -> [PASS][258] [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-7/igt@i915_selftest@live@hangcheck.html [258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@workarounds: - shard-mtlp: [DMESG-FAIL][259] ([i915#6763]) -> [PASS][260] [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-8/igt@i915_selftest@live@workarounds.html [260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@i915_selftest@live@workarounds.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-mtlp: [FAIL][261] ([i915#3743]) -> [PASS][262] [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html [262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic: - shard-glk: [FAIL][263] ([i915#72]) -> [PASS][264] [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html [264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk2/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html * igt@kms_cursor_legacy@cursor-vs-flip-toggle: - shard-mtlp: [FAIL][265] ([i915#8248]) -> [PASS][266] [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-7/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html [266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [FAIL][267] ([i915#2346]) -> [PASS][268] [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4: - {shard-dg1}: [FAIL][269] ([i915#79]) -> [PASS][270] [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-17/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4.html [270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-17/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a4.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-apl: [ABORT][271] ([i915#180]) -> [PASS][272] [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt: - shard-dg2: [FAIL][273] ([i915#6880]) -> [PASS][274] +1 similar issue [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html [274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt.html * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2: - shard-rkl: [FAIL][275] ([i915#8292]) -> [PASS][276] [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html [276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html * igt@kms_sysfs_edid_timing: - shard-dg2: [FAIL][277] ([IGT#2]) -> [PASS][278] [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-5/igt@kms_sysfs_edid_timing.html [278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-11/igt@kms_sysfs_edid_timing.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-dg2: [FAIL][279] ([fdo#103375] / [i915#6121]) -> [PASS][280] [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@perf_pmu@busy-double-start@ccs0: - shard-mtlp: [FAIL][281] ([i915#4349]) -> [PASS][282] [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-4/igt@perf_pmu@busy-double-start@ccs0.html [282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-7/igt@perf_pmu@busy-double-start@ccs0.html * igt@perf_pmu@most-busy-idle-check-all@bcs0: - shard-mtlp: [FAIL][283] ([i915#5234]) -> [PASS][284] +1 similar issue [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-3/igt@perf_pmu@most-busy-idle-check-all@bcs0.html [284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-2/igt@perf_pmu@most-busy-idle-check-all@bcs0.html * igt@perf_pmu@most-busy-idle-check-all@rcs0: - shard-dg2: [FAIL][285] ([i915#5234]) -> [PASS][286] [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-5/igt@perf_pmu@most-busy-idle-check-all@rcs0.html [286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html - {shard-dg1}: [FAIL][287] ([i915#5234]) -> [PASS][288] [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg1-13/igt@perf_pmu@most-busy-idle-check-all@rcs0.html [288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg1-18/igt@perf_pmu@most-busy-idle-check-all@rcs0.html * igt@sysfs_timeslice_duration@timeout@vecs0: - shard-mtlp: [ABORT][289] ([i915#8521]) -> [PASS][290] [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-mtlp-2/igt@sysfs_timeslice_duration@timeout@vecs0.html [290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-mtlp-5/igt@sysfs_timeslice_duration@timeout@vecs0.html #### Warnings #### * igt@gem_exec_suspend@basic-s0@smem: - shard-snb: [DMESG-FAIL][291] ([fdo#103375]) -> [DMESG-WARN][292] ([i915#8841]) [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-snb7/igt@gem_exec_suspend@basic-s0@smem.html [292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb4/igt@gem_exec_suspend@basic-s0@smem.html * igt@i915_pm_rc6_residency@rc6-idle@bcs0: - shard-tglu: [FAIL][293] ([i915#2681] / [i915#3591]) -> [WARN][294] ([i915#2681]) [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html [294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html * igt@i915_pm_rc6_residency@rc6-idle@rcs0: - shard-tglu: [WARN][295] ([i915#2681]) -> [FAIL][296] ([i915#2681] / [i915#3591]) [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-5/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html [296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html * igt@i915_suspend@basic-s2idle-without-i915: - shard-snb: [DMESG-WARN][297] ([i915#8841]) -> [ABORT][298] ([i915#4528] / [i915#8213]) [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-snb7/igt@i915_suspend@basic-s2idle-without-i915.html [298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-snb4/igt@i915_suspend@basic-s2idle-without-i915.html * igt@kms_content_protection@mei_interface: - shard-dg2: [SKIP][299] ([i915#7118] / [i915#7162]) -> [SKIP][300] ([i915#7118]) [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-11/igt@kms_content_protection@mei_interface.html [300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-1/igt@kms_content_protection@mei_interface.html - shard-rkl: [SKIP][301] ([fdo#109300]) -> [SKIP][302] ([i915#7118]) [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-1/igt@kms_content_protection@mei_interface.html [302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-6/igt@kms_content_protection@mei_interface.html - shard-tglu: [SKIP][303] ([fdo#109300]) -> [SKIP][304] ([i915#6944] / [i915#7116] / [i915#7118]) [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-tglu-7/igt@kms_content_protection@mei_interface.html [304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-tglu-2/igt@kms_content_protection@mei_interface.html * igt@kms_force_connector_basic@force-load-detect: - shard-rkl: [SKIP][305] ([fdo#109285] / [i915#4098]) -> [SKIP][306] ([fdo#109285]) [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html [306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem: - shard-dg2: [CRASH][307] ([i915#7331]) -> [INCOMPLETE][308] ([i915#5493]) [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13369/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html [308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2 [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681 [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743 [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804 [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281 [i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348 [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880 [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936 [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213 [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493 [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784 [i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892 [i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121 [i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187 [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227 [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335 [i915#6363]: https://gitlab.freedesktop.org/drm/intel/issues/6363 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763 [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768 [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880 [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944 [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953 [i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059 [i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069 [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116 [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118 [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162 [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72 [i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331 [i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443 [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561 [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697 [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701 [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711 [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742 [i915#7816]: https://gitlab.freedesktop.org/drm/intel/issues/7816 [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828 [i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#7916]: https://gitlab.freedesktop.org/drm/intel/issues/7916 [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940 [i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941 [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975 [i915#8063]: https://gitlab.freedesktop.org/drm/intel/issues/8063 [i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102 [i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131 [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213 [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228 [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247 [i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248 [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292 [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381 [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414 [i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428 [i915#8430]: https://gitlab.freedesktop.org/drm/intel/issues/8430 [i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489 [i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502 [i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503 [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516 [i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521 [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623 [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708 [i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709 [i915#8726]: https://gitlab.freedesktop.org/drm/intel/issues/8726 [i915#8758]: https://gitlab.freedesktop.org/drm/intel/issues/8758 [i915#8807]: https://gitlab.freedesktop.org/drm/intel/issues/8807 [i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810 [i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814 [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841 [i915#8875]: https://gitlab.freedesktop.org/drm/intel/issues/8875 [i915#8878]: https://gitlab.freedesktop.org/drm/intel/issues/8878 Build changes ------------- * CI: CI-20190529 -> None * IGT: IGT_7380 -> IGTPW_9383 * Piglit: piglit_4509 -> None CI-20190529: 20190529 CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html --===============3786772691755864516== Content-Type: text/html; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Project List - Patchwork Patch Details
Series:Extend intel_blt to work on Xe (rev3)
URL:https://patchwork.freedesktop.org/series/120162/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html

CI Bug Log - changes from CI_DRM_13369_full -> IGTPW_9383_full

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html

Participating hosts (9 -> 9)

No changes in participating hosts

Known issues

Here are the changes found in IGTPW_9383_full that come from known issues:

IGT changes

Issues hit

  • igt@api_intel_bb@crc32:

  • igt@device_reset@unbind-cold-reset-rebind:

  • igt@drm_fdinfo@busy-hang@bcs0:

  • igt@drm_fdinfo@most-busy-idle-check-all@rcs0:

  • igt@drm_fdinfo@virtual-busy-all:

  • igt@gem_bad_reloc@negative-reloc-bltcopy:

  • igt@gem_basic@multigpu-create-close:

  • igt@gem_ccs@block-copy-compressed:

  • igt@gem_ccs@ctrl-surf-copy-new-ctx:

  • igt@gem_close_race@multigpu-basic-process:

  • igt@gem_create@create-ext-cpu-access-big:

  • igt@gem_ctx_exec@basic-nohangcheck:

  • igt@gem_ctx_param@set-priority-not-supported:

  • igt@gem_ctx_persistence@saturated-hostile@vecs0:

  • igt@gem_eio@in-flight-contexts-1us:

  • igt@gem_eio@kms:

  • igt@gem_exec_balancer@bonded-true-hang:

  • igt@gem_exec_fair@basic-none@bcs0:

  • igt@gem_exec_fair@basic-pace@vcs0:

  • igt@gem_exec_fair@basic-throttle:

  • igt@gem_exec_fence@submit67:

  • igt@gem_exec_params@secure-non-root:

  • igt@gem_exec_reloc@basic-write-gtt-active:

  • igt@gem_exec_whisper@basic-forked:

  • igt@gem_exec_whisper@basic-forked-all:

  • igt@gem_lmem_swapping@heavy-verify-random-ccs:

  • igt@gem_lmem_swapping@parallel-multi:

  • igt@gem_lmem_swapping@parallel-random:

  • igt@gem_lmem_swapping@smem-oom@lmem0:

  • igt@gem_media_vme:

  • igt@gem_mmap_wc@write:

  • igt@gem_partial_pwrite_pread@reads:

  • igt@gem_partial_pwrite_pread@writes-after-reads:

  • igt@gem_pxp@create-regular-buffer:

  • igt@gem_pxp@fail-invalid-protected-context:

  • igt@gem_readwrite@beyond-eob:

  • igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:

  • igt@gem_set_tiling_vs_pwrite:

  • igt@gem_tiled_fence_blits@basic:

  • igt@gem_tiled_pread_basic:

  • igt@gem_userptr_blits@coherency-unsync:

  • igt@gem_userptr_blits@invalid-mmap-offset-unsync:

  • igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:

  • igt@gem_userptr_blits@nohangcheck:

  • igt@gen7_exec_parse@load-register-reg:

  • igt@gen7_exec_parse@oacontrol-tracking:

  • igt@gen9_exec_parse@bb-large:

  • igt@i915_hangman@gt-engine-error@vcs0:

  • igt@i915_module_load@load:

  • igt@i915_pm_backlight@bad-brightness:

  • igt@i915_pm_dc@dc5-psr:

  • igt@i915_pm_dc@dc9-dpms:

  • igt@i915_pm_lpsp@screens-disabled:

  • igt@i915_pm_rpm@modeset-non-lpsp-stress:

  • igt@i915_pm_rpm@pc8-residency:

  • igt@i915_pm_rpm@system-suspend-execbuf:

  • igt@i915_suspend@basic-s3-without-i915:

  • igt@i915_suspend@debugfs-reader:

  • igt@i915_suspend@fence-restore-tiled2untiled:

  • igt@kms_addfb_basic@addfb25-x-tiled-legacy:

  • igt@kms_addfb_basic@basic-y-tiled-legacy:

  • igt@kms_async_flips@crc@pipe-a-hdmi-a-3:

  • igt@kms_big_fb@4-tiled-16bpp-rotate-90:

  • igt@kms_big_fb@4-tiled-8bpp-rotate-270:

  • igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:

  • igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:

  • igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:

  • igt@kms_big_fb@x-tiled-32bpp-rotate-90:

  • igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:

  • igt@kms_big_fb@y-tiled-8bpp-rotate-90:

  • igt@kms_big_fb@yf-tiled-64bpp-rotate-90:

  • igt@kms_big_fb@yf-tiled-addfb-size-overflow:

  • igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:

  • igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:

  • igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:

  • igt@kms_ccs@pipe-a-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc:

  • igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:

  • igt@kms_ccs@pipe-a-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc:

  • igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:

  • igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:

  • igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:

  • igt@kms_ccs@pipe-c-bad-aux-stride-yf_tiled_ccs:

  • igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs:

  • igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:

  • igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:

  • igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:

  • igt@kms_chamelium_audio@dp-audio:

  • igt@kms_chamelium_color@ctm-0-50:

  • igt@kms_chamelium_color@ctm-0-75:

  • igt@kms_chamelium_color@ctm-blue-to-red:

  • igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k:

  • igt@kms_chamelium_frames@hdmi-cmp-planar-formats:

  • igt@kms_content_protection@legacy:

  • igt@kms_content_protection@mei_interface:

  • igt@kms_content_protection@uevent:

  • igt@kms_cursor_crc@cursor-onscreen-512x170:

  • igt@kms_cursor_crc@cursor-onscreen-512x512:

  • igt@kms_cursor_crc@cursor-random-32x10:

  • igt@kms_cursor_crc@cursor-random-512x512:

  • igt@kms_cursor_crc@cursor-sliding-512x512:

  • igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:

  • igt@kms_cursor_legacy@cursora-vs-flipb-legacy:

  • igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:

  • igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:

  • igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:

  • igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:

  • igt@kms_dp_aux_dev:

  • igt@kms_dsc@dsc-with-bpc-formats:

  • igt@kms_dsc@dsc-with-output-formats:

  • igt@kms_fbcon_fbt@psr:

  • igt@kms_flip@2x-blocking-absolute-wf_vblank:

  • igt@kms_flip@2x-flip-vs-blocking-wf-vblank:

  • igt@kms_flip@2x-flip-vs-fences-interruptible:

  • igt@kms_flip@2x-plain-flip-fb-recreate:

  • igt@kms_flip@2x-plain-flip-interruptible:

  • igt@kms_flip@2x-wf_vblank-ts-check-interruptible:

  • igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:

  • igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:

  • igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:

  • igt@kms_force_connector_basic@prune-stale-modes:

  • igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:

  • igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:

  • igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:

  • igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc:

  • igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite:

  • igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:

  • igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:

  • igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render:

  • igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu:

  • igt@kms_hdr@bpc-switch:

  • igt@kms_hdr@bpc-switch-suspend:

  • igt@kms_hdr@static-toggle:

  • igt@kms_pipe_b_c_ivb@pipe-b-dpms-off-modeset-pipe-c:

  • igt@kms_plane_scaling@intel-max-src-size:

  • igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-vga-1:

  • igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1:

  • igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2:

  • igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-3:

  • igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-edp-1:

  • igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:

  • igt@kms_psr2_sf@cursor-plane-move-continuous-sf:

  • igt@kms_psr2_su@frontbuffer-xrgb8888:

  • igt@kms_psr2_su@page_flip-xrgb8888:

  • igt@kms_psr@primary_mmap_cpu:

  • igt@kms_psr@psr2_cursor_blt:

  • igt@kms_psr@psr2_cursor_mmap_gtt:

  • igt@kms_rmfb@close-fd@pipe-a-edp-1:

  • igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:

  • igt@kms_scaling_modes@scaling-mode-full:

  • igt@kms_tiled_display@basic-test-pattern:

  • igt@kms_tiled_display@basic-test-pattern-with-chamelium:

  • igt@kms_vblank@pipe-c-query-forked-busy:

  • igt@kms_vblank@pipe-d-wait-idle:

  • igt@kms_writeback@writeback-pixel-formats:

  • igt@perf@oa-exponents@0-rcs0:

  • igt@perf_pmu@event-wait@rcs0:

  • igt@perf_pmu@rc6@other-idle-gt0:

  • igt@perf_pmu@render-node-busy-idle@ccs0:

  • igt@prime_vgem@basic-gtt:

  • igt@prime_vgem@fence-wait@ccs0:

  • igt@prime_vgem@fence-wait@vecs0:

  • igt@sysfs_heartbeat_interval@nopreempt@bcs0:

  • igt@sysfs_preempt_timeout@timeout@vecs0:

  • igt@v3d/v3d_perfmon@create-perfmon-exceed:

  • igt@v3d/v3d_submit_cl@valid-submission:

  • igt@v3d/v3d_submit_csd@bad-multisync-in-sync:

  • igt@vc4/vc4_mmap@mmap-bo:

  • igt@vc4/vc4_perfmon@create-perfmon-exceed:

  • igt@vc4/vc4_purgeable_bo@mark-unpurgeable-purged:

  • igt@vgem_basic@bad-pad:

  • igt@vgem_basic@sysfs:

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

  • CI: CI-20190529 -> None
  • IGT: IGT_7380 -> IGTPW_9383
  • Piglit: piglit_4509 -> None

CI-20190529: 20190529
CI_DRM_13369: 0595153b5c237d83f9990f3ce44d072a262dcb0e @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9383/index.html
IGT_7380: 8e65f12de2fd52c05dc48fdbcb8cfe86f6de1a75 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

--===============3786772691755864516==-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA7A110E118 for ; Fri, 14 Jul 2023 04:56:56 +0000 (UTC) From: "Yedireswarapu, SaiX Nandan" To: "Kempczynski, Zbigniew" , "igt-dev@lists.freedesktop.org" Date: Fri, 14 Jul 2023 04:56:30 +0000 Message-ID: References: <20230711112009.122482-1-zbigniew.kempczynski@intel.com> <168908713268.18666.15567798926028643785@emeril.freedesktop.org> <20230712081415.doigqvklqmi26i4x@zkempczy-mobl2> In-Reply-To: <20230712081415.doigqvklqmi26i4x@zkempczy-mobl2> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Subject: Re: [igt-dev] =?utf-8?b?4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRXh0ZW5k?= =?utf-8?q?_intel=5Fblt_to_work_on_Xe_=28rev3=29?= List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: SGksDQoNCklzc3VlIHJlLXJlcG9ydGVkLCBodHRwczovL3BhdGNod29yay5mcmVlZGVza3RvcC5v cmcvc2VyaWVzLzEyMDE2Mi8jcmV2Mw0KDQpUaGFua3MsDQpZIFNhaSBOYW5kYW4NCg0KLS0tLS1P cmlnaW5hbCBNZXNzYWdlLS0tLS0NCkZyb206IEtlbXBjenluc2tpLCBaYmlnbmlldyA8emJpZ25p ZXcua2VtcGN6eW5za2lAaW50ZWwuY29tPiANClNlbnQ6IFdlZG5lc2RheSwgSnVseSAxMiwgMjAy MyAxOjQ0IFBNDQpUbzogaWd0LWRldkBsaXN0cy5mcmVlZGVza3RvcC5vcmcNCkNjOiBZZWRpcmVz d2FyYXB1LCBTYWlYIE5hbmRhbiA8c2FpeC5uYW5kYW4ueWVkaXJlc3dhcmFwdUBpbnRlbC5jb20+ DQpTdWJqZWN0OiBSZTog4pyXIEZpLkNJLklHVDogZmFpbHVyZSBmb3IgRXh0ZW5kIGludGVsX2Js dCB0byB3b3JrIG9uIFhlIChyZXYzKQ0KDQpPbiBUdWUsIEp1bCAxMSwgMjAyMyBhdCAwMjo1Mjox MlBNICswMDAwLCBQYXRjaHdvcmsgd3JvdGU6DQo+ICAgIFBhdGNoIERldGFpbHMNCj4gDQo+ICAg IFNlcmllczogIEV4dGVuZCBpbnRlbF9ibHQgdG8gd29yayBvbiBYZSAocmV2MykgICAgICAgICAg ICAgICAgICAgICAgICAgIA0KPiAgICBVUkw6ICAgICBodHRwczovL3BhdGNod29yay5mcmVlZGVz a3RvcC5vcmcvc2VyaWVzLzEyMDE2Mi8gICAgICAgICAgICAgICANCj4gICAgU3RhdGU6ICAgZmFp bHVyZSAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgDQo+ICAgIERldGFpbHM6IGh0dHBzOi8vaW50ZWwtZ2Z4LWNpLjAxLm9yZy90cmVlL2RybS10 aXAvSUdUUFdfOTM4My9pbmRleC5odG1sIA0KPiANCj4gICAgICAgICAgQ0kgQnVnIExvZyAtIGNo YW5nZXMgZnJvbSBDSV9EUk1fMTMzNjlfZnVsbCAtPiBJR1RQV185MzgzX2Z1bGwNCj4gDQo+IFN1 bW1hcnkNCj4gDQo+ICAgIEZBSUxVUkUNCj4gDQo+ICAgIFNlcmlvdXMgdW5rbm93biBjaGFuZ2Vz IGNvbWluZyB3aXRoIElHVFBXXzkzODNfZnVsbCBhYnNvbHV0ZWx5IG5lZWQgdG8gYmUNCj4gICAg dmVyaWZpZWQgbWFudWFsbHkuDQo+IA0KPiAgICBJZiB5b3UgdGhpbmsgdGhlIHJlcG9ydGVkIGNo YW5nZXMgaGF2ZSBub3RoaW5nIHRvIGRvIHdpdGggdGhlIGNoYW5nZXMNCj4gICAgaW50cm9kdWNl ZCBpbiBJR1RQV185MzgzX2Z1bGwsIHBsZWFzZSBub3RpZnkgeW91ciBidWcgdGVhbSB0byBhbGxv dyB0aGVtDQo+ICAgIHRvIGRvY3VtZW50IHRoaXMgbmV3IGZhaWx1cmUgbW9kZSwgd2hpY2ggd2ls bCByZWR1Y2UgZmFsc2UgcG9zaXRpdmVzIGluDQo+ICAgIENJLg0KPiANCj4gICAgRXh0ZXJuYWwg VVJMOg0KPiAgICBodHRwczovL2ludGVsLWdmeC1jaS4wMS5vcmcvdHJlZS9kcm0tdGlwL0lHVFBX XzkzODMvaW5kZXguaHRtbA0KPiANCj4gUGFydGljaXBhdGluZyBob3N0cyAoOSAtPiA5KQ0KPiAN Cj4gICAgTm8gY2hhbmdlcyBpbiBwYXJ0aWNpcGF0aW5nIGhvc3RzDQo+IA0KPiBQb3NzaWJsZSBu ZXcgaXNzdWVzDQo+IA0KPiAgICBIZXJlIGFyZSB0aGUgdW5rbm93biBjaGFuZ2VzIHRoYXQgbWF5 IGhhdmUgYmVlbiBpbnRyb2R1Y2VkIGluDQo+ICAgIElHVFBXXzkzODNfZnVsbDoNCj4gDQo+ICAg SUdUIGNoYW5nZXMNCj4gDQo+ICAgICBQb3NzaWJsZSByZWdyZXNzaW9ucw0KPiANCj4gICAgICAq IGlndEBwcmltZV92Z2VtQGZlbmNlLXdhaXRAY2NzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJk LW10bHA6IFBBU1MgLT4gRE1FU0ctV0FSTg0KPiAgICAgICogaWd0QHByaW1lX3ZnZW1AZmVuY2Ut d2FpdEB2ZWNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IFBBU1MgLT4gQUJPUlQN Cj4gICAgICAqIGlndEB2Z2VtX2Jhc2ljQHN5c2ZzOg0KPiANCj4gICAgICAgICAgICogc2hhcmQt c25iOiBQQVNTIC0+IEFCT1JUDQoNClVucmVsYXRlZCB0byB0aGUgY2hhbmdlLg0KDQotLQ0KWmJp Z25pZXcNCg0KPiANCj4gS25vd24gaXNzdWVzDQo+IA0KPiAgICBIZXJlIGFyZSB0aGUgY2hhbmdl cyBmb3VuZCBpbiBJR1RQV185MzgzX2Z1bGwgdGhhdCBjb21lIGZyb20ga25vd24gaXNzdWVzOg0K PiANCj4gICBJR1QgY2hhbmdlcw0KPiANCj4gICAgIElzc3VlcyBoaXQNCj4gDQo+ICAgICAgKiBp Z3RAYXBpX2ludGVsX2JiQGNyYzMyOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9U UlVOIC0+IFNLSVAgKGk5MTUjNjIzMCkNCj4gICAgICAqIGlndEBkZXZpY2VfcmVzZXRAdW5iaW5k LWNvbGQtcmVzZXQtcmViaW5kOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4g LT4gU0tJUCAoaTkxNSM3NzAxKQ0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4g LT4gU0tJUCAoaTkxNSM3NzAxKQ0KPiANCj4gICAgICAqIGlndEBkcm1fZmRpbmZvQGJ1c3ktaGFu Z0BiY3MwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJUCAoaTkx NSM4NDE0KSArMTkgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBkcm1fZmRpbmZvQG1vc3Qt YnVzeS1pZGxlLWNoZWNrLWFsbEByY3MwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBQ QVNTIC0+IEZBSUwgKGk5MTUjNzc0MikNCj4gICAgICAqIGlndEBkcm1fZmRpbmZvQHZpcnR1YWwt YnVzeS1hbGw6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gU0tJUCAo aTkxNSM4NDE0KQ0KPiAgICAgICogaWd0QGdlbV9iYWRfcmVsb2NAbmVnYXRpdmUtcmVsb2MtYmx0 Y29weToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChpOTE1 IzMyODEpICs1IHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAZ2VtX2Jhc2ljQG11bHRpZ3B1 LWNyZWF0ZS1jbG9zZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNL SVAgKGk5MTUjNzY5NykgKzEgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGdlbV9jY3NAYmxv Y2stY29weS1jb21wcmVzc2VkOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVO IC0+IFNLSVAgKGk5MTUjMzU1NSAvIGk5MTUjNTMyNSkNCj4gICAgICAqIGlndEBnZW1fY2NzQGN0 cmwtc3VyZi1jb3B5LW5ldy1jdHg6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RS VU4gLT4gU0tJUCAoaTkxNSM1MzI1KQ0KPiAgICAgICogaWd0QGdlbV9jbG9zZV9yYWNlQG11bHRp Z3B1LWJhc2ljLXByb2Nlc3M6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAt PiBTS0lQIChpOTE1Izc2OTcpICsxIHNpbWlsYXIgaXNzdWUNCj4gICAgICAqIGlndEBnZW1fY3Jl YXRlQGNyZWF0ZS1leHQtY3B1LWFjY2Vzcy1iaWc6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10 Z2x1OiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM2MzM1KQ0KPiAgICAgICogaWd0QGdlbV9jdHhfZXhl Y0BiYXNpYy1ub2hhbmdjaGVjazoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IFBBU1Mg LT4gRkFJTCAoaTkxNSM2MjY4KQ0KPiAgICAgICogaWd0QGdlbV9jdHhfcGFyYW1Ac2V0LXByaW9y aXR5LW5vdC1zdXBwb3J0ZWQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAt PiBTS0lQIChmZG8jMTA5MzE0KQ0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4g LT4gU0tJUCAoZmRvIzEwOTMxNCkNCj4gDQo+ICAgICAgKiBpZ3RAZ2VtX2N0eF9wZXJzaXN0ZW5j ZUBzYXR1cmF0ZWQtaG9zdGlsZUB2ZWNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6 IFBBU1MgLT4gRkFJTCAoaTkxNSM3ODE2KSArMiBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0 QGdlbV9laW9AaW4tZmxpZ2h0LWNvbnRleHRzLTF1czoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJk LW10bHA6IFBBU1MgLT4gQUJPUlQgKGk5MTUjODUwMykNCj4gICAgICAqIGlndEBnZW1fZWlvQGtt czoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogUEFTUyAtPiBJTkNPTVBMRVRFIChpOTE1 Izc4OTIpDQo+ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfYmFsYW5jZXJAYm9uZGVkLXRydWUtaGFuZzoN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNDgxMikg KzIgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBnZW1fZXhlY19mYWlyQGJhc2ljLW5vbmVA YmNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBGQUlMIChpOTE1 IzI4NDIpICs0IHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfZmFpckBiYXNp Yy1wYWNlQHZjczA6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1nbGs6IFBBU1MgLT4gRkFJTCAo aTkxNSMyODQyKSArMSBzaW1pbGFyIGlzc3VlDQo+ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfZmFpckBi YXNpYy10aHJvdHRsZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNL SVAgKGk5MTUjMzUzOSkNCj4gICAgICAqIGlndEBnZW1fZXhlY19mZW5jZUBzdWJtaXQ2NzoNCj4g DQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzQ4MTIpDQo+ ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfcGFyYW1zQHNlY3VyZS1ub24tcm9vdDoNCj4gDQo+ICAgICAg ICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTEyMjgzKQ0KPiAgICAgICog aWd0QGdlbV9leGVjX3JlbG9jQGJhc2ljLXdyaXRlLWd0dC1hY3RpdmU6DQo+IA0KPiAgICAgICAg ICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzMyODEpICsyIHNpbWlsYXIgaXNz dWVzDQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzMy ODEpICsxIHNpbWlsYXIgaXNzdWUNCj4gDQo+ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfd2hpc3BlckBi YXNpYy1mb3JrZWQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gRkFJ TCAoaTkxNSM2MzYzKQ0KPiAgICAgICogaWd0QGdlbV9leGVjX3doaXNwZXJAYmFzaWMtZm9ya2Vk LWFsbDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IFBBU1MgLT4gRkFJTCAoaTkxNSM2 MzYzKQ0KPiAgICAgICogaWd0QGdlbV9sbWVtX3N3YXBwaW5nQGhlYXZ5LXZlcmlmeS1yYW5kb20t Y2NzOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IFNLSVAgKGk5MTUj NDYxMykgKzIgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBnZW1fbG1lbV9zd2FwcGluZ0Bw YXJhbGxlbC1tdWx0aToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWFwbDogTk9UUlVOIC0+IFNL SVAgKGZkbyMxMDkyNzEgLyBpOTE1IzQ2MTMpDQo+ICAgICAgKiBpZ3RAZ2VtX2xtZW1fc3dhcHBp bmdAcGFyYWxsZWwtcmFuZG9tOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVO IC0+IFNLSVAgKGk5MTUjNDYxMykNCj4gICAgICAqIGlndEBnZW1fbG1lbV9zd2FwcGluZ0BzbWVt LW9vbUBsbWVtMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogUEFTUyAtPiBUSU1FT1VU IChpOTE1IzU0OTMpDQo+ICAgICAgKiBpZ3RAZ2VtX21lZGlhX3ZtZToNCj4gDQo+ICAgICAgICAg ICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzI4NCkNCj4gICAgICAqIGlndEBn ZW1fbW1hcF93Y0B3cml0ZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAt PiBTS0lQIChpOTE1IzQwODMpICsxIHNpbWlsYXIgaXNzdWUNCj4gDQo+ICAgICAgICAgICAqIHNo YXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNDA4MykgKzMgc2ltaWxhciBpc3N1ZXMNCj4g DQo+ICAgICAgKiBpZ3RAZ2VtX3BhcnRpYWxfcHdyaXRlX3ByZWFkQHJlYWRzOg0KPiANCj4gICAg ICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMzI4MikgKzMgc2ltaWxh ciBpc3N1ZXMNCj4gICAgICAqIGlndEBnZW1fcGFydGlhbF9wd3JpdGVfcHJlYWRAd3JpdGVzLWFm dGVyLXJlYWRzOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4gLT4gU0tJUCAo aTkxNSMzMjgyKSArMiBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGdlbV9weHBAY3JlYXRl LXJlZ3VsYXItYnVmZmVyOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+ IFNLSVAgKGk5MTUjNDI3MCkNCj4gICAgICAqIGlndEBnZW1fcHhwQGZhaWwtaW52YWxpZC1wcm90 ZWN0ZWQtY29udGV4dDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBT S0lQIChpOTE1IzQyNzApICsxIHNpbWlsYXIgaXNzdWUNCj4gICAgICAqIGlndEBnZW1fcmVhZHdy aXRlQGJleW9uZC1lb2I6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBT S0lQIChpOTE1IzMyODIpICszIHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAZ2VtX3JlbmRl cl9jb3B5QHktdGlsZWQtY2NzLXRvLXlmLXRpbGVkLWNjczoNCj4gDQo+ICAgICAgICAgICAqIHNo YXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChpOTE1Izg0MjgpICszIHNpbWlsYXIgaXNzdWVzDQo+ ICAgICAgKiBpZ3RAZ2VtX3NldF90aWxpbmdfdnNfcHdyaXRlOg0KPiANCj4gICAgICAgICAgICog c2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM0MDc5KQ0KPiAgICAgICogaWd0QGdlbV90 aWxlZF9mZW5jZV9ibGl0c0BiYXNpYzoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9U UlVOIC0+IFNLSVAgKGk5MTUjNDA3NykgKzMgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBn ZW1fdGlsZWRfcHJlYWRfYmFzaWM6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RS VU4gLT4gU0tJUCAoaTkxNSM0MDc5KQ0KPiAgICAgICogaWd0QGdlbV91c2VycHRyX2JsaXRzQGNv aGVyZW5jeS11bnN5bmM6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4g U0tJUCAoaTkxNSMzMjk3KQ0KPiAgICAgICogaWd0QGdlbV91c2VycHRyX2JsaXRzQGludmFsaWQt bW1hcC1vZmZzZXQtdW5zeW5jOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4g LT4gU0tJUCAoaTkxNSMzMjk3KQ0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4g LT4gU0tJUCAoaTkxNSMzMjk3KQ0KPiANCj4gICAgICAqIGlndEBnZW1fdXNlcnB0cl9ibGl0c0Bt YXAtZml4ZWQtaW52YWxpZGF0ZS1vdmVybGFwLWJ1c3k6DQo+IA0KPiAgICAgICAgICAgKiBzaGFy ZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzMyOTcgLyBpOTE1IzQ4ODApDQo+ICAgICAgKiBp Z3RAZ2VtX3VzZXJwdHJfYmxpdHNAbm9oYW5nY2hlY2s6DQo+IA0KPiAgICAgICAgICAgKiBzaGFy ZC1tdGxwOiBQQVNTIC0+IEZBSUwgKGk5MTUjNzkxNikNCj4gICAgICAqIGlndEBnZW43X2V4ZWNf cGFyc2VAbG9hZC1yZWdpc3Rlci1yZWc6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5P VFJVTiAtPiBTS0lQIChmZG8jMTA5Mjg5KQ0KPiAgICAgICogaWd0QGdlbjdfZXhlY19wYXJzZUBv YWNvbnRyb2wtdHJhY2tpbmc6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4g LT4gU0tJUCAoZmRvIzEwOTI4OSkNCj4gICAgICAqIGlndEBnZW45X2V4ZWNfcGFyc2VAYmItbGFy Z2U6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzI4 NTYpDQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzI1 MjcpDQo+IA0KPiAgICAgICogaWd0QGk5MTVfaGFuZ21hbkBndC1lbmdpbmUtZXJyb3JAdmNzMDoN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IFBBU1MgLT4gRkFJTCAoaTkxNSM3MDY5KQ0K PiAgICAgICogaWd0QGk5MTVfbW9kdWxlX2xvYWRAbG9hZDoNCj4gDQo+ICAgICAgICAgICAqIHNo YXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNjIyNykNCj4gICAgICAqIGlndEBpOTE1X3Bt X2JhY2tsaWdodEBiYWQtYnJpZ2h0bmVzczoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjog Tk9UUlVOIC0+IFNLSVAgKGk5MTUjNTM1NCAvIGk5MTUjNzU2MSkNCj4gICAgICAqIGlndEBpOTE1 X3BtX2RjQGRjNS1wc3I6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4g U0tJUCAoaTkxNSM2NTgpDQo+ICAgICAgKiBpZ3RAaTkxNV9wbV9kY0BkYzktZHBtczoNCj4gDQo+ ICAgICAgICAgICAqIHNoYXJkLWFwbDogUEFTUyAtPiBTS0lQIChmZG8jMTA5MjcxKQ0KPiAgICAg ICogaWd0QGk5MTVfcG1fbHBzcEBzY3JlZW5zLWRpc2FibGVkOg0KPiANCj4gICAgICAgICAgICog c2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjODQzMCkNCj4gICAgICAqIGlndEBpOTE1 X3BtX3JwbUBtb2Rlc2V0LW5vbi1scHNwLXN0cmVzczoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJk LWRnMjogUEFTUyAtPiBTS0lQIChpOTE1IzEzOTcpICsxIHNpbWlsYXIgaXNzdWUNCj4gICAgICAq IGlndEBpOTE1X3BtX3JwbUBwYzgtcmVzaWRlbmN5Og0KPiANCj4gICAgICAgICAgICogc2hhcmQt bXRscDogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMDkyOTMpDQo+ICAgICAgKiBpZ3RAaTkxNV9wbV9y cG1Ac3lzdGVtLXN1c3BlbmQtZXhlY2J1ZjoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6 IE5PVFJVTiAtPiBGQUlMIChpOTE1Izc5NDApDQo+ICAgICAgKiBpZ3RAaTkxNV9zdXNwZW5kQGJh c2ljLXMzLXdpdGhvdXQtaTkxNToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogUEFTUyAt PiBGQUlMIChmZG8jMTAzMzc1IC8gaTkxNSM2MTIxKSArMiBzaW1pbGFyDQo+ICAgICAgICAgICAg IGlzc3Vlcw0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IElOQ09NUExF VEUgKGk5MTUjNzQ0MyAvIGk5MTUjODEwMikNCj4gDQo+ICAgICAgKiBpZ3RAaTkxNV9zdXNwZW5k QGRlYnVnZnMtcmVhZGVyOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtYXBsOiBQQVNTIC0+IEFC T1JUIChpOTE1IzE4MCAvIGk5MTUjODIxMykNCj4gICAgICAqIGlndEBpOTE1X3N1c3BlbmRAZmVu Y2UtcmVzdG9yZS10aWxlZDJ1bnRpbGVkOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtc25iOiBO T1RSVU4gLT4gRE1FU0ctV0FSTiAoaTkxNSM4ODQxKSArNCBzaW1pbGFyIGlzc3Vlcw0KPiAgICAg ICogaWd0QGttc19hZGRmYl9iYXNpY0BhZGRmYjI1LXgtdGlsZWQtbGVnYWN5Og0KPiANCj4gICAg ICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNDIxMikNCj4gICAgICAq IGlndEBrbXNfYWRkZmJfYmFzaWNAYmFzaWMteS10aWxlZC1sZWdhY3k6DQo+IA0KPiAgICAgICAg ICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzQyMTUgLyBpOTE1IzUxOTApDQo+ ICAgICAgKiBpZ3RAa21zX2FzeW5jX2ZsaXBzQGNyY0BwaXBlLWEtaGRtaS1hLTM6DQo+IA0KPiAg ICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBGQUlMIChpOTE1IzgyNDcpICszIHNpbWls YXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX2JpZ19mYkA0LXRpbGVkLTE2YnBwLXJvdGF0ZS05 MDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTEx NjE0KQ0KPiAgICAgICogaWd0QGttc19iaWdfZmJANC10aWxlZC04YnBwLXJvdGF0ZS0yNzA6DQo+ IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTExNjE0KSAr MSBzaW1pbGFyIGlzc3VlDQo+ICAgICAgKiBpZ3RAa21zX2JpZ19mYkA0LXRpbGVkLW1heC1ody1z dHJpZGUtMzJicHAtcm90YXRlLTE4MC1hc3luYy1mbGlwOg0KPiANCj4gICAgICAgICAgICogc2hh cmQtbXRscDogUEFTUyAtPiBGQUlMIChpOTE1IzM3NDMpDQo+ICAgICAgKiBpZ3RAa21zX2JpZ19m YkA0LXRpbGVkLW1heC1ody1zdHJpZGUtMzJicHAtcm90YXRlLTE4MC1oZmxpcDoNCj4gDQo+ICAg ICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTExNjE1IC8gaTkxNSM1 Mjg2KQ0KPiAgICAgICogaWd0QGttc19iaWdfZmJANC10aWxlZC1tYXgtaHctc3RyaWRlLTY0YnBw LXJvdGF0ZS0wLWhmbGlwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4gLT4g U0tJUCAoaTkxNSM1Mjg2KSArMSBzaW1pbGFyIGlzc3VlDQo+IA0KPiAgICAgICAgICAgKiBzaGFy ZC1tdGxwOiBQQVNTIC0+IEZBSUwgKGk5MTUjNTEzOCkNCj4gDQo+ICAgICAgKiBpZ3RAa21zX2Jp Z19mYkB4LXRpbGVkLTMyYnBwLXJvdGF0ZS05MDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJr bDogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMTE2MTQgLyBpOTE1IzM2MzgpDQo+ICAgICAgKiBpZ3RA a21zX2JpZ19mYkB4LXRpbGVkLW1heC1ody1zdHJpZGUtNjRicHAtcm90YXRlLTAtaGZsaXAtYXN5 bmMtZmxpcDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBGQUlMIChp OTE1IzM3NDMpDQo+ICAgICAgKiBpZ3RAa21zX2JpZ19mYkB5LXRpbGVkLThicHAtcm90YXRlLTkw Og0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMTE2 MTQpDQo+ICAgICAgKiBpZ3RAa21zX2JpZ19mYkB5Zi10aWxlZC02NGJwcC1yb3RhdGUtOTA6DQo+ IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTEwNzIzKSAr MiBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19iaWdfZmJAeWYtdGlsZWQtYWRkZmIt c2l6ZS1vdmVyZmxvdzoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNL SVAgKGk5MTUjNTE5MCkgKzUgc2ltaWxhciBpc3N1ZXMNCj4gDQo+ICAgICAgICAgICAqIHNoYXJk LXRnbHU6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTExNjE1KSArMSBzaW1pbGFyIGlzc3VlDQo+IA0K PiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM2MTg3KQ0KPiAN Cj4gICAgICAqIGlndEBrbXNfYmlnX2ZiQHlmLXRpbGVkLW1heC1ody1zdHJpZGUtMzJicHAtcm90 YXRlLTE4MC1hc3luYy1mbGlwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVO IC0+IFNLSVAgKGZkbyMxMTE2MTUpICs0IHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21z X2JpZ19mYkB5Zi10aWxlZC1tYXgtaHctc3RyaWRlLTY0YnBwLXJvdGF0ZS0wOg0KPiANCj4gICAg ICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM0NTM4IC8gaTkxNSM1MTkw KSArMyBzaW1pbGFyDQo+ICAgICAgICAgICAgIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19jY3NA cGlwZS1hLWJhZC1waXhlbC1mb3JtYXQteV90aWxlZF9nZW4xMl9tY19jY3M6DQo+IA0KPiAgICAg ICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSMzODg2IC8gaTkxNSM2MDk1 KSArNSBzaW1pbGFyDQo+ICAgICAgICAgICAgIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19jY3NA cGlwZS1hLWNjcy1vbi1hbm90aGVyLWJvLTRfdGlsZWRfbXRsX3JjX2Njc19jYzoNCj4gDQo+ICAg ICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNTM1NCAvIGk5MTUjNjA5 NSkgKzQgc2ltaWxhcg0KPiAgICAgICAgICAgICBpc3N1ZXMNCj4gICAgICAqIGlndEBrbXNfY2Nz QHBpcGUtYS1jcmMtc3ByaXRlLXBsYW5lcy1iYXNpYy15X3RpbGVkX2NjczoNCj4gDQo+ICAgICAg ICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMzY4OSAvIGk5MTUjNTM1NCkg KzEyIHNpbWlsYXINCj4gICAgICAgICAgICAgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX2Njc0Bw aXBlLWEtbWlzc2luZy1jY3MtYnVmZmVyLTRfdGlsZWRfbXRsX3JjX2Njc19jYzoNCj4gDQo+ICAg ICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzUzNTQgLyBpOTE1IzYw OTUpICs4IHNpbWlsYXINCj4gICAgICAgICAgICAgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX2Nj c0BwaXBlLWItYmFkLWF1eC1zdHJpZGUteV90aWxlZF9nZW4xMl9tY19jY3M6DQo+IA0KPiAgICAg ICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzM4ODYgLyBpOTE1IzUzNTQg LyBpOTE1IzYwOTUpDQo+ICAgICAgKiBpZ3RAa21zX2Njc0BwaXBlLWItY2NzLW9uLWFub3RoZXIt Ym8teV90aWxlZF9nZW4xMl9tY19jY3M6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBO T1RSVU4gLT4gU0tJUCAoaTkxNSMzNjg5IC8gaTkxNSMzODg2IC8gaTkxNSM1MzU0IC8NCj4gICAg ICAgICAgICAgaTkxNSM2MDk1KSArMiBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19j Y3NAcGlwZS1iLWNyYy1wcmltYXJ5LWJhc2ljLXlmX3RpbGVkX2NjczoNCj4gDQo+ICAgICAgICAg ICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMzczNCAvIGk5MTUjNTM1NCAvIGk5 MTUjNjA5NSkgKzENCj4gICAgICAgICAgICAgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGtt c19jY3NAcGlwZS1jLWJhZC1hdXgtc3RyaWRlLXlmX3RpbGVkX2NjczoNCj4gDQo+ICAgICAgICAg ICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTExNjE1IC8gaTkxNSMzNjg5IC8g aTkxNSM1MzU0IC8NCj4gICAgICAgICAgICAgaTkxNSM2MDk1KSArMSBzaW1pbGFyIGlzc3VlDQo+ ICAgICAgKiBpZ3RAa21zX2Njc0BwaXBlLWMtYmFkLXJvdGF0aW9uLTkwLTRfdGlsZWRfbXRsX21j X2NjczoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUj NTM1NCkgKzE4IHNpbWlsYXIgaXNzdWVzDQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5P VFJVTiAtPiBTS0lQIChpOTE1IzUzNTQpICs4IHNpbWlsYXIgaXNzdWVzDQo+IA0KPiAgICAgICog aWd0QGttc19jY3NAcGlwZS1jLWJhZC1yb3RhdGlvbi05MC15X3RpbGVkX2dlbjEyX3JjX2Njc19j YzoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMzY4 OSAvIGk5MTUjMzg4NiAvIGk5MTUjNTM1NCkgKzMNCj4gICAgICAgICAgICAgc2ltaWxhciBpc3N1 ZXMNCj4gICAgICAqIGlndEBrbXNfY2NzQHBpcGUtZC1iYWQtcm90YXRpb24tOTAtNF90aWxlZF9k ZzJfcmNfY2NzX2NjOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IFNL SVAgKGk5MTUjMzY4OSAvIGk5MTUjNTM1NCAvIGk5MTUjNjA5NSkgKzkNCj4gICAgICAgICAgICAg c2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBrbXNfY2NzQHBpcGUtZC1jcmMtcHJpbWFyeS1y b3RhdGlvbi0xODAteWZfdGlsZWRfY2NzOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDog Tk9UUlVOIC0+IFNLSVAgKGk5MTUjNjA5NSkgKzE2IHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBp Z3RAa21zX2NoYW1lbGl1bV9hdWRpb0BkcC1hdWRpbzoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJk LXRnbHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1Izc4MjgpICszIHNpbWlsYXIgaXNzdWVzDQo+IA0K PiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM3ODI4KQ0KPiAN Cj4gICAgICAqIGlndEBrbXNfY2hhbWVsaXVtX2NvbG9yQGN0bS0wLTUwOg0KPiANCj4gICAgICAg ICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMTE4MjcpICsxIHNpbWlsYXIg aXNzdWUNCj4gICAgICAqIGlndEBrbXNfY2hhbWVsaXVtX2NvbG9yQGN0bS0wLTc1Og0KPiANCj4g ICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMTE4MjcpDQo+ICAg ICAgKiBpZ3RAa21zX2NoYW1lbGl1bV9jb2xvckBjdG0tYmx1ZS10by1yZWQ6DQo+IA0KPiAgICAg ICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTExODI3KQ0KPiAgICAgICog aWd0QGttc19jaGFtZWxpdW1fZWRpZEBkcC1lZGlkLXN0cmVzcy1yZXNvbHV0aW9uLW5vbi00azoN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNzgyOCkN Cj4gICAgICAqIGlndEBrbXNfY2hhbWVsaXVtX2ZyYW1lc0BoZG1pLWNtcC1wbGFuYXItZm9ybWF0 czoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNzgy OCkgKzEgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGttc19jb250ZW50X3Byb3RlY3Rpb25A bGVnYWN5Og0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJUCAoaTkx NSM3MTE4KSArMiBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19jb250ZW50X3Byb3Rl Y3Rpb25AbWVpX2ludGVyZmFjZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJV TiAtPiBTS0lQIChpOTE1IzgwNjMpDQo+ICAgICAgKiBpZ3RAa21zX2NvbnRlbnRfcHJvdGVjdGlv bkB1ZXZlbnQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChp OTE1IzcxMTgpDQo+ICAgICAgKiBpZ3RAa21zX2N1cnNvcl9jcmNAY3Vyc29yLW9uc2NyZWVuLTUx MngxNzA6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChmZG8j MTA5Mjc5IC8gaTkxNSMzMzU5KQ0KPiAgICAgICogaWd0QGttc19jdXJzb3JfY3JjQGN1cnNvci1v bnNjcmVlbi01MTJ4NTEyOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+ IFNLSVAgKGk5MTUjMzM1OSkgKzEgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGttc19jdXJz b3JfY3JjQGN1cnNvci1yYW5kb20tMzJ4MTA6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxw OiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM4ODE0KQ0KPiAgICAgICogaWd0QGttc19jdXJzb3JfY3Jj QGN1cnNvci1yYW5kb20tNTEyeDUxMjoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5P VFJVTiAtPiBTS0lQIChpOTE1IzMzNTkpDQo+ICAgICAgKiBpZ3RAa21zX2N1cnNvcl9jcmNAY3Vy c29yLXNsaWRpbmctNTEyeDUxMjoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVO IC0+IFNLSVAgKGk5MTUjMzM1OSkgKzIgc2ltaWxhciBpc3N1ZXMNCj4gDQo+ICAgICAgICAgICAq IHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMzM1OSkgKzEgc2ltaWxhciBpc3N1ZQ0K PiANCj4gICAgICAqIGlndEBrbXNfY3Vyc29yX2xlZ2FjeUAyeC1sb25nLWZsaXAtdnMtY3Vyc29y LWxlZ2FjeToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChp OTE1IzM1NDYpDQo+ICAgICAgKiBpZ3RAa21zX2N1cnNvcl9sZWdhY3lAY3Vyc29yYS12cy1mbGlw Yi1sZWdhY3k6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4gU0tJUCAo ZmRvIzEwOTI3NCkgKzMgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBrbXNfY3Vyc29yX2xl Z2FjeUBjdXJzb3JiLXZzLWZsaXBhLXRvZ2dsZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRn MjogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMDkyNzQgLyBpOTE1IzUzNTQpICsxIHNpbWlsYXINCj4g ICAgICAgICAgICAgaXNzdWUNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+ IFNLSVAgKGZkbyMxMTE4MjUpICsxIHNpbWlsYXIgaXNzdWUNCj4gDQo+ICAgICAgKiBpZ3RAa21z X2N1cnNvcl9sZWdhY3lAY3Vyc29yYi12cy1mbGlwYi10b2dnbGU6DQo+IA0KPiAgICAgICAgICAg KiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTA5Mjc0IC8gZmRvIzExMTc2NyAvIGk5 MTUjNTM1NCkNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGZk byMxMTE3NjcgLyBmZG8jMTExODI1KQ0KPiANCj4gICAgICAqIGlndEBrbXNfY3Vyc29yX2xlZ2Fj eUBmbGlwLXZzLWN1cnNvci1hdG9taWMtdHJhbnNpdGlvbnMtdmFyeWluZy1zaXplOg0KPiANCj4g ICAgICAgICAgICogc2hhcmQtYXBsOiBQQVNTIC0+IEZBSUwgKGk5MTUjMjM0NikNCj4gDQo+ICAg ICAgICAgICAqIHNoYXJkLWdsazogUEFTUyAtPiBGQUlMIChpOTE1IzIzNDYpDQo+IA0KPiAgICAg ICogaWd0QGttc19kaXRoZXJAZmItOGJwYy12cy1wYW5lbC02YnBjQHBpcGUtYS1oZG1pLWEtMToN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMzgwNCkN Cj4gICAgICAqIGlndEBrbXNfZHBfYXV4X2RldjoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRn bHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzEyNTcpDQo+ICAgICAgKiBpZ3RAa21zX2RzY0Bkc2Mt d2l0aC1icGMtZm9ybWF0czoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAt PiBTS0lQIChpOTE1IzM1NTUgLyBpOTE1IzM4NDApDQo+ICAgICAgKiBpZ3RAa21zX2RzY0Bkc2Mt d2l0aC1vdXRwdXQtZm9ybWF0czoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJV TiAtPiBTS0lQIChpOTE1IzM4NDApDQo+ICAgICAgKiBpZ3RAa21zX2ZiY29uX2ZidEBwc3I6DQo+ IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzM0NjkpDQo+ IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTEwMTg5IC8g aTkxNSMzOTU1KQ0KPiANCj4gICAgICAqIGlndEBrbXNfZmxpcEAyeC1ibG9ja2luZy1hYnNvbHV0 ZS13Zl92Ymxhbms6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4gU0tJ UCAoZmRvIzEwOTI3NCAvIGk5MTUjMzYzNykgKzIgc2ltaWxhcg0KPiAgICAgICAgICAgICBpc3N1 ZXMNCj4gICAgICAqIGlndEBrbXNfZmxpcEAyeC1mbGlwLXZzLWJsb2NraW5nLXdmLXZibGFuazoN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXNuYjogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMDkyNzEg LyBmZG8jMTExNzY3KQ0KPiAgICAgICogaWd0QGttc19mbGlwQDJ4LWZsaXAtdnMtZmVuY2VzLWlu dGVycnVwdGlibGU6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gU0tJ UCAoaTkxNSM4MzgxKQ0KPiAgICAgICogaWd0QGttc19mbGlwQDJ4LXBsYWluLWZsaXAtZmItcmVj cmVhdGU6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1hcGw6IE5PVFJVTiAtPiBTS0lQIChmZG8j MTA5MjcxKSArMjQgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBrbXNfZmxpcEAyeC1wbGFp bi1mbGlwLWludGVycnVwdGlibGU6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RS VU4gLT4gU0tJUCAoaTkxNSMzNjM3KQ0KPiAgICAgICogaWd0QGttc19mbGlwQDJ4LXdmX3ZibGFu ay10cy1jaGVjay1pbnRlcnJ1cHRpYmxlOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBO T1RSVU4gLT4gU0tJUCAoZmRvIzEwOTI3NCkNCj4gICAgICAqIGlndEBrbXNfZmxpcF9zY2FsZWRf Y3JjQGZsaXAtMzJicHAtNHRpbGUtdG8tMzJicHAtNHRpbGVkZzJyY2Njcy1kb3duc2NhbGluZ0Bw aXBlLWEtdmFsaWQtbW9kZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+ IFNLSVAgKGk5MTUjMjY3MikNCj4gICAgICAqIGlndEBrbXNfZmxpcF9zY2FsZWRfY3JjQGZsaXAt MzJicHAteXRpbGUtdG8tMzJicHAteXRpbGVnZW4xMnJjY2NzLXVwc2NhbGluZ0BwaXBlLWEtZGVm YXVsdC1tb2RlOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAg KGk5MTUjMjY3MikgKzEgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGttc19mbGlwX3NjYWxl ZF9jcmNAZmxpcC02NGJwcC14dGlsZS10by0xNmJwcC14dGlsZS1kb3duc2NhbGluZ0BwaXBlLWEt ZGVmYXVsdC1tb2RlOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNL SVAgKGk5MTUjODgxMCkNCj4gICAgICAqIGlndEBrbXNfZm9yY2VfY29ubmVjdG9yX2Jhc2ljQHBy dW5lLXN0YWxlLW1vZGVzOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+ IFNLSVAgKGk5MTUjNTI3NCkNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+ IFNLSVAgKGk5MTUjNTI3NCkNCj4gDQo+ICAgICAgKiBpZ3RAa21zX2Zyb250YnVmZmVyX3RyYWNr aW5nQGZiYy0xcC1wcmltc2Nybi1zcHItaW5kZmItZHJhdy1tbWFwLWd0dDoNCj4gDQo+ICAgICAg ICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChpOTE1Izg3MDgpICsxIHNpbWlsYXIg aXNzdWUNCj4gICAgICAqIGlndEBrbXNfZnJvbnRidWZmZXJfdHJhY2tpbmdAZmJjLTFwLXByaW1z Y3JuLXNwci1pbmRmYi1mdWxsc2NyZWVuOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBQ QVNTIC0+IEZBSUwgKGk5MTUjNjg4MCkNCj4gICAgICAqIGlndEBrbXNfZnJvbnRidWZmZXJfdHJh Y2tpbmdAZmJjcHNyLTFwLXByaW1zY3JuLXByaS1zaHJmYi1kcmF3LW1tYXAtZ3R0Og0KPiANCj4g ICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSMzMDIzKSArNCBzaW1p bGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19mcm9udGJ1ZmZlcl90cmFja2luZ0BmYmNwc3It MnAtcHJpbXNjcm4tcHJpLXNocmZiLWRyYXctbW1hcC13YzoNCj4gDQo+ICAgICAgICAgICAqIHNo YXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjODcwOCkgKzUgc2ltaWxhciBpc3N1ZXMNCj4g DQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMTE4MjUgLyBp OTE1IzE4MjUpICs4IHNpbWlsYXINCj4gICAgICAgICAgICAgaXNzdWVzDQo+IA0KPiAgICAgICog aWd0QGttc19mcm9udGJ1ZmZlcl90cmFja2luZ0BmYmNwc3ItMnAtc2NuZHNjcm4tcHJpLXNocmZi LWRyYXctcHdyaXRlOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IFNL SVAgKGZkbyMxMDkyODApICsxNCBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19mcm9u dGJ1ZmZlcl90cmFja2luZ0BmYmNwc3ItdGlsaW5nLTQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFy ZC10Z2x1OiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM1NDM5KQ0KPiAgICAgICogaWd0QGttc19mcm9u dGJ1ZmZlcl90cmFja2luZ0Bwc3ItMXAtb2Zmc2NyZW4tcHJpLWluZGZiLWRyYXctbW1hcC1jcHU6 DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4gU0tJUCAoZmRvIzExMDE4 OSkgKzEyIHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX2Zyb250YnVmZmVyX3RyYWNr aW5nQHBzci0xcC1vZmZzY3Jlbi1wcmktc2hyZmItZHJhdy1yZW5kZXI6DQo+IA0KPiAgICAgICAg ICAgKiBzaGFyZC1kZzI6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzM0NTgpICszIHNpbWlsYXIgaXNz dWVzDQo+ICAgICAgKiBpZ3RAa21zX2Zyb250YnVmZmVyX3RyYWNraW5nQHBzci0ycC1zY25kc2Ny bi1wcmktc2hyZmItZHJhdy1tbWFwLWNwdToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6 IE5PVFJVTiAtPiBTS0lQIChpOTE1IzE4MjUpICsxMCBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICog aWd0QGttc19oZHJAYnBjLXN3aXRjaDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IE5P VFJVTiAtPiBTS0lQIChpOTE1IzM1NTUgLyBpOTE1IzgyMjgpDQo+ICAgICAgKiBpZ3RAa21zX2hk ckBicGMtc3dpdGNoLXN1c3BlbmQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5PVFJV TiAtPiBTS0lQIChpOTE1IzM1NTUgLyBpOTE1IzgyMjgpDQo+ICAgICAgKiBpZ3RAa21zX2hkckBz dGF0aWMtdG9nZ2xlOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJ UCAoaTkxNSMzNTU1IC8gaTkxNSM4MjI4KSArMSBzaW1pbGFyDQo+ICAgICAgICAgICAgIGlzc3Vl DQo+ICAgICAgKiBpZ3RAa21zX3BpcGVfYl9jX2l2YkBwaXBlLWItZHBtcy1vZmYtbW9kZXNldC1w aXBlLWM6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4gU0tJUCAoZmRv IzEwOTI4OSkgKzEgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGttc19wbGFuZV9zY2FsaW5n QGludGVsLW1heC1zcmMtc2l6ZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVO IC0+IFNLSVAgKGk5MTUjNjk1MykNCj4gICAgICAqIGlndEBrbXNfcGxhbmVfc2NhbGluZ0BwbGFu ZS1zY2FsZXItd2l0aC1jbGlwcGluZy1jbGFtcGluZy1yb3RhdGlvbkBwaXBlLWEtdmdhLTE6DQo+ IA0KPiAgICAgICAgICAgKiBzaGFyZC1zbmI6IE5PVFJVTiAtPiBTS0lQIChmZG8jMTA5MjcxKSAr MTAxIHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX3BsYW5lX3NjYWxpbmdAcGxhbmUt dXBzY2FsZS13aXRoLXJvdGF0aW9uLWZhY3Rvci0wLTI1QHBpcGUtYS1oZG1pLWEtMToNCj4gDQo+ ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzUxNzYpICsxNSBz aW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGttc19wbGFuZV9zY2FsaW5nQHBsYW5lLXVwc2Nh bGUtd2l0aC1yb3RhdGlvbi1mYWN0b3ItMC0yNUBwaXBlLWEtaGRtaS1hLTI6DQo+IA0KPiAgICAg ICAgICAgKiBzaGFyZC1ya2w6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzUxNzYpICs3IHNpbWlsYXIg aXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX3BsYW5lX3NjYWxpbmdAcGxhbmVzLWRvd25zY2FsZS1m YWN0b3ItMC0yNUBwaXBlLWQtaGRtaS1hLTM6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6 IE5PVFJVTiAtPiBTS0lQIChpOTE1IzUyMzUpICsxNSBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICog aWd0QGttc19wbGFuZV9zY2FsaW5nQHBsYW5lcy11cHNjYWxlLTIweDIwLWRvd25zY2FsZS1mYWN0 b3ItMC0yNUBwaXBlLWItZWRwLTE6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RS VU4gLT4gU0tJUCAoaTkxNSM1MjM1KSArMyBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGtt c19wbGFuZV9zY2FsaW5nQHBsYW5lcy11cHNjYWxlLWZhY3Rvci0wLTI1LWRvd25zY2FsZS1mYWN0 b3ItMC0yNUBwaXBlLWItaGRtaS1hLTI6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IE5P VFJVTiAtPiBTS0lQIChpOTE1IzUyMzUpICszIHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RA a21zX3BzcjJfc2ZAY3Vyc29yLXBsYW5lLW1vdmUtY29udGludW91cy1zZjoNCj4gDQo+ICAgICAg ICAgICAqIHNoYXJkLWFwbDogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMDkyNzEgLyBpOTE1IzY1OCkN Cj4gICAgICAqIGlndEBrbXNfcHNyMl9zdUBmcm9udGJ1ZmZlci14cmdiODg4ODoNCj4gDQo+ICAg ICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNjU4KSArMSBzaW1pbGFy IGlzc3VlDQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBOT1RSVU4gLT4gU0tJUCAoaTkx NSM0MzQ4KQ0KPiANCj4gICAgICAqIGlndEBrbXNfcHNyMl9zdUBwYWdlX2ZsaXAteHJnYjg4ODg6 DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4gU0tJUCAoZmRvIzEwOTY0 MiAvIGZkbyMxMTEwNjggLyBpOTE1IzY1OCkNCj4gICAgICAgICAgICAgKzEgc2ltaWxhciBpc3N1 ZQ0KPiAgICAgICogaWd0QGttc19wc3JAcHJpbWFyeV9tbWFwX2NwdToNCj4gDQo+ICAgICAgICAg ICAqIHNoYXJkLWRnMjogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMTA3MikgKzQgc2ltaWxhciBpc3N1 ZXMNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjMTA3 MikgKzIgc2ltaWxhciBpc3N1ZXMNCj4gDQo+ICAgICAgKiBpZ3RAa21zX3BzckBwc3IyX2N1cnNv cl9ibHQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBQQVNTIC0+IEZBSUwgKGk5MTUj ODcyNikNCj4gICAgICAqIGlndEBrbXNfcHNyQHBzcjJfY3Vyc29yX21tYXBfZ3R0Og0KPiANCj4g ICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAgKGk5MTUjNDA3NykgKzIgc2lt aWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBrbXNfcm1mYkBjbG9zZS1mZEBwaXBlLWEtZWRwLTE6 DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBQQVNTIC0+IERNRVNHLVdBUk4gKGk5MTUj MTk4MikNCj4gICAgICAqIGlndEBrbXNfcm90YXRpb25fY3JjQHByaW1hcnkteS10aWxlZC1yZWZs ZWN0LXgtMjcwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVOIC0+IFNLSVAg KGk5MTUjNDIzNSkNCj4gICAgICAqIGlndEBrbXNfc2NhbGluZ19tb2Rlc0BzY2FsaW5nLW1vZGUt ZnVsbDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1 IzM1NTUpICsyIHNpbWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAa21zX3RpbGVkX2Rpc3BsYXlA YmFzaWMtdGVzdC1wYXR0ZXJuOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVO IC0+IFNLSVAgKGk5MTUjODYyMykNCj4gICAgICAqIGlndEBrbXNfdGlsZWRfZGlzcGxheUBiYXNp Yy10ZXN0LXBhdHRlcm4td2l0aC1jaGFtZWxpdW06DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1t dGxwOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM4NjIzKQ0KPiAgICAgICogaWd0QGttc192YmxhbmtA cGlwZS1jLXF1ZXJ5LWZvcmtlZC1idXN5Og0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBO T1RSVU4gLT4gU0tJUCAoaTkxNSM0MDcwIC8gaTkxNSM2NzY4KQ0KPiAgICAgICogaWd0QGttc192 YmxhbmtAcGlwZS1kLXdhaXQtaWRsZToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogTk9U UlVOIC0+IFNLSVAgKGk5MTUjNDA3MCAvIGk5MTUjNTMzIC8gaTkxNSM2NzY4KQ0KPiAgICAgICog aWd0QGttc193cml0ZWJhY2tAd3JpdGViYWNrLXBpeGVsLWZvcm1hdHM6DQo+IA0KPiAgICAgICAg ICAgKiBzaGFyZC10Z2x1OiBOT1RSVU4gLT4gU0tJUCAoaTkxNSMyNDM3KQ0KPiAgICAgICogaWd0 QHBlcmZAb2EtZXhwb25lbnRzQDAtcmNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWdsazog UEFTUyAtPiBBQk9SVCAoaTkxNSM1MjEzIC8gaTkxNSM3OTQxKQ0KPiAgICAgICogaWd0QHBlcmZf cG11QGV2ZW50LXdhaXRAcmNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJV TiAtPiBTS0lQIChpOTE1Izg4MDcpDQo+ICAgICAgKiBpZ3RAcGVyZl9wbXVAcmM2QG90aGVyLWlk bGUtZ3QwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJUCAoaTkx NSM4NTE2KQ0KPiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogTk9UUlVOIC0+IFNLSVAgKGk5 MTUjODUxNikNCj4gDQo+ICAgICAgKiBpZ3RAcGVyZl9wbXVAcmVuZGVyLW5vZGUtYnVzeS1pZGxl QGNjczA6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBQQVNTIC0+IEZBSUwgKGk5MTUj NDM0OSkgKzcgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEBwcmltZV92Z2VtQGJhc2ljLWd0 dDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzM3 MDggLyBpOTE1IzQwNzcpDQo+ICAgICAgKiBpZ3RAc3lzZnNfaGVhcnRiZWF0X2ludGVydmFsQG5v cHJlZW1wdEBiY3MwOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogUEFTUyAtPiBGQUlM IChpOTE1IzYwMTUpICsxIHNpbWlsYXIgaXNzdWUNCj4gICAgICAqIGlndEBzeXNmc19wcmVlbXB0 X3RpbWVvdXRAdGltZW91dEB2ZWNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IFBB U1MgLT4gQUJPUlQgKGk5MTUjODUyMSkNCj4gICAgICAqIGlndEB2M2QvdjNkX3BlcmZtb25AY3Jl YXRlLXBlcmZtb24tZXhjZWVkOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVO IC0+IFNLSVAgKGk5MTUjMjU3NSkgKzUgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEB2M2Qv djNkX3N1Ym1pdF9jbEB2YWxpZC1zdWJtaXNzaW9uOg0KPiANCj4gICAgICAgICAgICogc2hhcmQt dGdsdTogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMDkzMTUgLyBpOTE1IzI1NzUpICs0IHNpbWlsYXIN Cj4gICAgICAgICAgICAgaXNzdWVzDQo+ICAgICAgKiBpZ3RAdjNkL3YzZF9zdWJtaXRfY3NkQGJh ZC1tdWx0aXN5bmMtaW4tc3luYzoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogTk9UUlVO IC0+IFNLSVAgKGk5MTUjMjU3NSkgKzIgc2ltaWxhciBpc3N1ZXMNCj4gDQo+ICAgICAgICAgICAq IHNoYXJkLXJrbDogTk9UUlVOIC0+IFNLSVAgKGZkbyMxMDkzMTUpICsyIHNpbWlsYXIgaXNzdWVz DQo+IA0KPiAgICAgICogaWd0QHZjNC92YzRfbW1hcEBtbWFwLWJvOg0KPiANCj4gICAgICAgICAg ICogc2hhcmQtZGcyOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM3NzExKSArMyBzaW1pbGFyIGlzc3Vl cw0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBOT1RSVU4gLT4gU0tJUCAoaTkxNSM3NzEx KSArMiBzaW1pbGFyIGlzc3Vlcw0KPiANCj4gICAgICAqIGlndEB2YzQvdmM0X3BlcmZtb25AY3Jl YXRlLXBlcmZtb24tZXhjZWVkOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogTk9UUlVO IC0+IFNLSVAgKGk5MTUjNzcxMSkgKzMgc2ltaWxhciBpc3N1ZXMNCj4gICAgICAqIGlndEB2YzQv dmM0X3B1cmdlYWJsZV9ib0BtYXJrLXVucHVyZ2VhYmxlLXB1cmdlZDoNCj4gDQo+ICAgICAgICAg ICAqIHNoYXJkLXRnbHU6IE5PVFJVTiAtPiBTS0lQIChpOTE1IzI1NzUpICs0IHNpbWlsYXIgaXNz dWVzDQo+ICAgICAgKiBpZ3RAdmdlbV9iYXNpY0BiYWQtcGFkOg0KPiANCj4gICAgICAgICAgICog c2hhcmQtbXRscDogUEFTUyAtPiBETUVTRy1XQVJOIChpOTE1IzIwMTcpDQo+IA0KPiAgICAgUG9z c2libGUgZml4ZXMNCj4gDQo+ICAgICAgKiBpZ3RAZ2VtX2NyZWF0ZUBob2ctY3JlYXRlQHNtZW0w Og0KPiANCj4gICAgICAgICAgICogc2hhcmQtZGcyOiBGQUlMIChpOTE1IzU4OTIgLyBpOTE1Izg3 NTgpIC0+IFBBU1MNCj4gICAgICAqIGlndEBnZW1fZWlvQGhpYmVybmF0ZToNCj4gDQo+ICAgICAg ICAgICAqIHtzaGFyZC1kZzF9OiBBQk9SVCAoaTkxNSM0MzkxIC8gaTkxNSM3OTc1IC8gaTkxNSM4 MjEzKSAtPiBQQVNTDQo+ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfZmFpckBiYXNpYy1wYWNlLXNoYXJl QHJjczA6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1nbGs6IEZBSUwgKGk5MTUjMjg0MikgLT4g UEFTUw0KPiAgICAgICogaWd0QGdlbV9leGVjX2ZhaXJAYmFzaWMtdGhyb3R0bGVAcmNzMDoNCj4g DQo+ICAgICAgICAgICAqIHNoYXJkLXJrbDogRkFJTCAoaTkxNSMyODQyKSAtPiBQQVNTICszIHNp bWlsYXIgaXNzdWVzDQo+ICAgICAgKiBpZ3RAZ2VtX2V4ZWNfd2hpc3BlckBiYXNpYy1jb250ZXh0 cy1mb3JrZWQtYWxsOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogQUJPUlQgKGk5MTUj ODEzMSkgLT4gUEFTUw0KPiAgICAgICogaWd0QGdlbV9leGVjX3doaXNwZXJAYmFzaWMtZmRzLXBy aW9yaXR5LWFsbDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IEZBSUwgKGk5MTUjNjM2 MykgLT4gUEFTUw0KPiAgICAgICogaWd0QGdlbV9sbWVtX3N3YXBwaW5nQHNtZW0tb29tQGxtZW0w Og0KPiANCj4gICAgICAgICAgICoge3NoYXJkLWRnMX06IERNRVNHLVdBUk4gKGk5MTUjNDkzNiAv IGk5MTUjNTQ5MykgLT4gUEFTUw0KPiAgICAgICogaWd0QGk5MTVfaGFuZ21hbkBlbmdpbmUtZW5n aW5lLWhhbmdAdmNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IEZBSUwgKGk5MTUj NzA2OSkgLT4gUEFTUw0KPiAgICAgICogaWd0QGk5MTVfbW9kdWxlX2xvYWRAcmVsb2FkLXdpdGgt ZmF1bHQtaW5qZWN0aW9uOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogQUJPUlQgKGk5 MTUjODQ4OSAvIGk5MTUjODY2OCkgLT4gUEFTUw0KPiAgICAgICogaWd0QGk5MTVfcG1fZGNAZGM5 LWRwbXM6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1OiBTS0lQIChpOTE1IzQyODEpIC0+ IFBBU1MNCj4gICAgICAqIGlndEBpOTE1X3BtX3JjNl9yZXNpZGVuY3lAcmM2LWlkbGVAcmNzMDoN Cj4gDQo+ICAgICAgICAgICAqIHtzaGFyZC1kZzF9OiBGQUlMIChpOTE1IzM1OTEpIC0+IFBBU1Mg KzEgc2ltaWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGk5MTVfcG1fcnBtQGN1cnNvci1kcG1zOg0K PiANCj4gICAgICAgICAgICogc2hhcmQtdGdsdTogRkFJTCAoaTkxNSM3OTQwKSAtPiBQQVNTICsx IHNpbWlsYXIgaXNzdWUNCj4gICAgICAqIGlndEBpOTE1X3BtX3JwbUBkcG1zLW1vZGUtdW5zZXQt bHBzcDoNCj4gDQo+ICAgICAgICAgICAqIHtzaGFyZC1kZzF9OiBTS0lQIChpOTE1IzEzOTcpIC0+ IFBBU1MNCj4gICAgICAqIGlndEBpOTE1X3BtX3JwbUBkcG1zLW5vbi1scHNwOg0KPiANCj4gICAg ICAgICAgICogc2hhcmQtcmtsOiBTS0lQIChpOTE1IzEzOTcpIC0+IFBBU1MgKzEgc2ltaWxhciBp c3N1ZQ0KPiAgICAgICogaWd0QGk5MTVfcG1fcnBtQG1vZGVzZXQtbm9uLWxwc3Atc3RyZXNzLW5v LXdhaXQ6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IFNLSVAgKGk5MTUjMTM5NykgLT4g UEFTUyArMiBzaW1pbGFyIGlzc3Vlcw0KPiAgICAgICogaWd0QGk5MTVfc2VsZnRlc3RAbGl2ZUBn dF9tb2NzOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogRE1FU0ctRkFJTCAoaTkxNSM3 MDU5KSAtPiBQQVNTDQo+ICAgICAgKiBpZ3RAaTkxNV9zZWxmdGVzdEBsaXZlQGhhbmdjaGVjazoN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogQUJPUlQgKGk5MTUjNzkxMykgLT4gUEFTUw0K PiAgICAgICogaWd0QGk5MTVfc2VsZnRlc3RAbGl2ZUB3b3JrYXJvdW5kczoNCj4gDQo+ICAgICAg ICAgICAqIHNoYXJkLW10bHA6IERNRVNHLUZBSUwgKGk5MTUjNjc2MykgLT4gUEFTUw0KPiAgICAg ICogaWd0QGttc19iaWdfZmJAeC10aWxlZC1tYXgtaHctc3RyaWRlLTY0YnBwLXJvdGF0ZS0xODAt aGZsaXAtYXN5bmMtZmxpcDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IEZBSUwgKGk5 MTUjMzc0MykgLT4gUEFTUw0KPiAgICAgICogaWd0QGttc19jdXJzb3JfbGVnYWN5QDJ4LWxvbmct ZmxpcC12cy1jdXJzb3ItYXRvbWljOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZ2xrOiBGQUlM IChpOTE1IzcyKSAtPiBQQVNTDQo+ICAgICAgKiBpZ3RAa21zX2N1cnNvcl9sZWdhY3lAY3Vyc29y LXZzLWZsaXAtdG9nZ2xlOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtbXRscDogRkFJTCAoaTkx NSM4MjQ4KSAtPiBQQVNTDQo+ICAgICAgKiBpZ3RAa21zX2N1cnNvcl9sZWdhY3lAZmxpcC12cy1j dXJzb3ItYXRvbWljLXRyYW5zaXRpb25zOg0KPiANCj4gICAgICAgICAgICogc2hhcmQtZ2xrOiBG QUlMIChpOTE1IzIzNDYpIC0+IFBBU1MNCj4gICAgICAqIGlndEBrbXNfZmxpcEBmbGlwLXZzLWV4 cGlyZWQtdmJsYW5rLWludGVycnVwdGlibGVAYS1oZG1pLWE0Og0KPiANCj4gICAgICAgICAgICog e3NoYXJkLWRnMX06IEZBSUwgKGk5MTUjNzkpIC0+IFBBU1MNCj4gICAgICAqIGlndEBrbXNfZmxp cEBmbGlwLXZzLXN1c3BlbmQtaW50ZXJydXB0aWJsZUBhLWRwMToNCj4gDQo+ICAgICAgICAgICAq IHNoYXJkLWFwbDogQUJPUlQgKGk5MTUjMTgwKSAtPiBQQVNTDQo+ICAgICAgKiBpZ3RAa21zX2Zy b250YnVmZmVyX3RyYWNraW5nQGZiYy0xcC1wcmltc2Nybi1pbmRmYi1wbGZsaXAtYmx0Og0KPiAN Cj4gICAgICAgICAgICogc2hhcmQtZGcyOiBGQUlMIChpOTE1IzY4ODApIC0+IFBBU1MgKzEgc2lt aWxhciBpc3N1ZQ0KPiAgICAgICogaWd0QGttc19wbGFuZV9zY2FsaW5nQGludGVsLW1heC1zcmMt c2l6ZUBwaXBlLWEtaGRtaS1hLTI6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6IEZBSUwg KGk5MTUjODI5MikgLT4gUEFTUw0KPiAgICAgICogaWd0QGttc19zeXNmc19lZGlkX3RpbWluZzoN Cj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogRkFJTCAoSUdUIzIpIC0+IFBBU1MNCj4gICAg ICAqIGlndEBrbXNfdmJsYW5rQHBpcGUtYS10cy1jb250aW51YXRpb24tc3VzcGVuZDoNCj4gDQo+ ICAgICAgICAgICAqIHNoYXJkLWRnMjogRkFJTCAoZmRvIzEwMzM3NSAvIGk5MTUjNjEyMSkgLT4g UEFTUw0KPiAgICAgICogaWd0QHBlcmZfcG11QGJ1c3ktZG91YmxlLXN0YXJ0QGNjczA6DQo+IA0K PiAgICAgICAgICAgKiBzaGFyZC1tdGxwOiBGQUlMIChpOTE1IzQzNDkpIC0+IFBBU1MNCj4gICAg ICAqIGlndEBwZXJmX3BtdUBtb3N0LWJ1c3ktaWRsZS1jaGVjay1hbGxAYmNzMDoNCj4gDQo+ICAg ICAgICAgICAqIHNoYXJkLW10bHA6IEZBSUwgKGk5MTUjNTIzNCkgLT4gUEFTUyArMSBzaW1pbGFy IGlzc3VlDQo+ICAgICAgKiBpZ3RAcGVyZl9wbXVAbW9zdC1idXN5LWlkbGUtY2hlY2stYWxsQHJj czA6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1kZzI6IEZBSUwgKGk5MTUjNTIzNCkgLT4gUEFT Uw0KPiANCj4gICAgICAgICAgICoge3NoYXJkLWRnMX06IEZBSUwgKGk5MTUjNTIzNCkgLT4gUEFT Uw0KPiANCj4gICAgICAqIGlndEBzeXNmc190aW1lc2xpY2VfZHVyYXRpb25AdGltZW91dEB2ZWNz MDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLW10bHA6IEFCT1JUIChpOTE1Izg1MjEpIC0+IFBB U1MNCj4gDQo+ICAgICBXYXJuaW5ncw0KPiANCj4gICAgICAqIGlndEBnZW1fZXhlY19zdXNwZW5k QGJhc2ljLXMwQHNtZW06DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1zbmI6IERNRVNHLUZBSUwg KGZkbyMxMDMzNzUpIC0+IERNRVNHLVdBUk4gKGk5MTUjODg0MSkNCj4gICAgICAqIGlndEBpOTE1 X3BtX3JjNl9yZXNpZGVuY3lAcmM2LWlkbGVAYmNzMDoNCj4gDQo+ICAgICAgICAgICAqIHNoYXJk LXRnbHU6IEZBSUwgKGk5MTUjMjY4MSAvIGk5MTUjMzU5MSkgLT4gV0FSTiAoaTkxNSMyNjgxKQ0K PiAgICAgICogaWd0QGk5MTVfcG1fcmM2X3Jlc2lkZW5jeUByYzYtaWRsZUByY3MwOg0KPiANCj4g ICAgICAgICAgICogc2hhcmQtdGdsdTogV0FSTiAoaTkxNSMyNjgxKSAtPiBGQUlMIChpOTE1IzI2 ODEgLyBpOTE1IzM1OTEpDQo+ICAgICAgKiBpZ3RAaTkxNV9zdXNwZW5kQGJhc2ljLXMyaWRsZS13 aXRob3V0LWk5MTU6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1zbmI6IERNRVNHLVdBUk4gKGk5 MTUjODg0MSkgLT4gQUJPUlQgKGk5MTUjNDUyOCAvDQo+ICAgICAgICAgICAgIGk5MTUjODIxMykN Cj4gICAgICAqIGlndEBrbXNfY29udGVudF9wcm90ZWN0aW9uQG1laV9pbnRlcmZhY2U6DQo+IA0K PiAgICAgICAgICAgKiBzaGFyZC1kZzI6IFNLSVAgKGk5MTUjNzExOCAvIGk5MTUjNzE2MikgLT4g U0tJUCAoaTkxNSM3MTE4KQ0KPiANCj4gICAgICAgICAgICogc2hhcmQtcmtsOiBTS0lQIChmZG8j MTA5MzAwKSAtPiBTS0lQIChpOTE1IzcxMTgpDQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC10Z2x1 OiBTS0lQIChmZG8jMTA5MzAwKSAtPiBTS0lQIChpOTE1IzY5NDQgLyBpOTE1IzcxMTYgLw0KPiAg ICAgICAgICAgICBpOTE1IzcxMTgpDQo+IA0KPiAgICAgICogaWd0QGttc19mb3JjZV9jb25uZWN0 b3JfYmFzaWNAZm9yY2UtbG9hZC1kZXRlY3Q6DQo+IA0KPiAgICAgICAgICAgKiBzaGFyZC1ya2w6 IFNLSVAgKGZkbyMxMDkyODUgLyBpOTE1IzQwOTgpIC0+IFNLSVAgKGZkbyMxMDkyODUpDQo+ICAg ICAgKiBpZ3RAcHJpbWVfbW1hcEB0ZXN0X2FwZXJ0dXJlX2xpbWl0QHRlc3RfYXBlcnR1cmVfbGlt aXQtc21lbToNCj4gDQo+ICAgICAgICAgICAqIHNoYXJkLWRnMjogQ1JBU0ggKGk5MTUjNzMzMSkg LT4gSU5DT01QTEVURSAoaTkxNSM1NDkzKQ0KPiANCj4gICAge25hbWV9OiBUaGlzIGVsZW1lbnQg aXMgc3VwcHJlc3NlZC4gVGhpcyBtZWFucyBpdCBpcyBpZ25vcmVkIHdoZW4NCj4gICAgY29tcHV0 aW5nDQo+ICAgIHRoZSBzdGF0dXMgb2YgdGhlIGRpZmZlcmVuY2UgKFNVQ0NFU1MsIFdBUk5JTkcs IG9yIEZBSUxVUkUpLg0KPiANCj4gQnVpbGQgY2hhbmdlcw0KPiANCj4gICAgICAqIENJOiBDSS0y MDE5MDUyOSAtPiBOb25lDQo+ICAgICAgKiBJR1Q6IElHVF83MzgwIC0+IElHVFBXXzkzODMNCj4g ICAgICAqIFBpZ2xpdDogcGlnbGl0XzQ1MDkgLT4gTm9uZQ0KPiANCj4gICAgQ0ktMjAxOTA1Mjk6 IDIwMTkwNTI5DQo+ICAgIENJX0RSTV8xMzM2OTogMDU5NTE1M2I1YzIzN2Q4M2Y5OTkwZjNjZTQ0 ZDA3MmEyNjJkY2IwZSBADQo+ICAgIGdpdDovL2Fub25naXQuZnJlZWRlc2t0b3Aub3JnL2dmeC1j aS9saW51eA0KPiAgICBJR1RQV185MzgzOiBodHRwczovL2ludGVsLWdmeC1jaS4wMS5vcmcvdHJl ZS9kcm0tdGlwL0lHVFBXXzkzODMvaW5kZXguaHRtbA0KPiAgICBJR1RfNzM4MDogOGU2NWYxMmRl MmZkNTJjMDVkYzQ4ZmRiY2I4Y2ZlODZmNmRlMWE3NSBADQo+ICAgIGh0dHBzOi8vZ2l0bGFiLmZy ZWVkZXNrdG9wLm9yZy9kcm0vaWd0LWdwdS10b29scy5naXQNCj4gICAgcGlnbGl0XzQ1MDk6IGZk YzVhNGNhMTExMjRhYjg0MTNjNzk4ODg5NmVlYzRjOTczMzY2OTQgQA0KPiAgICBnaXQ6Ly9hbm9u Z2l0LmZyZWVkZXNrdG9wLm9yZy9waWdsaXQNCg==