Enable DC3CO with PSR2/PR mode on TGL and for platforms with
display version greater than 35.
Signed-off-by: Jeevan B <jeevan.b@intel.com>
---
tests/intel/kms_pm_dc.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index 507b6168d..10450474a 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -315,19 +315,19 @@ static void check_dc3co_with_videoplayback_like_load(data_t *data)
check_dc_counter(data, IGT_INTEL_CHECK_DC3CO, dc3co_prev_cnt);
}
-static void setup_dc3co(data_t *data)
+static void setup_dc3co(data_t *data, enum psr_mode mode)
{
- data->op_psr_mode = PSR_MODE_2;
+ data->op_psr_mode = mode;
psr_enable(data->drm_fd, data->debugfs_fd, data->op_psr_mode, NULL);
igt_require_f(psr_wait_entry(data->debugfs_fd, data->op_psr_mode, NULL),
- "PSR2 is not enabled\n");
+ "PSR2/PR is not enabled\n");
--> add message like: "PSR2/PR mode is not enabled\n"
}
-static void test_dc3co_vpb_simulation(data_t *data)
+static void test_dc3co_vpb_simulation(data_t *data, enum psr_mode mode)
{
igt_require_dc_counter(data->debugfs_fd, IGT_INTEL_CHECK_DC3CO);
setup_output(data);
- setup_dc3co(data);
+ setup_dc3co(data, mode);
setup_videoplayback(data);
check_dc3co_with_videoplayback_like_load(data);
cleanup_dc3co_fbs(data);
@@ -638,10 +638,26 @@ int igt_main()
igt_describe("In this test we make sure that system enters DC3CO "
"when PSR2 is active and system is in SLEEP state");
- igt_subtest("dc3co-vpb-simulation") {
- igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
- PSR_MODE_2, NULL));
- test_dc3co_vpb_simulation(&data);
+ igt_subtest_with_dynamic("dc3co-vpb-simulation") {
+ int modes[] = {PSR_MODE_2, PR_MODE};
+ const char *append_subtest_name[2] = {
+ "psr2-",
+ "pr-",
-->beter to remove here no trailing dash so that below dynamic_f
call should be execut like : "psr2/pr-dc3co-basic"insteald "psr2/pr--dc3co-basic"
--> here two completly separte arrays are used, it would be better if use them in to single struct array+ };
+
+ for (int i = 0; i < ARRAY_SIZE(modes); i++) {
+ igt_dynamic_f("%s-dc3co-basic", append_subtest_name[i]) {
+ igt_require(psr_sink_support(data.drm_fd, data.debugfs_fd,
+ modes[i], NULL));
+
+ if (modes[i] == PSR_MODE_2)
+ igt_require(IS_TIGERLAKE(data.devid) ||
+ intel_display_ver(data.devid) >= 35);
+ else if (modes[i] == PR_MODE)
+ igt_require(intel_display_ver(data.devid) >= 35);
+ test_dc3co_vpb_simulation(&data, modes[i]);
+ }
+ }
}
igt_describe("This test validates display engine entry to DC5 state "