Re: [PATCH 1/1] tests/xe_eudebug_online: fix thread ID math in pagefault-one-of-many shader

["Hajda, Andrzej" <andrzej.hajda@intel.com>]

W dniu 7.05.2026 o 11:09, Maciej Patelczyk pisze:
> On 28/01/2026 12:39, Jan Maslak wrote:
>

Not sure why the subject jest revived after 3 months. Anyway please 
restrain before merging this patch, see below.


>> Replace the incorrect use of r1.4 (wrong inline field) with explicit 
>> dim.x
>> passed as an argument, then computing tgid.y * dim.x + tgid.x via mul 
>> + add.
>>
>> Signed-off-by: Jan Maslak <jan.maslak@intel.com>
>> ---
>>   tests/intel/xe_eudebug_online.c                   | 5 +++--
>>   tests/intel/xe_eudebug_online.c.gen.iga64_codes.c | 7 ++++---
>>   2 files changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/tests/intel/xe_eudebug_online.c 
>> b/tests/intel/xe_eudebug_online.c
>> index 084bdeb77..9f736af58 100644
>> --- a/tests/intel/xe_eudebug_online.c
>> +++ b/tests/intel/xe_eudebug_online.c
>> @@ -267,12 +267,13 @@ static struct gpgpu_shader *get_shader(struct 
>> online_debug_data *data)
>>       mov (1) r30.4<1>:ud 0x3f:ud
>>       mov (1) r30.7<1>:ud 0x3:ud // 4 bytes
>>       // calculate thread id: r20.0 = dim.x * tgid.y + tgid.x
>> -    mad (1) r20.0<1>:ud r0.1<0;0>:ud r0.6<0;0>:ud r1.4<0>:ud
>> +    mul (1) r20.0<1>:ud r0.6<0;1,0>:ud ARG(1):ud
>> +    add (1) r20.0<1>:ud r20.0<0;1,0>:ud r0.1<0;1,0>:ud
>
> Hm,
>
> mad src0 src1 src2
>
> does the src0 * src1 + src3, right?

No, it does: dst= src0 + src1*src2, see bspec.

>
> dim.x is r1.4, tgid.y r0.6 and tgid.x is r0.1
>
> so it should be mad r1.4 r0.6 r0.1
>
> Macros for those fields should preferably be used.

  IIRC the shader is correct, the only missing thing was passing DIM_X 
via inline fields, and it was fixed already.

Macros are hard to use due to baroque syntax of asm.


Regards

Andrzej


>
>
> Thanks for the catch!
>
> Maciej
>
>
>>       // page-fault only for arbitrary thread
>>       cmp (1) (eq)f0.0 null<1>:ud r20.0<0;1,0>:ud ARG(0):ud
>>   (f0.0)    send.ugm (1) r31 r30 null 0x0 0x2128403 // 
>> load_block2d.ugm.d32t.a64.uc.uc
>>   #endif
>> -            )", data->pf_thread_number);
>> +            )", data->pf_thread_number, data->w_dim.x);
>>             gpgpu_shader__label(shader, 0);
>>           gpgpu_shader__write_dword(shader, SHADER_CANARY, 0);
>> diff --git a/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c 
>> b/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c
>> index 3bd5b0c5f..2fe6bb7d8 100644
>> --- a/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c
>> +++ b/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c
>> @@ -3,7 +3,7 @@
>>     #include "gpgpu_shader.h"
>>   -#define MD5_SUM_IGA64_ASMS f0897ea23eff7ea77569eca6ddd16161
>> +#define MD5_SUM_IGA64_ASMS 7ab1b0da138a90599e4086c2c40269c9
>>     struct iga64_template const iga64_code_store_sr0_0[] = {
>>       { .gen_ver = 2000, .size = 40, .code = (const uint32_t []) {
>> @@ -24,13 +24,14 @@ struct iga64_template const 
>> iga64_code_store_sr0_0[] = {
>>   };
>>     struct iga64_template const iga64_code_pagefault_one_of_many[] = {
>> -    { .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
>> +    { .gen_ver = 2000, .size = 48, .code = (const uint32_t []) {
>>           0x000c0061, 0x1e054330, 0x00000000, 0x00000000,
>>           0x00000061, 0x1e054330, 0x00000123, 0x45678000,
>>           0x00000061, 0x1e254220, 0x00000000, 0x0000003f,
>>           0x00000061, 0x1e454220, 0x00000000, 0x0000003f,
>>           0x00000061, 0x1e754220, 0x00000000, 0x00000003,
>> -        0x0000005b, 0x14040220, 0x02020014, 0x01440064,
>> +        0x00000041, 0x14058220, 0x02000064, 0xc0ded001,
>> +        0x00001940, 0x14050220, 0x02001404, 0x00000014,
>>           0x00001970, 0x00018220, 0x12001404, 0xc0ded000,
>>           0x04032031, 0x1f0c0000, 0xf8061e0c, 0x00a00000,
>>           0x80000001, 0x00010000, 0x20000000, 0x00000000,