Re: [PATCH i-g-t v1] lib/i915/fbc: Disable FBC in case of selective update in xe2lpd

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Thu, 2025-03-20 at 13:09 +0200, Vinod Govindapillai wrote:
> In xe2lpd onwards, FBC and PSR2 selective update should be
> selectively enabled based on the dirty rect threshold. Display
> driver lacks such a logic at the moment and instead disables
> FBC in case selective update is on. So replicate the same
> in related IGT cases as well.

As a name intel_fbc_psr_combo_supported is not specifically referring
PSR2. It is generally PSR. Also checked usage of
intel_fbc_psr_combo_supported and it seems to be used in PSR1-FBC
testcases as well. This will skip those tests as well. I don't think we
want that.

BR,

Jouni Högander

> 
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  lib/i915/intel_fbc.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/lib/i915/intel_fbc.c b/lib/i915/intel_fbc.c
> index 3971e4920..b0b4278ad 100644
> --- a/lib/i915/intel_fbc.c
> +++ b/lib/i915/intel_fbc.c
> @@ -167,11 +167,16 @@ bool intel_fbc_plane_size_supported(int fd,
> uint32_t width, uint32_t height)
>   */
>  bool intel_fbc_psr_combo_supported(int device)
>  {
> -	int ver = intel_display_ver(intel_get_drm_devid(device));
> -
> -	/* In Xe3 FBC PSR combo not supported because of FBC dirty
> rect */
> -	if (ver >= 20 && ver < 30)
> -		return true;
> +	/*
> +	 * Because of some random underruns, FBC is disabled when
> selective
> +	 * update is enabled for xe2lpd onwards. The display driver
> should
> +	 * implement a selection logic between FBC and PSR2 / PR
> selective
> +	 * update from xe2lpd onwards. Until that is implemented,
> keep
> +	 * FBC disabled if PSR2 selective update is on.
> +	 *
> +	 * Though right now this function is empty, keep this for
> the future
> +	 * display version based variations for FBC and PSR
> +	 */
>  
>  	return false;
>  }