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d="scan'208";a="161538705" Received: from orsosgc001.jf.intel.com (HELO orsosgc001.intel.com) ([10.165.21.142]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2025 22:58:21 -0700 Date: Wed, 09 Jul 2025 22:58:20 -0700 Message-ID: <85tt3kk2o3.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Jesse.Zhang Cc: , Vitaly Prosyak , Alex Deucher , Christian Koenig Subject: Re: [PATCH i-g-t 3/4] tests/amdgpu: Add test coverage for all user-mode queues across IP blocks In-Reply-To: <20250708074819.624367-3-Jesse.Zhang@amd.com> References: <20250708074819.624367-1-Jesse.Zhang@amd.com> <20250708074819.624367-3-Jesse.Zhang@amd.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-redhat-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-7 Content-Transfer-Encoding: quoted-printable X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Tue, 08 Jul 2025 00:47:49 -0700, Jesse.Zhang wrote: > > Introduced a new test function, amdgpu_test_all_queues(), to validate > write-linear command submission across all available IP blocks (GFX, Comp= ute, SDMA) > with user-mode queues (UMQ). > > - Adds a dynamic subtest "all-queues-test-with-UMQ" under amdgpu_basic to= ensure > all supported IP queues are exercised individually and in combination. > - Uses the newly added helper amdgpu_command_submission_write_linear_help= er2() to > manage setup, execution, and teardown across multiple IP types. > > This improves test coverage for command submission paths involving user q= ueues > and multi-IP coordination. > > Signed-off-by: Jesse Zhang > --- > tests/amdgpu/amd_basic.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/tests/amdgpu/amd_basic.c b/tests/amdgpu/amd_basic.c > index 8c6b466ce..100a634ce 100644 > --- a/tests/amdgpu/amd_basic.c > +++ b/tests/amdgpu/amd_basic.c > @@ -139,6 +139,14 @@ static void amdgpu_command_submission_sdma(amdgpu_de= vice_handle device, bool use > amdgpu_command_submission_nop(device, AMDGPU_HW_IP_DMA, user_queue); > } > > +static void amdgpu_test_all_queues(amdgpu_device_handle device, bool use= r_queue) > +{ > + amdgpu_command_submission_write_linear_helper2(device, AMDGPU_HW_IP_GFX= , false, user_queue); > + amdgpu_command_submission_write_linear_helper2(device, AMDGPU_HW_IP_COM= PUTE, false, user_queue); > + amdgpu_command_submission_write_linear_helper2(device, AMDGPU_HW_IP_DMA= , false, user_queue); > + amdgpu_command_submission_write_linear_helper2(device, AMDGPU_HW_IP_GFX= |AMDGPU_HW_IP_COMPUTE | > + AMDGPU_HW_IP_DMA, false, user_queue); > +} > /** > * SEMAPHORE > * @param device > @@ -830,6 +838,16 @@ igt_main > amdgpu_command_submission_sdma(device, true); > } > } > + > + igt_describe("Check-all-user-queues-for-write-operation"); > + igt_subtest_with_dynamic("all-queues-test-with-UMQ") { > + if (enable_test && userq_arr_cap[AMD_IP_GFX] && > + userq_arr_cap[AMD_IP_COMPUTE] && > + userq_arr_cap[AMD_IP_DMA]) { > + igt_dynamic_f("all-queues-with-umq") > + amdgpu_test_all_queues(device, true); Please clean up this warning without AMDGPU_USERQ_ENABLED: 636/1531] Compiling C object tests/amdgpu/amd_basic.p/amd_basic.c.o ../tests/amdgpu/amd_basic.c:142:13: warning: =A1amdgpu_test_all_queues=A2 d= efined but not used [-Wunused-function] 142 | static void amdgpu_test_all_queues(amdgpu_device_handle device, boo= l user_queue) | ^~~~~~~~~~~~~~~~~~~~~~ [1526/1529] Generating docs/testplan/intel-ci-tests with a custom command > + } > + } > #endif > > igt_fixture { > -- > 2.49.0 >