From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6791B6E48D for ; Tue, 26 Oct 2021 20:30:20 +0000 (UTC) Date: Tue, 26 Oct 2021 13:30:19 -0700 Message-ID: <8735onmsv8.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" In-Reply-To: <20211026082919.14135-1-zbigniew.kempczynski@intel.com> References: <20211026082919.14135-1-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: quoted-printable Subject: Re: [igt-dev] [PATCH i-g-t] tests/gem_sync: Use softpin path for no-reloc gens List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" To: Zbigniew =?ISO-8859-2?Q?Kempczy=F1ski?= Cc: igt-dev@lists.freedesktop.org List-ID: On Tue, 26 Oct 2021 01:29:19 -0700, Zbigniew Kempczy=F1ski wrote: > > Test uses pre-warming batch which establishes offsets in the kernel > so adding pinned flag + zeroing relocation is enough to run with > softpinning on no-reloc gens. LGTM, but don't we need something similar in switch_ring() too or it needs something different? Reviewed-by: Ashutosh Dixit > Signed-off-by: Zbigniew Kempczy=F1ski > Cc: Ashutosh Dixit > --- > tests/i915/gem_sync.c | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/tests/i915/gem_sync.c b/tests/i915/gem_sync.c > index 6cb00c406..2e9ed9ed8 100644 > --- a/tests/i915/gem_sync.c > +++ b/tests/i915/gem_sync.c > @@ -501,6 +501,7 @@ store_ring(int fd, const intel_ctx_t *ctx, unsigned r= ing, > { > const unsigned int gen =3D intel_gen(intel_get_drm_devid(fd)); > struct intel_engine_data ied; > + bool has_relocs =3D gem_has_relocations(fd); > > ied =3D list_store_engines(fd, ctx, ring); > igt_require(ied.nengines); > @@ -532,10 +533,11 @@ store_ring(int fd, const intel_ctx_t *ctx, unsigned= ring, > gem_execbuf(fd, &execbuf); > > object[0].flags |=3D EXEC_OBJECT_WRITE; > + object[0].flags |=3D has_relocs ? 0 : EXEC_OBJECT_PINNED; > object[1].handle =3D gem_create(fd, 20*1024); > > object[1].relocs_ptr =3D to_user_pointer(reloc); > - object[1].relocation_count =3D 1024; > + object[1].relocation_count =3D has_relocs ? 1024 : 0; > > batch =3D gem_mmap__cpu(fd, object[1].handle, 0, 20*1024, > PROT_WRITE | PROT_READ); > @@ -789,6 +791,7 @@ __store_many(int fd, const intel_ctx_t *ctx, unsigned= ring, > int order[64]; > uint32_t *batch, *b; > int done; > + bool has_relocs =3D gem_has_relocations(fd); > > memset(&execbuf, 0, sizeof(execbuf)); > execbuf.buffers_ptr =3D to_user_pointer(object); > @@ -805,9 +808,10 @@ __store_many(int fd, const intel_ctx_t *ctx, unsigne= d ring, > execbuf.buffer_count =3D 1; > gem_execbuf(fd, &execbuf); > object[0].flags |=3D EXEC_OBJECT_WRITE; > + object[0].flags |=3D has_relocs ? 0 : EXEC_OBJECT_PINNED; > > object[1].relocs_ptr =3D to_user_pointer(reloc); > - object[1].relocation_count =3D 1024; > + object[1].relocation_count =3D has_relocs ? 1024 : 0; > execbuf.buffer_count =3D 2; > > memset(reloc, 0, sizeof(reloc)); > @@ -990,6 +994,7 @@ store_all(int fd, const intel_ctx_t *ctx, int num_chi= ldren, int timeout) > { > const unsigned int gen =3D intel_gen(intel_get_drm_devid(fd)); > struct intel_engine_data ied; > + bool has_relocs =3D gem_has_relocations(fd); > > ied =3D list_store_engines(fd, ctx, ALL_ENGINES); > igt_require(ied.nengines); > @@ -1019,10 +1024,11 @@ store_all(int fd, const intel_ctx_t *ctx, int num= _children, int timeout) > gem_execbuf(fd, &execbuf); > > object[0].flags |=3D EXEC_OBJECT_WRITE; > + object[0].flags |=3D has_relocs ? 0 : EXEC_OBJECT_PINNED; > object[1].handle =3D gem_create(fd, 1024*16 + 4096); > > object[1].relocs_ptr =3D to_user_pointer(reloc); > - object[1].relocation_count =3D 1024; > + object[1].relocation_count =3D has_relocs ? 1024 : 0; > > batch =3D gem_mmap__cpu(fd, object[1].handle, 0, 16*1024 + 4096, > PROT_WRITE | PROT_READ); > -- > 2.26.0 >