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From: Jani Nikula <jani.nikula@intel.com>
To: Kamil Konieczny <kamil.konieczny@linux.intel.com>,
	igt-dev@lists.freedesktop.org
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH i-g-t] xe: Add test to check pci memory barrier capability
Date: Wed, 09 Oct 2024 15:02:10 +0300	[thread overview]
Message-ID: <875xq1a3i5.fsf@intel.com> (raw)
In-Reply-To: <20241009103608.uw7fbirmms2dfv62@kamilkon-desk.igk.intel.com>

On Wed, 09 Oct 2024, Kamil Konieczny <kamil.konieczny@linux.intel.com> wrote:
> Hi Tejas,
> On 2024-10-09 at 15:26:08 +0530, Tejas Upadhyay wrote:
>> We want to make sure that direct mmap mapping of physical
>> page at doorbell space and whole page is accessible in order
>> to use pci memory barrier effect effectively.
>> 
>> This is basic pci memory barrier test to showcase xe driver
>> support for feature. In follow up patches we will have more
>> of corner and negative tests added later.
>> 
>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>> ---
>>  include/drm-uapi/xe_drm.h       |  3 ++
>
> Please send updates to drm-uapi with a separate patch.

Possibly the best way to codify kernel header updates would be to script
them.

This is what I did with intel_vbt_defs.h to automate. Should be pretty
easy to tweak for other headers.

BR,
Jani.


#!/bin/bash

SINCE=962601ac4c78
INFILE=drivers/gpu/drm/i915/display/intel_vbt_defs.h
OUTFILE=tools/intel_vbt_defs.h
KERNEL=$HOME/src/linux
IGT=$HOME/src/intel-gpu-tools


cd $KERNEL

for commit in $(git log --reverse --pretty=%h $SINCE..HEAD -- $INFILE); do
	ref=$(git cite $commit)
	git show $commit:$INFILE > $IGT/$OUTFILE
	cd $IGT
	git commit -as \
	    -m "tools/intel_vbt_decode: sync intel_vbt_defs.h with kernel commit $commit" \
	    -m "Synchronize intel_vbt_defs.h with kernel commit:" \
	    -m "$ref"
	cd -
done


-- 
Jani Nikula, Intel

  reply	other threads:[~2024-10-09 12:02 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-09  9:56 [PATCH i-g-t] xe: Add test to check pci memory barrier capability Tejas Upadhyay
2024-10-09 10:36 ` Kamil Konieczny
2024-10-09 12:02   ` Jani Nikula [this message]
2024-10-09 17:19     ` Kamil Konieczny
2024-10-14  9:35   ` Upadhyay, Tejas
2024-10-09 17:30 ` Kamil Konieczny
2024-10-14  9:44   ` Upadhyay, Tejas
2024-10-23  7:10   ` Upadhyay, Tejas
2024-10-09 23:32 ` ✓ CI.xeBAT: success for " Patchwork
2024-10-09 23:39 ` ✓ Fi.CI.BAT: " Patchwork
2024-10-10 13:50 ` ✗ CI.xeFULL: failure " Patchwork
2024-10-11  5:55 ` ✗ Fi.CI.IGT: " Patchwork

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