From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C87B6EAA7 for ; Sat, 30 Oct 2021 03:55:41 +0000 (UTC) Date: Fri, 29 Oct 2021 20:55:40 -0700 Message-ID: <87h7czb1z7.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" In-Reply-To: <20211028182322.34133-3-zbigniew.kempczynski@intel.com> References: <20211028182322.34133-1-zbigniew.kempczynski@intel.com> <20211028182322.34133-3-zbigniew.kempczynski@intel.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: quoted-printable Subject: Re: [igt-dev] [PATCH i-g-t 2/2] tests/gem_sync: Use softpin path for no-reloc gens List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" To: Zbigniew =?ISO-8859-2?Q?Kempczy=F1ski?= Cc: igt-dev@lists.freedesktop.org List-ID: On Thu, 28 Oct 2021 11:23:22 -0700, Zbigniew Kempczy=F1ski wrote: > > @@ -384,6 +401,8 @@ active_wakeup_ring(int fd, const intel_ctx_t *ctx, un= signed ring, > int timeout, int wlen) > { > struct intel_engine_data ied; > + uint64_t ahnd0 =3D get_reloc_ahnd(fd, 0); > + uint64_t ahnd =3D get_reloc_ahnd(fd, ctx->id); > > ied =3D list_store_engines(fd, ctx, ring); > igt_require(ied.nengines); > @@ -397,8 +416,14 @@ active_wakeup_ring(int fd, const intel_ctx_t *ctx, u= nsigned ring, > unsigned long cycles; > igt_spin_t *spin[2]; > > + ahnd0 =3D get_reloc_ahnd(fd, 0); > + ahnd =3D get_reloc_ahnd(fd, ctx->id); > + > memset(&object, 0, sizeof(object)); > object.handle =3D gem_create(fd, 4096); > + object.offset =3D get_offset(ahnd, object.handle, 4096, 0); > + if (ahnd) > + object.offset =3D EXEC_OBJECT_PINNED; > gem_write(fd, object.handle, 0, &bbe, sizeof(bbe)); > > memset(&execbuf, 0, sizeof(execbuf)); > @@ -408,12 +433,14 @@ active_wakeup_ring(int fd, const intel_ctx_t *ctx, = unsigned ring, > execbuf.rsvd1 =3D ctx->id; > > spin[0] =3D __igt_spin_new(fd, > + .ahnd =3D ahnd, > .engine =3D execbuf.flags, > .flags =3D (IGT_SPIN_POLL_RUN | > IGT_SPIN_FAST)); > igt_assert(igt_spin_has_poll(spin[0])); > > spin[1] =3D __igt_spin_new(fd, > + .ahnd =3D ahnd, > .engine =3D execbuf.flags, > .flags =3D (IGT_SPIN_POLL_RUN | > IGT_SPIN_FAST)); > @@ -490,8 +517,13 @@ active_wakeup_ring(int fd, const intel_ctx_t *ctx, u= nsigned ring, > igt_spin_free(fd, spin[1]); > igt_spin_free(fd, spin[0]); > gem_close(fd, object.handle); > + put_offset(ahnd, object.handle); > + put_ahnd(ahnd); > + put_ahnd(ahnd0); > } > igt_waitchildren_timeout(2*timeout, NULL); > + put_ahnd(ahnd); > + put_ahnd(ahnd0); > igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0); > } Sorry don't see ahnd0 being used in active_wakeup_ring() above? Rest looks fine but please let me know about this one issue. Thanks.