From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1963C30653 for ; Thu, 4 Jul 2024 19:14:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D29C10E9FA; Thu, 4 Jul 2024 19:14:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="fUxXCOpo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C9C510EA00 for ; Thu, 4 Jul 2024 19:14:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720120449; x=1751656449; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=tO60B0HkvTJf8fSPwubgXAXeYjF9bFJnhQJ346nzsKk=; b=fUxXCOpoUC7vbHsUCBsEfM1PgIjKCl8a6urHaJaSASy3jnHX0nlPqsBM r/KPG2k4DM2QHrhT7zo2SOqzLGw6gybQyVmficFA3Te949WTPCwlwA//m qV70mLml83A9AKIx9Q9GSk73o4ckyObBF8iC9FPqquWnBRaKQDWFcZ+a8 4lxmgzb/ZHX3ubztELkzLVHjFr2RviWI1A0N3tNLpFb0j4VPXue70o119 Z7+Xdyr317Idi/zJx6Co2Vho5sQvpfDdShAfkUu2a18zMjC6ZLig1QfuR ge3r9E/FDQ4uB3d22/xZUZJzO4GCm83X+HGltU5qoZQSKpgk+zShvYjMF w==; X-CSE-ConnectionGUID: JEyGn6u7R9OnPrGu+atWrA== X-CSE-MsgGUID: 6W4JNOtgTd2jvZ2TQhoTFw== X-IronPort-AV: E=McAfee;i="6700,10204,11123"; a="42835719" X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="42835719" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2024 12:14:09 -0700 X-CSE-ConnectionGUID: SPxi1gqSQSapFcIvu8Hyug== X-CSE-MsgGUID: Vy8GUIfXSMuRdP3clRuBPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,183,1716274800"; d="scan'208";a="47326575" Received: from rtatoosk-mobl2.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.125.129.72]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2024 12:14:10 -0700 Date: Thu, 04 Jul 2024 12:12:20 -0700 Message-ID: <87ikxl9dkb.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Cc: Subject: Re: [PATCH i-g-t] lib/i915/perf: Add ARL support in IGT perf library In-Reply-To: <20240703224405.3172164-1-umesh.nerlige.ramappa@intel.com> References: <20240703224405.3172164-1-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.3 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Wed, 03 Jul 2024 15:44:05 -0700, Umesh Nerlige Ramappa wrote: > > Add ARL PCI ids for ARL in IGT perf library. > > Resolves: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11356 > Signed-off-by: Umesh Nerlige Ramappa > --- > lib/i915/perf.c | 32 ++++++++++++++++++++++++++++++++ > lib/i915_pciids_local.h | 18 ++++++++++++++++++ > 2 files changed, 50 insertions(+) > > diff --git a/lib/i915/perf.c b/lib/i915/perf.c > index ee950b3c0..ef2f74be8 100644 > --- a/lib/i915/perf.c > +++ b/lib/i915/perf.c > @@ -230,6 +230,34 @@ is_mtl_gt3(const struct intel_perf_devinfo *devinfo) > return false; > } > > +static bool > +is_arl_gt1(const struct intel_perf_devinfo *devinfo) > +{ > + static const uint32_t devids[] = { > + INTEL_ARL_GT1_IDS(ID), > + }; > + for (uint32_t i = 0; i < ARRAY_SIZE(devids); i++) { > + if (devids[i] == devinfo->devid) > + return true; > + } > + > + return false; > +} > + > +static bool > +is_arl_gt2(const struct intel_perf_devinfo *devinfo) > +{ > + static const uint32_t devids[] = { > + INTEL_ARL_GT2_IDS(ID), > + }; > + for (uint32_t i = 0; i < ARRAY_SIZE(devids); i++) { > + if (devids[i] == devinfo->devid) > + return true; > + } > + > + return false; > +} > + > struct intel_perf * > intel_perf_for_devinfo(uint32_t device_id, > uint32_t revision, > @@ -432,6 +460,10 @@ intel_perf_for_devinfo(uint32_t device_id, > intel_perf_load_metrics_mtlgt2(perf); > else if (is_mtl_gt3(&perf->devinfo)) > intel_perf_load_metrics_mtlgt3(perf); > + else if (is_arl_gt1(&perf->devinfo)) > + intel_perf_load_metrics_mtlgt2(perf); > + else if (is_arl_gt2(&perf->devinfo)) > + intel_perf_load_metrics_mtlgt3(perf); Bspec 55420 says MTL has gt1 and gt2 instead of gt2 and gt3 here? > else > return unsupported_i915_perf_platform(perf); > } else { > diff --git a/lib/i915_pciids_local.h b/lib/i915_pciids_local.h > index 92879704a..c404a51af 100644 > --- a/lib/i915_pciids_local.h > +++ b/lib/i915_pciids_local.h > @@ -31,6 +31,24 @@ > INTEL_MTL_P_GT3_IDS(MACRO__, ## __VA_ARGS__) > #endif > > +#ifndef INTEL_ARL_GT1_IDS > +#define INTEL_ARL_GT1_IDS(MACRO__, ...) \ > + MACRO__(0x7D41, ## __VA_ARGS__), \ > + MACRO__(0x7D67, ## __VA_ARGS__) > +#endif > + > +#ifndef INTEL_ARL_GT2_IDS > +#define INTEL_ARL_GT2_IDS(MACRO__, ...) \ > + MACRO__(0x7D51, ## __VA_ARGS__), \ > + MACRO__(0x7DD1, ## __VA_ARGS__) > +#endif OK, these match Bspec 55420 for ARL GT1 and GT2. Since ARL is not distinguished from MTL in the kernel, another idea would be add ARL ID's to MTL ID's directly, but maybe maintaining separate ID's is better? > + > +#ifndef INTEL_ARL_IDS > +#define INTEL_ARL_IDS(MACRO__, ...) \ > + INTEL_ARL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ > + INTEL_ARL_GT2_IDS(MACRO__, ## __VA_ARGS__) > +#endif > + > /* PVC */ > #ifndef INTEL_PVC_IDS > #define INTEL_PVC_IDS(MACRO__, ...) \ > -- > 2.38.1 > In any case, LGTM: Reviewed-by: Ashutosh Dixit