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Nishit, is this change related to Wa_14026539277? If so, with the recent merge of the workaround code in the KMD, 2-way-coherent PAT entries will be marked as reserved and you could check that instead. We did a similar check in the recently merged commit b3b6bb81f007 ("intel: Implement Wa_14026539277"), by avoiding using PAT entries with the rsvd field set to true in the xe_pat test. -- Gustavo > >> Signed-off-by: Nishit Sharma >> --- >> tests/intel/xe_exec_system_allocator.c | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> >> diff --git a/tests/intel/xe_exec_system_allocator.c b/tests/intel/xe_exec_system_allocator.c >> index 45ec62813..2519b9e62 100644 >> --- a/tests/intel/xe_exec_system_allocator.c >> +++ b/tests/intel/xe_exec_system_allocator.c >> @@ -1216,6 +1216,22 @@ xe_vm_madvixe_pat_attr(int fd, uint32_t vm, uint64_t addr, uint64_t range, >> DRM_XE_MEM_RANGE_ATTR_PAT, pat_index, 0, 0); >> } >> >> +static bool pat_idx_unsupported_by_wa(int fd, uint8_t pat_idx) >> +{ >> + struct intel_pat_cache pat = {}; >> + int32_t n; >> + >> + if (intel_graphics_ver(intel_get_drm_devid(fd)) < IP_VER(35, 0) || >> + xe_has_vram(fd)) >> + return false; >> + >> + n = xe_get_pat_sw_config(fd, &pat, 0); >> + if (n <= pat_idx) >> + return false; >> + >> + return (pat.entries[pat_idx].pat & 0x3) == 3; >> +} >> + >> static void >> xe_vm_madvise_atomic_attr(int fd, uint32_t vm, uint64_t addr, uint64_t range, >> int mem_attr) >> @@ -2887,6 +2903,9 @@ int igt_main() >> if (IS_PONTEVECCHIO(dev_id) && >> strstr(s->name, "madvise-pat-idx-uc-comp-")) >> igt_skip("Skipping compression-related PAT index on PVC\n"); >> + >> + igt_skip_on_f(pat_idx_unsupported_by_wa(fd, s->fn(fd)), >> + "2-way coherent PAT index not allowed\n"); >> xe_for_each_engine(fd, hwe) >> test_exec(fd, hwe, 1, 1, SZ_4M, 0, 0, NULL, NULL, s->flags, s->fn); >> } >> -- >> 2.43.0 >>