From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B357F10EAD4 for ; Thu, 6 Apr 2023 05:24:35 +0000 (UTC) Date: Wed, 05 Apr 2023 22:24:34 -0700 Message-ID: <87pm8hoa5p.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Vikas Srivastava In-Reply-To: <20230331124717.3005947-1-vikas.srivastava@intel.com> References: <20230331124717.3005947-1-vikas.srivastava@intel.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [igt-dev] [PATCH i-g-t v4] tests/i915: skip gem_set_caching call for mtl List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: igt-dev@lists.freedesktop.org Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" List-ID: On Fri, 31 Mar 2023 05:47:17 -0700, Vikas Srivastava wrote: > > diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c > index 1ab41ab6d6..ebd8a2f36f 100644 > --- a/lib/ioctl_wrappers.c > +++ b/lib/ioctl_wrappers.c > @@ -1297,3 +1297,17 @@ bool igt_has_drm_cap(int fd, uint64_t capability) > igt_assert(drmIoctl(fd, DRM_IOCTL_GET_CAP, &cap) == 0); > return cap.value; > } > + > +/** > + * igt_has_set_caching: > + * @devid: platform id. > + * > + * This helper verifies if the passed platform id > + * has support for setting cache. > + * > + * Returns: Whether the cache setting is supported or not. > + */ > +bool igt_has_set_caching(uint32_t devid) > +{ > + return IS_METEORLAKE(devid) ? false : true; Can we include the gem_has_lmem condition below here too? > +} > diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h > index e4d7c0d408..4c232078d0 100644 > --- a/lib/ioctl_wrappers.h > +++ b/lib/ioctl_wrappers.h > @@ -145,6 +145,7 @@ void prime_sync_end(int dma_buf_fd, bool write); > bool igt_has_fb_modifiers(int fd); > void igt_require_fb_modifiers(int fd); > bool igt_has_drm_cap(int fd, uint64_t capability); > +bool igt_has_set_caching(uint32_t devid); > > /** > * __kms_addfb: > diff --git a/tests/i915/gem_caching.c b/tests/i915/gem_caching.c > index eb0170abca..d0c7aa035f 100644 > --- a/tests/i915/gem_caching.c > +++ b/tests/i915/gem_caching.c > @@ -158,6 +158,11 @@ igt_main > igt_info("coherency broken on i965g/gm\n"); > flags = 0; > } > + > + if (!gem_has_lmem(data.fd)) > + igt_require_f(igt_has_set_caching(data.devid), > + " cache setting not supported on this target\n"); > + > data.bops = buf_ops_create(data.fd); > > scratch_buf = intel_buf_create(data.bops, BO_SIZE/4, 1,