From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CE93F47CCE for ; Thu, 5 Mar 2026 20:39:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FA37892AA; Thu, 5 Mar 2026 20:39:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m0AmcpQ1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46B2710EC79 for ; Thu, 5 Mar 2026 20:39:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772743157; x=1804279157; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version:content-transfer-encoding; bh=CW3vKm1xdwnJNXakwEXxHz0OvmHJrEStG2WZffyfpz4=; b=m0AmcpQ15gTOzjC1oNcp1v/0JVfJh8HKgTxH+aflYoFmUAYKFPUBySTX 3tJyARE3hbxJvJZuB3AQ+2SOnugWKQdHFhprysEJPi+ehf3tdlPO6g3hn PsxAJef48TQs1ZcGCVtvwUmfu3zzdkDl2BJXA9aD4nXF8puYuDGUE7shG QOa5iKn39d5DaqpqOlQ7DI8NwwAFs5YdOXOoBN4+9WNVON3wUq7UZp6un ravEaf025fYn4MNi6VkOAQQSAX3godFZIVnXj4h980pISjhbx3EesSdia ak1XGfms1mW3vp3KQ+FfNWazT5yG0In/vDGkaEd87/Uep2bWZImFe1CkS w==; X-CSE-ConnectionGUID: 8fWr3FIHTkOTZR/oXeSyJw== X-CSE-MsgGUID: ygHmDSb8RYaVfRGPYBcX8A== X-IronPort-AV: E=McAfee;i="6800,10657,11720"; a="85316721" X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="85316721" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 12:39:16 -0800 X-CSE-ConnectionGUID: 2b8eYJboTEu9v80CFg/9rg== X-CSE-MsgGUID: ZoecYzKHShi3qVpqL+cwzg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,103,1770624000"; d="scan'208";a="218747096" Received: from ashisha1-mobl1.amr.corp.intel.com (HELO adixit-MOBL3.intel.com) ([10.125.98.196]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2026 12:39:15 -0800 Date: Thu, 05 Mar 2026 12:39:14 -0800 Message-ID: <87qzpyroy5.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Cc: , , , Subject: Re: [PATCH v4 i-g-t] lib/intel_pat: Cache PAT config for unprivileged processes In-Reply-To: <20260305185431.6515-1-himanshu.girotra@intel.com> References: <20260305185431.6515-1-himanshu.girotra@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Thu, 05 Mar 2026 10:54:31 -0800, wrote: > > From: Himanshu Girotra > > Commit 4e59b8e7779b ("lib/intel_pat: use kernel debugfs as > authoritative PAT source for Xe") changed the Xe PAT lookup to > read from debugfs, which requires root access. Some xe_oa subtests > fork a child process that drops root privileges before performing > GPU operations that internally need the PAT write-back index. > After dropping root, the debugfs read fails. > > Fix this by caching the PAT configuration in struct xe_device at > xe_device_get() time. Since xe_device_get() is called while still > root, the cache is available to forked children even after > igt_drop_root(). Tests that open a new fd after forking must call > xe_device_get() explicitly before dropping root to populate the > cache for that fd. > > v2: Cache PAT in struct xe_device instead of a global static; > drop the intel_pat_precache() helper =E2=80=94 xe_device_get() already > populates the cache, so call it directly in xe_oa before > igt_drop_root() (Ashutosh Dixit) > > v3: Use pat_cache pointer, NULL indicates unpopulated cache; > remove redundant xe_oa.c change (Ashutosh Dixit) > > Add FIXME for multi-GPU (Zbigniew Kempczy=C5=84ski) > > v4: nit fixes and use forward declaration in xe_query.h (Ashutosh Dixit) Reviewed-by: Ashutosh Dixit > > Cc: Matt Roper > Cc: Xin Wang > Cc: Nishit Sharma > Cc: Ashutosh Dixit > Cc: Zbigniew Kempczy=C5=84ski > > Reviewed-by: Zbigniew Kempczy=C5=84ski > Signed-off-by: Himanshu Girotra > --- > lib/intel_pat.c | 17 +++++++++-------- > lib/xe/xe_query.c | 20 ++++++++++++++++++++ > lib/xe/xe_query.h | 5 +++++ > 3 files changed, 34 insertions(+), 8 deletions(-) > > diff --git a/lib/intel_pat.c b/lib/intel_pat.c > index 8660a2515..9feeeb39d 100644 > --- a/lib/intel_pat.c > +++ b/lib/intel_pat.c > @@ -6,6 +6,7 @@ > #include > #include "igt.h" > #include "intel_pat.h" > +#include "xe/xe_query.h" > > /** > * xe_get_pat_sw_config - Helper to read PAT (Page Attribute Table) soft= ware configuration > @@ -99,17 +100,17 @@ static void intel_get_pat_idx(int fd, struct intel_p= at_cache *pat) > uint16_t dev_id; > > /* > - * For Xe driver, query the kernel's PAT software configuration > - * via debugfs. The kernel is the authoritative source for PAT > - * indices, accounting for platform-specific workarounds > - * (e.g. Wa_16023588340) at runtime. > + * For Xe, use the PAT cache stored in struct xe_device. > + * xe_device_get() populates the cache while still root; forked > + * children that inherit the xe_device can use it post-drop_root(). > */ > if (is_xe_device(fd)) { > - int32_t parsed =3D xe_get_pat_sw_config(fd, pat); > + struct xe_device *xe_dev =3D xe_device_get(fd); > > - igt_assert_f(parsed > 0, > - "Failed to get PAT sw_config from debugfs (parsed=3D%d)\n", > - parsed); > + igt_assert_f(xe_dev->pat_cache, > + "PAT sw_config not available -- " > + "debugfs not accessible (missing root or not mounted?)\n"); > + *pat =3D *xe_dev->pat_cache; > return; > } > > diff --git a/lib/xe/xe_query.c b/lib/xe/xe_query.c > index 981d76948..3afca353e 100644 > --- a/lib/xe/xe_query.c > +++ b/lib/xe/xe_query.c > @@ -21,6 +21,7 @@ > #include "drmtest.h" > #include "ioctl_wrappers.h" > #include "igt_map.h" > +#include "intel_pat.h" > > #include "xe_query.h" > #include "xe_ioctl.h" > @@ -235,6 +236,7 @@ static void xe_device_free(struct xe_device *xe_dev) > free(xe_dev->mem_regions); > free(xe_dev->vram_size); > free(xe_dev->eu_stall); > + free(xe_dev->pat_cache); > free(xe_dev); > } > > @@ -299,6 +301,24 @@ struct xe_device *xe_device_get(int fd) > xe_dev->default_alignment =3D __mem_default_alignment(xe_dev->mem_regions= ); > xe_dev->has_vram =3D __mem_has_vram(xe_dev->mem_regions); > > + /* > + * Populate the PAT cache while we still have sufficient privileges > + * to read debugfs. Forked children that inherit this xe_device > + * (via fork()) will be able to use the cached values even after > + * dropping root with igt_drop_root(). pat_cache is left NULL if > + * debugfs is not accessible. > + * > + * FIXME: the cache is keyed by fd; for multi-GPU support this > + * should be extended to cache PAT entries by platform version/ > + * revision instead. > + */ > + xe_dev->pat_cache =3D calloc(1, sizeof(*xe_dev->pat_cache)); > + igt_assert(xe_dev->pat_cache); > + if (xe_get_pat_sw_config(xe_dev->fd, xe_dev->pat_cache) <=3D 0) { > + free(xe_dev->pat_cache); > + xe_dev->pat_cache =3D NULL; > + } > + > /* We may get here from multiple threads, use first cached xe_dev */ > pthread_mutex_lock(&cache.cache_mutex); > prev =3D find_in_cache_unlocked(fd); > diff --git a/lib/xe/xe_query.h b/lib/xe/xe_query.h > index d7a9f95f9..05e2ad84f 100644 > --- a/lib/xe/xe_query.h > +++ b/lib/xe/xe_query.h > @@ -20,6 +20,8 @@ > #define XE_DEFAULT_ALIGNMENT SZ_4K > #define XE_DEFAULT_ALIGNMENT_64K SZ_64K > > +struct intel_pat_cache; > + > struct xe_device { > /** @fd: xe fd */ > int fd; > @@ -74,6 +76,9 @@ struct xe_device { > > /** @dev_id: Device id of xe device */ > uint16_t dev_id; > + > + /** @pat_cache: cached PAT index configuration, NULL if not yet populat= ed */ > + struct intel_pat_cache *pat_cache; > }; > > #define xe_for_each_engine(__fd, __hwe) \ > -- > 2.50.1 >