From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DC20EFCE22 for ; Thu, 5 Mar 2026 00:24:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2277310EAE0; Thu, 5 Mar 2026 00:24:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CMAdll30"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F03B10EAED for ; Thu, 5 Mar 2026 00:24:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772670275; x=1804206275; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=uVr2CKB8iO4jtndbrH/w0AuAfSRvUccNfVFvAIgvmYo=; b=CMAdll30srOMQ+ycCGA6HUuvv7XkfGxfPxuEXDs0oMRtbhEmJyVlbl6v JCT1UG9eyui4690RPSg6BVX4ki3sm8+qE5Oklq/Gp+ymUickRqfXTTZqA DsV7cqVgZeHwmQ2ZKpA/VHHNXVUgkFlCPVoMIeqa9pfb/zHSJG4V8/sFb BaVcbSu0ElqFMAtm/JtFtwW8Yxty7524Dh8Gott+3zaIcRig5bCMTdLTR 5LcCcq0tkS6VvFuVu5T/9q4z3830+L3kA39ZCY7ZjzAsZnjpDclTsaLXu qpdNmyrt/zKH6ZFEMEJz71+kRw5XZ5VIJYXmitrpBWjoG7fxBS9+/t4Ox w==; X-CSE-ConnectionGUID: AzhV+Xp5RxSlyZNObPFymA== X-CSE-MsgGUID: qHNrslo5Rvmiu3MkkFm0Wg== X-IronPort-AV: E=McAfee;i="6800,10657,11719"; a="99214629" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="99214629" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2026 16:24:35 -0800 X-CSE-ConnectionGUID: VGZBiCblSbezTWReeLCgSw== X-CSE-MsgGUID: iG1gQjoqRtCn8yrGeSzTNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="218495326" Received: from unknown (HELO adixit-MOBL3.intel.com) ([10.241.243.162]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2026 16:24:35 -0800 Date: Wed, 04 Mar 2026 16:24:33 -0800 Message-ID: <87qzpz5dj2.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: himanshu.girotra@intel.com Cc: igt-dev@lists.freedesktop.org, nishit.sharma@intel.com Subject: Re: [PATCH i-g-t] lib/intel_pat: Cache PAT config for unprivileged processes In-Reply-To: <20260301153553.23708-1-himanshu.girotra@intel.com> References: <20260301153553.23708-1-himanshu.girotra@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Sun, 01 Mar 2026 07:35:53 -0800, himanshu.girotra@intel.com wrote: > > diff --git a/lib/intel_pat.c b/lib/intel_pat.c > index 8660a2515..16dfc0217 100644 > --- a/lib/intel_pat.c > +++ b/lib/intel_pat.c > @@ -7,6 +7,16 @@ > #include "igt.h" > #include "intel_pat.h" > > +/* > + * Global PAT cache. PAT configuration is a hardware/driver property that > + * does not change over the lifetime of a device, so we cache the result of > + * the first successful query. This allows unprivileged processes (e.g. > + * after igt_drop_root()) to use the cached values without needing debugfs > + * access. > + */ > +static struct intel_pat_cache pat_cache; > +static bool pat_cached; This is not correct. The cache should be maintained as part of 'struct xe_device'. All tests, include xe_oa, already call xe_device_get(). The code in lib/intel_pat.c can also call xe_device_get() to check if pat entries are cached. > diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c > index 927f3f4f2..37449c87c 100644 > --- a/tests/intel/xe_oa.c > +++ b/tests/intel/xe_oa.c > @@ -27,6 +27,7 @@ > #include "xe/xe_ioctl.h" > #include "xe/xe_query.h" > #include "xe/xe_oa.h" > +#include "intel_pat.h" > > /** > * TEST: perf > @@ -5094,6 +5095,15 @@ int igt_main_args("b:t", long_options, help_str, opt_handler, NULL) > write_u64_file("/proc/sys/dev/xe/observation_paranoid", 1); > > render_copy = igt_get_render_copyfunc(drm_fd); > + > + /* > + * Pre-cache PAT configuration while we still have root > + * privileges. Several subtests fork a child that drops > + * root before using bufops/intel_bb, which internally > + * needs the PAT WB index. Without this, the child would > + * fail to read debugfs after dropping privileges. > + */ > + intel_pat_precache(drm_fd); As mentioned above, this is not needed if the cache is maintained as part of 'struct xe_device' since xe_device_get() is being called above.