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d="scan'208";a="127086378" Received: from mkuoppal-desk.fi.intel.com (HELO localhost) ([10.237.72.193]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 09:04:14 -0800 From: Mika Kuoppala To: Dominik Karol =?utf-8?Q?Pi=C4=85tkowski?= , igt-dev@lists.freedesktop.org Cc: Dominik Karol =?utf-8?Q?Pi=C4=85tkowski?= Subject: Re: [PATCH i-g-t 1/1] tests/intel/xe_eudebug_online: Improve writes-caching-* tests In-Reply-To: <20241205140352.16822-2-dominik.karol.piatkowski@intel.com> References: <20241205140352.16822-1-dominik.karol.piatkowski@intel.com> <20241205140352.16822-2-dominik.karol.piatkowski@intel.com> Date: Thu, 12 Dec 2024 19:04:36 +0200 Message-ID: <87wmg4bzob.fsf@mkuoppal-desk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" Dominik Karol Pi=C4=85tkowski writes: > - Remove repeated calls to caching_get_instruction_count > - Limit surface checking to each breakpoint that is after write > instruction > - Fix the issue with sync between workload lifetime vs resume > > Signed-off-by: Dominik Karol Pi=C4=85tkowski > --- > tests/intel/xe_eudebug_online.c | 39 +++++++++++++++++++++++---------- > 1 file changed, 28 insertions(+), 11 deletions(-) > > diff --git a/tests/intel/xe_eudebug_online.c b/tests/intel/xe_eudebug_onl= ine.c > index 750350556..c02e2b1f4 100644 > --- a/tests/intel/xe_eudebug_online.c > +++ b/tests/intel/xe_eudebug_online.c > @@ -919,6 +919,10 @@ static void eu_attention_resume_caching_trigger(stru= ct xe_eudebug_debugger *d, > const uint32_t breakpoint_bit =3D 1 << 30; > struct gpgpu_shader *shader_preamble; > struct gpgpu_shader *shader_write_instr; > + const unsigned int instruction_count =3D > + caching_get_instruction_count(d->master_fd, s_dim.x, d->flags); > + uint64_t seqno =3D 0; > + int ret; >=20=20 > shader_preamble =3D gpgpu_shader_create(d->master_fd); > gpgpu_shader__write_dword(shader_preamble, SHADER_CANARY, 0); > @@ -935,7 +939,7 @@ static void eu_attention_resume_caching_trigger(struc= t xe_eudebug_debugger *d, > } >=20=20 > /* set breakpoint on next write instruction */ > - if (*counter < caching_get_instruction_count(d->master_fd, s_dim.x, d->= flags)) { > + if (*counter < instruction_count) { > igt_assert_eq(pread(data->vm_fd, &instr_usdw, sizeof(instr_usdw), > data->bb_offset + *kernel_offset + shader_preamble->size * 4 + > shader_write_instr->size * 4 * *counter), > @@ -949,7 +953,7 @@ static void eu_attention_resume_caching_trigger(struc= t xe_eudebug_debugger *d, > } >=20=20 > /* restore current instruction */ > - if (*counter && *counter <=3D caching_get_instruction_count(d->master_f= d, s_dim.x, d->flags)) > + if (*counter && *counter <=3D instruction_count) > overwrite_immediate_value_in_common_target_write(data->vm_fd, > data->bb_offset + *kernel_offset + > shader_preamble->size * 4 + > @@ -958,7 +962,7 @@ static void eu_attention_resume_caching_trigger(struc= t xe_eudebug_debugger *d, > CACHING_VALUE(*counter - 1)); >=20=20 > /* poison next instruction */ > - if (*counter < caching_get_instruction_count(d->master_fd, s_dim.x, d->= flags)) > + if (*counter < instruction_count) > overwrite_immediate_value_in_common_target_write(data->vm_fd, > data->bb_offset + *kernel_offset + > shader_preamble->size * 4 + > @@ -969,15 +973,28 @@ static void eu_attention_resume_caching_trigger(str= uct xe_eudebug_debugger *d, > gpgpu_shader_destroy(shader_write_instr); > gpgpu_shader_destroy(shader_preamble); >=20=20 > - for (int i =3D 0; i < data->target_size; i +=3D sizeof(uint32_t)) { > - igt_assert_eq(pread(data->vm_fd, &val, sizeof(val), data->target_offse= t + i), > - sizeof(val)); > - igt_assert_f(val !=3D CACHING_POISON_VALUE, "Poison value found at %04= d!\n", i); > - } > + /* check surface at each breakpoint that is after write instruction */ > + if (*counter > 1 && *counter <=3D instruction_count + 1) > + for (int i =3D 0; i < data->target_size; i +=3D sizeof(uint32_t)) { > + igt_assert_eq(pread(data->vm_fd, &val, sizeof(val), > + data->target_offset + i), sizeof(val)); > + igt_assert_f(val !=3D CACHING_POISON_VALUE, > + "Poison value found at %04d!\n", i); > + } >=20=20 > - eu_ctl_resume(d->master_fd, d->fd, att->client_handle, > - att->exec_queue_handle, att->lrc_handle, > - att->bitmask, att->bitmask_size); > + ret =3D __eu_ctl(d->fd, att->client_handle, att->exec_queue_handle, att= ->lrc_handle, > + att->bitmask, &att->bitmask_size, DRM_XE_EUDEBUG_EU_CONTROL_CMD= _RESUME, > + &seqno); > + > + /* > + * XXX: build a better sync between workload lifetime vs resume. > + * > + * Right now, it is possible to get attention after the workload has va= nished - in result, > + * eu_ctl above fails. Band-aid it by checking the eu_ctl return value = only n times it is > + * actually expected - that is, instruction_count of writes + 2 nops. > + */ The eu_ctl seqno versus the attention seqno can be used to untangle the async. But this should be band aid to remove timing component that causes some fails atleast on slow setups. Thanks for fixing this, Reviewed-by: Mika Kuoppala > + if (*counter < instruction_count + 2) > + igt_assert_eq(ret, 0); >=20=20 > (*counter)++; > } > --=20 > 2.34.1