From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Mon, 01 May 2023 13:01:45 -0700 Message-ID: <87wn1rkehi.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" In-Reply-To: <99a016bd-d3da-154c-4bca-46ff66bb1932@intel.com> References: <20230425201926.99086-1-John.C.Harrison@Intel.com> <20230425201926.99086-2-John.C.Harrison@Intel.com> <874jp29urv.wl-ashutosh.dixit@intel.com> <99a016bd-d3da-154c-4bca-46ff66bb1932@intel.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 1/2] lib/intel_decode: Decode Gen12 ring/batch instructions correctly List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" To: John Harrison Cc: IGT-Dev@Lists.FreeDesktop.Org, Intel-GFX@Lists.FreeDesktop.Org List-ID: On Mon, 01 May 2023 12:44:14 -0700, John Harrison wrote: > > On 4/26/2023 14:51, Dixit, Ashutosh wrote: > > On Tue, 25 Apr 2023 13:19:25 -0700, John.C.Harrison@Intel.com wrote: > >> @@ -3623,7 +3624,17 @@ decode_3d_965(struct intel_decode *ctx) > >> return len; > >> > >> case 0x7a00: > >> - if (IS_GEN6(devid) || IS_GEN7(devid)) { > >> + if (IS_GEN12(devid)) { > >> + if (len != 6) > >> + fprintf(out, "Bad count in PIPE_CONTROL\n"); > >> + instr_out(ctx, 0, "PIPE_CONTROL\n"); > >> + instr_out(ctx, 1, "flags\n"); > >> + instr_out(ctx, 2, "write address low\n"); > >> + instr_out(ctx, 3, "write address high\n"); > >> + instr_out(ctx, 4, "write data low\n"); > >> + instr_out(ctx, 5, "write data high\n"); > >> + return len; > > Is there a reference for this? I can review but have no idea what's going > > on here. The rest of the patch looks good. Thanks. > Just the bspec definition of PIPE_CONTROL. On later gens it has more data - > 64bit rather than 32bit addressing I think. Reviewed-by: Ashutosh Dixit