From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 82AF98982A for ; Fri, 22 Oct 2021 00:32:33 +0000 (UTC) Date: Thu, 21 Oct 2021 17:29:50 -0700 Message-ID: <87wnm59a0x.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" In-Reply-To: <87y26l9atx.wl-ashutosh.dixit@intel.com> References: <20211021043508.1158148-1-priyanka.dandamudi@intel.com> <20211021043508.1158148-4-priyanka.dandamudi@intel.com> <20211021073321.GC3640@zkempczy-mobl2> <87y26l9atx.wl-ashutosh.dixit@intel.com> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: quoted-printable Subject: Re: [igt-dev] [PATCH i-g-t 3/4] lib/igt_gt: Add compute engine List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" To: Zbigniew =?ISO-8859-2?Q?Kempczy=F1ski?= Cc: priyanka.dandamudi@intel.com, igt-dev@lists.freedesktop.org, arjun.melkaveri@intel.com, John Harrison , Tvrtko Ursulin List-ID: On Thu, 21 Oct 2021 17:12:26 -0700, Dixit, Ashutosh wrote: > > On Thu, 21 Oct 2021 00:33:21 -0700, Zbigniew Kempczy=F1ski wrote: > > > > On Thu, Oct 21, 2021 at 10:05:07AM +0530, priyanka.dandamudi@intel.com = wrote: > > > From: Vinay Belgaumkar > > > > > > Add compute (CCS) engine. Add this to the IGT > > > structure to allow gem tests to execute. > > > > > > Signed-off-by: Stuart Summers > > > Signed-off-by: Vinay Belgaumkar > > > Signed-off-by: Priyanka Dandamudi > > > Cc: Ashutosh Dixit > > > Cc: Arjun Melkaveri > > > --- > > > lib/igt_gt.c | 4 ++++ > > > 1 file changed, 4 insertions(+) > > > > > > diff --git a/lib/igt_gt.c b/lib/igt_gt.c > > > index a0ba04cc..80fb65ca 100644 > > > --- a/lib/igt_gt.c > > > +++ b/lib/igt_gt.c > > > @@ -604,6 +604,10 @@ const struct intel_execution_engine2 intel_execu= tion_engines2[] =3D { > > > { "vcs1", I915_ENGINE_CLASS_VIDEO, 1, I915_EXEC_BSD | I915_EXEC_BSD_R= ING2 }, > > > { "vcs2", I915_ENGINE_CLASS_VIDEO, 2, -1 }, > > > { "vecs0", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, I915_EXEC_VEBOX }, > > > + { "ccs0", I915_ENGINE_CLASS_COMPUTE, 0 , -1}, > > > + { "ccs1", I915_ENGINE_CLASS_COMPUTE, 1 , -1}, > > > + { "ccs2", I915_ENGINE_CLASS_COMPUTE, 2 , -1}, > > > + { "ccs3", I915_ENGINE_CLASS_COMPUTE, 3 , -1}, > > Is this correct? Isn't intel_execution_engines2 a list of just the legacy > engines? I don't think compute engines (which may vary in number) can be > added to the list of legacy engines. Isn't it true that compute engines c= an > only be accessed by querying the present engines dynamically (using > something like intel_ctx_create_all_physical())? I've copied Tvrtko (the boss :), but I am pretty sure what I said is correct. Legacy engines are what context 0 is created with (without adding any more engines onto context 0). So unless we can confirm that these engines are present for context 0 in the kernel we can't add them in IGT.