Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET

From: Antonio Argenziano <antonio.argenziano@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t] i915/gem_ctx_isolation: Ignore the low bits of BB_OFFSET
Date: Thu, 10 Jan 2019 13:24:56 -0800	[thread overview]
Message-ID: <965ee694-dab4-c5b4-76a5-5fea23634292@intel.com> (raw)
In-Reply-To: <20190107124140.20183-1-chris@chris-wilson.co.uk>

On 07/01/19 04:41, Chris Wilson wrote:
> On Skylake, BB_OFFSET seems to be unstable. Since this is an
> offset into the batch at the time of CS execution, it should be actively
> written to as we read from the register so allow it a qword of
> discrepancy (since the CS should be reading in qwords). This still
> allows us to detect dirt across the rest of the register field, should
> that be required.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   tests/i915/gem_ctx_isolation.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
> index 058cf3ec1..78a244382 100644
> --- a/tests/i915/gem_ctx_isolation.c
> +++ b/tests/i915/gem_ctx_isolation.c
> @@ -96,7 +96,7 @@ static const struct named_register {
>   	{ "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
>   	{ "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
>   	{ "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
> -	{ "BB_OFFSET", GEN8, RCS0, 0x2158 },
> +	{ "BB_OFFSET", GEN8, RCS0, 0x2158, .ignore_bits = 0x7 },

The batch offset starts at bit 2. Do we observe changes in bit 0-1 as well?

Antonio

>   	{ "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
>   	{ "CS_GPR", GEN8, RCS0, 0x2600, 32 },
>   	{ "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
> 
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