From: "Sharma, Nishit" <nishit.sharma@intel.com>
To: Xin Wang <x.wang@intel.com>, <igt-dev@lists.freedesktop.org>
Cc: Matt Roper <matthew.d.roper@intel.com>
Subject: Re: [PATCH] tests/intel/xe_multigpu_svm: fix 32-bit build error
Date: Tue, 6 Jan 2026 11:02:58 +0530 [thread overview]
Message-ID: <99913471-1032-469d-80c9-cc65964c83ea@intel.com> (raw)
In-Reply-To: <20260105234615.284403-1-x.wang@intel.com>
On 1/6/2026 5:16 AM, Xin Wang wrote:
> The test was treating several ioctl-style __u64 user pointer
> fields as native pointers and doing pointer arithmetic /
> dereferences / munmap() directly on the integer values. On 32-bit
> this triggers -Werror=int-to-pointer-cast and can also truncate
> addresses. In addition, splitting 64-bit addresses with 1UL << 32
> is not safe on 32-bit.
>
> Fixes: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/pipelines/1577551
>
> Cc: Nishit Sharma <nishit.sharma@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> ---
> tests/intel/xe_multigpu_svm.c | 69 ++++++++++++++++++-----------------
> 1 file changed, 35 insertions(+), 34 deletions(-)
>
> diff --git a/tests/intel/xe_multigpu_svm.c b/tests/intel/xe_multigpu_svm.c
> index fee738035..5583d781a 100644
> --- a/tests/intel/xe_multigpu_svm.c
> +++ b/tests/intel/xe_multigpu_svm.c
> @@ -3,6 +3,7 @@
> * Copyright © 2025 Intel Corporation
> */
>
> +#include <inttypes.h>
> #include <unistd.h>
>
> #include "drmtest.h"
> @@ -407,10 +408,10 @@ static void batch_init(int fd, uint32_t vm, uint64_t src_addr,
> cmd[i++] = height - 1;
> cmd[i++] = width - 1;
> cmd[i++] = width - 1;
> - cmd[i++] = src_addr & ((1UL << 32) - 1);
> - cmd[i++] = src_addr >> 32;
> - cmd[i++] = dst_addr & ((1UL << 32) - 1);
> - cmd[i++] = dst_addr >> 32;
> + cmd[i++] = lower_32_bits(src_addr);
> + cmd[i++] = upper_32_bits(src_addr);
> + cmd[i++] = lower_32_bits(dst_addr);
> + cmd[i++] = upper_32_bits(dst_addr);
> if (intel_graphics_ver(dev_id) >= IP_VER(20, 0)) {
> cmd[i++] = mocs_index << XE2_MEM_COPY_SRC_MOCS_SHIFT | mocs_index;
> } else {
> @@ -542,7 +543,7 @@ gpu_madvise_exec_sync(struct xe_svm_gpu_info *gpu, struct xe_svm_gpu_info *xgpu,
> sync_addr, exec_queue, flags);
> free(sync_addr);
>
> - sync_addr = (void *)((char *)*batch_addr + SZ_4K);
> + sync_addr = (uint64_t *)((char *)from_user_pointer(*batch_addr) + SZ_4K);
> sync.addr = to_user_pointer((uint64_t *)sync_addr);
> sync.timeline_value = EXEC_SYNC_VAL;
> WRITE_ONCE(*sync_addr, 0);
> @@ -630,7 +631,7 @@ copy_src_dst(struct xe_svm_gpu_info *gpu1,
> sync_addr, exec_queue[0], flags);
> free(sync_addr);
>
> - sync_addr = (void *)((char *)batch_addr + SZ_4K);
> + sync_addr = (uint64_t *)((char *)from_user_pointer(batch_addr) + SZ_4K);
> sync.addr = to_user_pointer((uint64_t *)sync_addr);
> sync.timeline_value = EXEC_SYNC_VAL;
> WRITE_ONCE(*sync_addr, 0);
> @@ -645,7 +646,7 @@ copy_src_dst(struct xe_svm_gpu_info *gpu1,
>
> free(copy_dst);
> free(copy_src);
> - munmap((void *)batch_addr, BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch_addr), BATCH_SIZE(gpu1->fd));
> batch_fini(gpu1->fd, vm[0], batch_bo, batch_addr);
> cleanup_vm_and_queue(gpu1, vm[0], exec_queue[0]);
> }
> @@ -680,7 +681,7 @@ atomic_inc_op(struct xe_svm_gpu_info *gpu1,
> copy_dst = aligned_alloc(SZ_2M, SZ_4K);
> igt_assert(copy_dst);
>
> - WRITE_ONCE(*(uint64_t *)addr, ATOMIC_OP_VAL - 1);
> + WRITE_ONCE(*(uint64_t *)from_user_pointer(addr), ATOMIC_OP_VAL - 1);
>
> /* GPU1: Atomic Batch create */
> gpu_batch_create(gpu1, vm[0], exec_queue[0], addr, 0,
> @@ -715,12 +716,12 @@ atomic_inc_op(struct xe_svm_gpu_info *gpu1,
> gpu_madvise_exec_sync(gpu1, gpu2, vm[0], exec_queue[0], addr,
> &batch_addr[0], flags, NULL);
>
> - final_value = *(uint32_t *)addr;
> + final_value = *(uint32_t *)from_user_pointer(addr);
> /* NOW CPU can read copy_dst (GPU1 ATOMIC op) */
> igt_assert_eq(final_value, ATOMIC_OP_VAL + 1);
>
> - munmap((void *)batch_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch_addr[1]), BATCH_SIZE(gpu2->fd));
> batch_fini(gpu1->fd, vm[0], batch_bo[0], batch_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch_bo[1], batch_addr[1]);
> free(data);
> @@ -787,7 +788,7 @@ coherency_test_multigpu(struct xe_svm_gpu_info *gpu1,
>
> igt_info("verifying concurrent write race\n");
>
> - WRITE_ONCE(*(uint64_t *)addr, 0);
> + WRITE_ONCE(*(uint64_t *)from_user_pointer(addr), 0);
>
> store_dword_batch_init(gpu1->fd, vm[0], addr, &batch1_bo[0],
> &batch1_addr[0], BATCH_VALUE + 10);
> @@ -795,7 +796,7 @@ coherency_test_multigpu(struct xe_svm_gpu_info *gpu1,
> &batch1_addr[1], BATCH_VALUE + 20);
>
> /* Setup sync for GPU1 */
> - sync_addr0 = (void *)((char *)batch1_addr[0] + SZ_4K);
> + sync_addr0 = (uint64_t *)((char *)from_user_pointer(batch1_addr[0]) + SZ_4K);
> sync0.flags = DRM_XE_SYNC_FLAG_SIGNAL;
> sync0.type = DRM_XE_SYNC_TYPE_USER_FENCE;
> sync0.addr = to_user_pointer((uint64_t *)sync_addr0);
> @@ -803,7 +804,7 @@ coherency_test_multigpu(struct xe_svm_gpu_info *gpu1,
> WRITE_ONCE(*sync_addr0, 0);
>
> /* Setup sync for GPU2 */
> - sync_addr1 = (void *)((char *)batch1_addr[1] + SZ_4K);
> + sync_addr1 = (uint64_t *)((char *)from_user_pointer(batch1_addr[1]) + SZ_4K);
> sync1.flags = DRM_XE_SYNC_FLAG_SIGNAL;
> sync1.type = DRM_XE_SYNC_TYPE_USER_FENCE;
> sync1.addr = to_user_pointer((uint64_t *)sync_addr1);
> @@ -845,19 +846,19 @@ coherency_test_multigpu(struct xe_svm_gpu_info *gpu1,
> else if (coh_result == 0)
> igt_warn("Both writes failed - coherency issue\n");
> else
> - igt_warn("Unexpected value 0x%lx - possible coherency corruption\n",
> + igt_warn("Unexpected value 0x%" PRIx64 " - possible coherency corruption\n",
> coh_result);
>
> - munmap((void *)batch1_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch1_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch1_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch1_addr[1]), BATCH_SIZE(gpu2->fd));
>
> batch_fini(gpu1->fd, vm[0], batch1_bo[0], batch1_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch1_bo[1], batch1_addr[1]);
> free(result);
> }
>
> - munmap((void *)batch_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch_addr[1]), BATCH_SIZE(gpu2->fd));
> batch_fini(gpu1->fd, vm[0], batch_bo[0], batch_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch_bo[1], batch_addr[1]);
> free(data1);
> @@ -995,8 +996,8 @@ latency_test_multigpu(struct xe_svm_gpu_info *gpu1,
> igt_warn("Prefetch not providing expected performance benefit\n");
> }
>
> - munmap((void *)batch_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch_addr[1]), BATCH_SIZE(gpu2->fd));
>
> batch_fini(gpu1->fd, vm[0], batch_bo[0], batch_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch_bo[1], batch_addr[1]);
> @@ -1109,8 +1110,8 @@ pagefault_test_multigpu(struct xe_svm_gpu_info *gpu1,
> pf_count_gpu2_after - pf_count_gpu2_before);
> }
>
> - munmap((void *)batch_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch_addr[1]), BATCH_SIZE(gpu2->fd));
> batch_fini(gpu1->fd, vm[0], batch_bo[0], batch_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch_bo[1], batch_addr[0]);
> free(data);
> @@ -1152,7 +1153,7 @@ multigpu_access_test(struct xe_svm_gpu_info *gpu1,
> data[0].vm_sync = 0;
> addr = to_user_pointer(data);
>
> - WRITE_ONCE(*(uint64_t *)addr, 0);
> + WRITE_ONCE(*(uint64_t *)from_user_pointer(addr), 0);
>
> /* GPU1: Atomic Batch create */
> gpu_batch_create(gpu1, vm[0], exec_queue[0], addr, 0,
> @@ -1195,14 +1196,14 @@ multigpu_access_test(struct xe_svm_gpu_info *gpu1,
> bool last = (i == NUM_ITER - 1);
>
> if (last) {
> - sync_addr[0] = (void *)((char *)batch_addr[0] + SZ_4K);
> + sync_addr[0] = (uint64_t *)((char *)from_user_pointer(batch_addr[0]) + SZ_4K);
> sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> sync[0].type = DRM_XE_SYNC_TYPE_USER_FENCE;
> sync[0].addr = to_user_pointer((uint64_t *)sync_addr[0]);
> sync[0].timeline_value = EXEC_SYNC_VAL + i;
> WRITE_ONCE(*sync_addr[0], 0);
>
> - sync_addr[1] = (void *)((char *)batch_addr[1] + SZ_4K);
> + sync_addr[1] = (uint64_t *)((char *)from_user_pointer(batch_addr[1]) + SZ_4K);
> sync[1].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> sync[1].type = DRM_XE_SYNC_TYPE_USER_FENCE;
> sync[1].addr = to_user_pointer((uint64_t *)sync_addr[1]);
> @@ -1230,7 +1231,7 @@ multigpu_access_test(struct xe_svm_gpu_info *gpu1,
> exec_queue[1], NSEC_PER_SEC * 30);
> }
>
> - igt_info("Both GPUs completed execution %u\n", READ_ONCE(*(uint32_t *)addr));
> + igt_info("Both GPUs completed execution %u\n", READ_ONCE(*(uint32_t *)from_user_pointer(addr)));
>
> /* === Verification using GPU read (not CPU) === */
> verify_result = aligned_alloc(SZ_2M, SZ_4K);
> @@ -1241,7 +1242,7 @@ multigpu_access_test(struct xe_svm_gpu_info *gpu1,
> gpu_batch_create(gpu1, vm[0], exec_queue[0], addr, to_user_pointer(verify_result),
> &verify_batch_bo, &verify_batch_addr, flags, INIT);
>
> - sync_addr[0] = (void *)((char *)verify_batch_addr + SZ_4K);
> + sync_addr[0] = (uint64_t *)((char *)from_user_pointer(verify_batch_addr) + SZ_4K);
> sync[0].addr = to_user_pointer((uint64_t *)sync_addr[0]);
> sync[0].timeline_value = EXEC_SYNC_VAL;
> sync[0].flags = DRM_XE_SYNC_FLAG_SIGNAL;
> @@ -1257,19 +1258,19 @@ multigpu_access_test(struct xe_svm_gpu_info *gpu1,
> final_value = READ_ONCE(*(uint32_t *)verify_result);
>
> igt_info("GPU verification batch copied value: %u\n", final_value);
> - igt_info("CPU direct read shows: %u\n", (unsigned int)*(uint64_t *)addr);
> + igt_info("CPU direct read shows: %u\n", (unsigned int)*(uint64_t *)from_user_pointer(addr));
>
> /* Expected: 0 + (NUM_ITER * 2 GPUs) = 400 */
> igt_assert_f((final_value == 2 * NUM_ITER),
> "Expected %u value, got %u\n",
> 2 * NUM_ITER, final_value);
>
> - munmap((void *)verify_batch_addr, BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(verify_batch_addr), BATCH_SIZE(gpu1->fd));
> batch_fini(gpu1->fd, vm[0], verify_batch_bo, verify_batch_addr);
> free(verify_result);
>
> - munmap((void *)batch_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch_addr[1]), BATCH_SIZE(gpu2->fd));
> batch_fini(gpu1->fd, vm[0], batch_bo[0], batch_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch_bo[1], batch_addr[1]);
> free(data);
> @@ -1356,8 +1357,8 @@ multigpu_migrate_test(struct xe_svm_gpu_info *gpu1,
>
> igt_info("Migration test completed successfully\n");
>
> - munmap((void *)batch1_addr[0], BATCH_SIZE(gpu1->fd));
> - munmap((void *)batch1_addr[1], BATCH_SIZE(gpu2->fd));
> + munmap(from_user_pointer(batch1_addr[0]), BATCH_SIZE(gpu1->fd));
> + munmap(from_user_pointer(batch1_addr[1]), BATCH_SIZE(gpu2->fd));
> batch_fini(gpu1->fd, vm[0], batch1_bo[0], batch1_addr[0]);
> batch_fini(gpu2->fd, vm[1], batch1_bo[1], batch1_addr[1]);
> free(data);
Please execute checkpatch before merge. Got three warnings
tests-intel-xe_multigpu_svm-fix-32-bit-build-error.patch:168:
WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#168: FILE: tests/intel/xe_multigpu_svm.c:1199:
+ sync_addr[0] = (uint64_t *)((char
*)from_user_pointer(batch_addr[0]) + SZ_4K);
tests-intel-xe_multigpu_svm-fix-32-bit-build-error.patch:176:
WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#176: FILE: tests/intel/xe_multigpu_svm.c:1206:
+ sync_addr[1] = (uint64_t *)((char
*)from_user_pointer(batch_addr[1]) + SZ_4K);
tests-intel-xe_multigpu_svm-fix-32-bit-build-error.patch:185:
WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#185: FILE: tests/intel/xe_multigpu_svm.c:1234:
+ igt_info("Both GPUs completed execution %u\n",
READ_ONCE(*(uint32_t *)from_user_pointer(addr)));
Please take care these before final merge. Otherwise LGTM
Reviewed-by: Nishit Sharma <nishit.sharma@intel.com>
next prev parent reply other threads:[~2026-01-06 5:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-05 23:46 [PATCH] tests/intel/xe_multigpu_svm: fix 32-bit build error Xin Wang
2026-01-06 1:23 ` ✓ Xe.CI.BAT: success for " Patchwork
2026-01-06 1:32 ` ✓ i915.CI.BAT: " Patchwork
2026-01-06 2:14 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-06 5:19 ` ✓ i915.CI.Full: success " Patchwork
2026-01-06 5:32 ` Sharma, Nishit [this message]
2026-01-06 6:02 ` [PATCH v2] " Xin Wang
2026-01-06 8:21 ` Karthik B S
2026-01-06 6:42 ` ✓ Xe.CI.BAT: success for tests/intel/xe_multigpu_svm: fix 32-bit build error (rev2) Patchwork
2026-01-06 6:56 ` ✓ i915.CI.BAT: " Patchwork
2026-01-06 9:15 ` ✓ Xe.CI.Full: " Patchwork
2026-01-06 10:19 ` ✓ i915.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=99913471-1032-469d-80c9-cc65964c83ea@intel.com \
--to=nishit.sharma@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=matthew.d.roper@intel.com \
--cc=x.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox