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IGT updates to this file generally > > > > specify which actual kernel commit you're synchronizing against; none of > > > > the four listed above match the content you've copied here because there > > > > are additional changes not present in those. > > > Because there are now several out of sync next branches, saying as > > > of this commit idea was not working. Hence this approach. > > > > You should generally be syncing with drm-next after things land there. > > So which drm-next commit are you syncing with for this commit? > They hadnt been in a drm-next commit yet. At the time it was just after > a next cut, at this point we can probably just wait for them to land. I agree with Atwood here. We had changes coming from drm-intel-next and changes coming to drm-xe-next. In the kernel history the changes coming from drm-xe-next are on top of the drm-intel-next ones. But they landed first here in the IGT. Now it is in a situation that individual patches from drm-intel-next would conflict here badly. The safest thing is to keep it simple and use a single patch like this. This is the final copy of the file directly with the proper mention to the commit ids. I really believe we should just go ahead and push this to finalize the alignment before something else gets in the way. > > MattA > > > > > > Matt > > > > > > > > MattA > > > > > > > > > > > > Matt > > > > > > > > > > > > > > Signed-off-by: Matt Atwood > > > > > --- > > > > > lib/pciids.h | 62 +++++++++++++++++++++++++++++++++++++++------------- > > > > > 1 file changed, 47 insertions(+), 15 deletions(-) > > > > > > > > > > diff --git a/lib/pciids.h b/lib/pciids.h > > > > > index 23f349f65..4736ea525 100644 > > > > > --- a/lib/pciids.h > > > > > +++ b/lib/pciids.h > > > > > @@ -717,37 +717,66 @@ > > > > > MACRO__(0xA7AB, ## __VA_ARGS__) > > > > > > > > > > /* DG2 */ > > > > > -#define INTEL_DG2_G10_IDS(MACRO__, ...) \ > > > > > - MACRO__(0x5690, ## __VA_ARGS__), \ > > > > > - MACRO__(0x5691, ## __VA_ARGS__), \ > > > > > - MACRO__(0x5692, ## __VA_ARGS__), \ > > > > > +#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \ > > > > > MACRO__(0x56A0, ## __VA_ARGS__), \ > > > > > MACRO__(0x56A1, ## __VA_ARGS__), \ > > > > > - MACRO__(0x56A2, ## __VA_ARGS__), \ > > > > > + MACRO__(0x56A2, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \ > > > > > MACRO__(0x56BE, ## __VA_ARGS__), \ > > > > > MACRO__(0x56BF, ## __VA_ARGS__) > > > > > > > > > > -#define INTEL_DG2_G11_IDS(MACRO__, ...) \ > > > > > - MACRO__(0x5693, ## __VA_ARGS__), \ > > > > > - MACRO__(0x5694, ## __VA_ARGS__), \ > > > > > - MACRO__(0x5695, ## __VA_ARGS__), \ > > > > > +#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \ > > > > > + MACRO__(0x5690, ## __VA_ARGS__), \ > > > > > + MACRO__(0x5691, ## __VA_ARGS__), \ > > > > > + MACRO__(0x5692, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G10_IDS(MACRO__, ...) \ > > > > > + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \ > > > > > MACRO__(0x56A5, ## __VA_ARGS__), \ > > > > > MACRO__(0x56A6, ## __VA_ARGS__), \ > > > > > MACRO__(0x56B0, ## __VA_ARGS__), \ > > > > > - MACRO__(0x56B1, ## __VA_ARGS__), \ > > > > > + MACRO__(0x56B1, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \ > > > > > MACRO__(0x56BA, ## __VA_ARGS__), \ > > > > > MACRO__(0x56BB, ## __VA_ARGS__), \ > > > > > MACRO__(0x56BC, ## __VA_ARGS__), \ > > > > > MACRO__(0x56BD, ## __VA_ARGS__) > > > > > > > > > > -#define INTEL_DG2_G12_IDS(MACRO__, ...) \ > > > > > - MACRO__(0x5696, ## __VA_ARGS__), \ > > > > > - MACRO__(0x5697, ## __VA_ARGS__), \ > > > > > +#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \ > > > > > + MACRO__(0x5693, ## __VA_ARGS__), \ > > > > > + MACRO__(0x5694, ## __VA_ARGS__), \ > > > > > + MACRO__(0x5695, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G11_IDS(MACRO__, ...) \ > > > > > + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \ > > > > > MACRO__(0x56A3, ## __VA_ARGS__), \ > > > > > MACRO__(0x56A4, ## __VA_ARGS__), \ > > > > > MACRO__(0x56B2, ## __VA_ARGS__), \ > > > > > MACRO__(0x56B3, ## __VA_ARGS__) > > > > > > > > > > +#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \ > > > > > + MACRO__(0x5696, ## __VA_ARGS__), \ > > > > > + MACRO__(0x5697, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_G12_IDS(MACRO__, ...) \ > > > > > + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_DG2_D_IDS(MACRO__, ...) \ > > > > > + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__) > > > > > + > > > > > #define INTEL_DG2_IDS(MACRO__, ...) \ > > > > > INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > @@ -782,9 +811,12 @@ > > > > > INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__) > > > > > > > > > > /* MTL */ > > > > > -#define INTEL_MTL_IDS(MACRO__, ...) \ > > > > > +#define INTEL_MTL_U_IDS(MACRO__, ...) \ > > > > > MACRO__(0x7D40, ## __VA_ARGS__), \ > > > > > - MACRO__(0x7D45, ## __VA_ARGS__), \ > > > > > + MACRO__(0x7D45, ## __VA_ARGS__) > > > > > + > > > > > +#define INTEL_MTL_IDS(MACRO__, ...) \ > > > > > + INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \ > > > > > MACRO__(0x7D55, ## __VA_ARGS__), \ > > > > > MACRO__(0x7D60, ## __VA_ARGS__), \ > > > > > MACRO__(0x7DD5, ## __VA_ARGS__) > > > > > -- > > > > > 2.45.0 > > > > > > > > > > > > > -- > > > > Matt Roper > > > > Graphics Software Engineer > > > > Linux GPU Platform Enablement > > > > Intel Corporation > > > > -- > > Matt Roper > > Graphics Software Engineer > > Linux GPU Platform Enablement > > Intel Corporation