From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Matt Atwood <matthew.s.atwood@intel.com>,
Petri Latvala <adrinael@adrinael.net>,
Arkadiusz Hiler <arek@hiler.eu>,
Kamil Konieczny <kamil.konieczny@linux.intel.com>,
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>,
Bhanuprakash Modem <bhanuprakash.modem@gmail.com>,
Ashutosh Dixit <ashutosh.dixit@intel.com>,
Karthik B S <karthik.b.s@intel.com>
Cc: <igt-dev@lists.freedesktop.org>, <matthew.d.roper@intel.com>
Subject: Re: [PATCH v2] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL
Date: Mon, 10 Feb 2025 11:47:30 -0500 [thread overview]
Message-ID: <Z6otorjM88ECUD-2@intel.com> (raw)
In-Reply-To: <20250207001432.48524-1-matthew.s.atwood@intel.com>
On Thu, Feb 06, 2025 at 04:14:32PM -0800, Matt Atwood wrote:
> There have been several changes to pciids upstream that need to be
> sync'd into igt. This synchronization is different from the normal
> process because kernel history differences in drm-xe-next, and
> drm-i915-next cause conflicts that create conflicts.
I did a s/drm-i915-next/drm-intel-next (i915)/ while applying the patch
But I forgot the -s on both b4 shazam and on git amend,
so the patch is without my signed off by...
Cc IGT maintainers here to see if there's some correction needed.
I'm sorry for the mistake,
Rodrigo.
>
> Sync with the following kernel commits:
> f9a15b968dce ("drm/intel/pciids: Refactor DG2 PCI IDs into segment
> ranges")
> e35ecd95ecf2 ("drm/i915/display: Add MTL subplatforms definition")
> fa8ffaae1b15 ("drm/xe/bmg: Add new PCI IDs")
> 16016ade13f6 ("drm/xe/ptl: Update the PTL pci id table")
>
> v2: More verbose commit message
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> lib/pciids.h | 62 +++++++++++++++++++++++++++++++++++++++-------------
> 1 file changed, 47 insertions(+), 15 deletions(-)
>
> diff --git a/lib/pciids.h b/lib/pciids.h
> index 23f349f65..4736ea525 100644
> --- a/lib/pciids.h
> +++ b/lib/pciids.h
> @@ -717,37 +717,66 @@
> MACRO__(0xA7AB, ## __VA_ARGS__)
>
> /* DG2 */
> -#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> - MACRO__(0x5690, ## __VA_ARGS__), \
> - MACRO__(0x5691, ## __VA_ARGS__), \
> - MACRO__(0x5692, ## __VA_ARGS__), \
> +#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
> MACRO__(0x56A0, ## __VA_ARGS__), \
> MACRO__(0x56A1, ## __VA_ARGS__), \
> - MACRO__(0x56A2, ## __VA_ARGS__), \
> + MACRO__(0x56A2, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
> MACRO__(0x56BE, ## __VA_ARGS__), \
> MACRO__(0x56BF, ## __VA_ARGS__)
>
> -#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> - MACRO__(0x5693, ## __VA_ARGS__), \
> - MACRO__(0x5694, ## __VA_ARGS__), \
> - MACRO__(0x5695, ## __VA_ARGS__), \
> +#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
> + MACRO__(0x5690, ## __VA_ARGS__), \
> + MACRO__(0x5691, ## __VA_ARGS__), \
> + MACRO__(0x5692, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G10_IDS(MACRO__, ...) \
> + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
> MACRO__(0x56A5, ## __VA_ARGS__), \
> MACRO__(0x56A6, ## __VA_ARGS__), \
> MACRO__(0x56B0, ## __VA_ARGS__), \
> - MACRO__(0x56B1, ## __VA_ARGS__), \
> + MACRO__(0x56B1, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
> MACRO__(0x56BA, ## __VA_ARGS__), \
> MACRO__(0x56BB, ## __VA_ARGS__), \
> MACRO__(0x56BC, ## __VA_ARGS__), \
> MACRO__(0x56BD, ## __VA_ARGS__)
>
> -#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> - MACRO__(0x5696, ## __VA_ARGS__), \
> - MACRO__(0x5697, ## __VA_ARGS__), \
> +#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
> + MACRO__(0x5693, ## __VA_ARGS__), \
> + MACRO__(0x5694, ## __VA_ARGS__), \
> + MACRO__(0x5695, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G11_IDS(MACRO__, ...) \
> + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
> MACRO__(0x56A3, ## __VA_ARGS__), \
> MACRO__(0x56A4, ## __VA_ARGS__), \
> MACRO__(0x56B2, ## __VA_ARGS__), \
> MACRO__(0x56B3, ## __VA_ARGS__)
>
> +#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
> + MACRO__(0x5696, ## __VA_ARGS__), \
> + MACRO__(0x5697, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_G12_IDS(MACRO__, ...) \
> + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define INTEL_DG2_D_IDS(MACRO__, ...) \
> + INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
> + INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
> +
> #define INTEL_DG2_IDS(MACRO__, ...) \
> INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
> INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
> @@ -782,9 +811,12 @@
> INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
>
> /* MTL */
> -#define INTEL_MTL_IDS(MACRO__, ...) \
> +#define INTEL_MTL_U_IDS(MACRO__, ...) \
> MACRO__(0x7D40, ## __VA_ARGS__), \
> - MACRO__(0x7D45, ## __VA_ARGS__), \
> + MACRO__(0x7D45, ## __VA_ARGS__)
> +
> +#define INTEL_MTL_IDS(MACRO__, ...) \
> + INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \
> MACRO__(0x7D55, ## __VA_ARGS__), \
> MACRO__(0x7D60, ## __VA_ARGS__), \
> MACRO__(0x7DD5, ## __VA_ARGS__)
> --
> 2.45.0
>
next prev parent reply other threads:[~2025-02-10 16:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-07 0:14 [PATCH v2] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL Matt Atwood
2025-02-07 2:55 ` ✓ Xe.CI.BAT: success for lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL (rev2) Patchwork
2025-02-07 8:16 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-07 16:25 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-07 16:38 ` ✓ Xe.CI.BAT: " Patchwork
2025-02-08 1:04 ` ✗ i915.CI.Full: failure " Patchwork
2025-02-08 2:00 ` ✗ Xe.CI.Full: " Patchwork
2025-02-10 16:47 ` Rodrigo Vivi [this message]
2025-02-10 18:21 ` [PATCH v2] lib/pciids: Sync pci id changes for DG2/MTL/BMG/PTL Juha-Pekka Heikkilä
2025-02-10 18:34 ` Rodrigo Vivi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z6otorjM88ECUD-2@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=adrinael@adrinael.net \
--cc=arek@hiler.eu \
--cc=ashutosh.dixit@intel.com \
--cc=bhanuprakash.modem@gmail.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=juhapekka.heikkila@gmail.com \
--cc=kamil.konieczny@linux.intel.com \
--cc=karthik.b.s@intel.com \
--cc=matthew.d.roper@intel.com \
--cc=matthew.s.atwood@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox