From: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t v4 13/15] lib/intel_batchbuffer: extend to include optional alignment
Date: Thu, 19 Oct 2023 13:36:58 -0700 [thread overview]
Message-ID: <ZTGTaume7TusjmZy@nvishwa1-DESK> (raw)
In-Reply-To: <20231019144106.560624-14-matthew.auld@intel.com>
On Thu, Oct 19, 2023 at 03:41:04PM +0100, Matthew Auld wrote:
>Extend intel_bb_create_full() to support specifying the alignment for
>the allocator. This will be useful in some upcoming test.
>
>Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>Cc: José Roberto de Souza <jose.souza@intel.com>
>Cc: Pallavi Mishra <pallavi.mishra@intel.com>
LGTM.
Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>---
> lib/intel_batchbuffer.c | 30 +++++++++++++++++++-----------
> lib/intel_batchbuffer.h | 2 +-
> 2 files changed, 20 insertions(+), 12 deletions(-)
>
>diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>index ef3e3154a..0fcf62452 100644
>--- a/lib/intel_batchbuffer.c
>+++ b/lib/intel_batchbuffer.c
>@@ -894,7 +894,7 @@ static inline uint64_t __intel_bb_get_offset(struct intel_bb *ibb,
> static struct intel_bb *
> __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
> uint32_t size, bool do_relocs,
>- uint64_t start, uint64_t end,
>+ uint64_t start, uint64_t end, uint64_t alignment,
> uint8_t allocator_type, enum allocator_strategy strategy)
> {
> struct drm_i915_gem_exec_object2 *object;
>@@ -918,7 +918,11 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
> */
> if (ibb->driver == INTEL_DRIVER_I915) {
> ibb->uses_full_ppgtt = gem_uses_full_ppgtt(fd);
>- ibb->alignment = gem_detect_safe_alignment(fd);
>+
>+ if (!alignment)
>+ alignment = gem_detect_safe_alignment(fd);
>+
>+ ibb->alignment = alignment;
> ibb->gtt_size = gem_aperture_size(fd);
> ibb->handle = gem_create(fd, size);
>
>@@ -947,7 +951,10 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
> } else {
> igt_assert(!do_relocs);
>
>- ibb->alignment = xe_get_default_alignment(fd);
>+ if (!alignment)
>+ alignment = xe_get_default_alignment(fd);
>+
>+ ibb->alignment = alignment;
> size = ALIGN(size, ibb->alignment);
> ibb->handle = xe_bo_create_flags(fd, 0, size, visible_vram_if_possible(fd, 0));
>
>@@ -1018,6 +1025,7 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
> * @size: size of the batchbuffer
> * @start: allocator vm start address
> * @end: allocator vm start address
>+ * @alignment: alignment to use for allocator, zero for default
> * @allocator_type: allocator type, SIMPLE, RELOC, ...
> * @strategy: allocation strategy
> *
>@@ -1034,11 +1042,11 @@ __intel_bb_create(int fd, uint32_t ctx, uint32_t vm, const intel_ctx_cfg_t *cfg,
> struct intel_bb *intel_bb_create_full(int fd, uint32_t ctx, uint32_t vm,
> const intel_ctx_cfg_t *cfg, uint32_t size,
> uint64_t start, uint64_t end,
>- uint8_t allocator_type,
>+ uint64_t alignment, uint8_t allocator_type,
> enum allocator_strategy strategy)
> {
> return __intel_bb_create(fd, ctx, vm, cfg, size, false, start, end,
>- allocator_type, strategy);
>+ alignment, allocator_type, strategy);
> }
>
> /**
>@@ -1063,7 +1071,7 @@ struct intel_bb *intel_bb_create_with_allocator(int fd, uint32_t ctx, uint32_t v
> uint32_t size,
> uint8_t allocator_type)
> {
>- return __intel_bb_create(fd, ctx, vm, cfg, size, false, 0, 0,
>+ return __intel_bb_create(fd, ctx, vm, cfg, size, false, 0, 0, 0,
> allocator_type, ALLOC_STRATEGY_HIGH_TO_LOW);
> }
>
>@@ -1102,7 +1110,7 @@ struct intel_bb *intel_bb_create(int fd, uint32_t size)
> bool relocs = is_i915_device(fd) && gem_has_relocations(fd);
>
> return __intel_bb_create(fd, 0, 0, NULL, size,
>- relocs && !aux_needs_softpin(fd), 0, 0,
>+ relocs && !aux_needs_softpin(fd), 0, 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> ALLOC_STRATEGY_HIGH_TO_LOW);
> }
>@@ -1129,7 +1137,7 @@ intel_bb_create_with_context(int fd, uint32_t ctx, uint32_t vm,
> bool relocs = is_i915_device(fd) && gem_has_relocations(fd);
>
> return __intel_bb_create(fd, ctx, vm, cfg, size,
>- relocs && !aux_needs_softpin(fd), 0, 0,
>+ relocs && !aux_needs_softpin(fd), 0, 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> ALLOC_STRATEGY_HIGH_TO_LOW);
> }
>@@ -1150,7 +1158,7 @@ struct intel_bb *intel_bb_create_with_relocs(int fd, uint32_t size)
> {
> igt_require(is_i915_device(fd) && gem_has_relocations(fd));
>
>- return __intel_bb_create(fd, 0, 0, NULL, size, true, 0, 0,
>+ return __intel_bb_create(fd, 0, 0, NULL, size, true, 0, 0, 0,
> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
> }
>
>@@ -1175,7 +1183,7 @@ intel_bb_create_with_relocs_and_context(int fd, uint32_t ctx,
> {
> igt_require(is_i915_device(fd) && gem_has_relocations(fd));
>
>- return __intel_bb_create(fd, ctx, 0, cfg, size, true, 0, 0,
>+ return __intel_bb_create(fd, ctx, 0, cfg, size, true, 0, 0, 0,
> INTEL_ALLOCATOR_NONE, ALLOC_STRATEGY_NONE);
> }
>
>@@ -1195,7 +1203,7 @@ struct intel_bb *intel_bb_create_no_relocs(int fd, uint32_t size)
> {
> igt_require(gem_uses_full_ppgtt(fd));
>
>- return __intel_bb_create(fd, 0, 0, NULL, size, false, 0, 0,
>+ return __intel_bb_create(fd, 0, 0, NULL, size, false, 0, 0, 0,
> INTEL_ALLOCATOR_SIMPLE,
> ALLOC_STRATEGY_HIGH_TO_LOW);
> }
>diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
>index bdb3b6a67..8738cb5c4 100644
>--- a/lib/intel_batchbuffer.h
>+++ b/lib/intel_batchbuffer.h
>@@ -307,7 +307,7 @@ struct intel_bb {
> struct intel_bb *
> intel_bb_create_full(int fd, uint32_t ctx, uint32_t vm,
> const intel_ctx_cfg_t *cfg, uint32_t size, uint64_t start,
>- uint64_t end, uint8_t allocator_type,
>+ uint64_t end, uint64_t alignment, uint8_t allocator_type,
> enum allocator_strategy strategy);
> struct intel_bb *
> intel_bb_create_with_allocator(int fd, uint32_t ctx, uint32_t vm,
>--
>2.41.0
>
next prev parent reply other threads:[~2023-10-19 20:37 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 14:40 [igt-dev] [PATCH i-g-t v4 00/15] PAT and cache coherency support Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 01/15] drm-uapi/xe_drm: sync to get pat and coherency bits Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 02/15] lib/igt_fb: mark buffers as SCANOUT Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 03/15] lib/igt_draw: " Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 04/15] lib/xe: support cpu_caching and coh_mod for gem_create Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 05/15] tests/xe/mmap: add some tests for cpu_caching and coh_mode Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 06/15] lib/intel_pat: add helpers for common pat_index modes Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 07/15] lib/allocator: add get_offset_pat_index() helper Matthew Auld
2023-10-19 14:40 ` [igt-dev] [PATCH i-g-t v4 08/15] lib/intel_blt: support pat_index Matthew Auld
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 09/15] lib/intel_buf: " Matthew Auld
2023-10-20 5:17 ` Niranjana Vishwanathapura
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 10/15] lib/xe_ioctl: update vm_bind to account for pat_index Matthew Auld
2023-10-19 17:37 ` Niranjana Vishwanathapura
2023-10-20 5:19 ` Niranjana Vishwanathapura
2023-10-20 8:13 ` Matthew Auld
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 11/15] lib/intel_allocator: treat default_alignment as the minimum Matthew Auld
2023-10-19 17:34 ` Niranjana Vishwanathapura
2023-10-20 7:55 ` Matthew Auld
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 12/15] lib/intel_blt: tidy up alignment usage Matthew Auld
2023-10-19 20:46 ` Niranjana Vishwanathapura
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 13/15] lib/intel_batchbuffer: extend to include optional alignment Matthew Auld
2023-10-19 20:36 ` Niranjana Vishwanathapura [this message]
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 14/15] tests/xe: add some vm_bind pat_index tests Matthew Auld
2023-10-20 5:27 ` Niranjana Vishwanathapura
2023-10-20 8:21 ` Matthew Auld
2023-10-20 8:42 ` Matthew Auld
2023-10-20 17:24 ` Niranjana Vishwanathapura
2023-10-19 14:41 ` [igt-dev] [PATCH i-g-t v4 15/15] tests/intel-ci/xe: add pat and caching related tests Matthew Auld
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