Re: [PATCH i-g-t] tests/intel/kms_pm_dc: Add a new test to validate the deep sleep state during extended vblank

["Modem, Bhanuprakash" <bhanuprakash.modem@intel.com>]

Hi Jeevan,

On 28-05-2024 03:39 pm, Jeevan B wrote:
> Add a new test to validate deep sleep states during extended vblank
> scenarios, where two frames are committed simultaneously for a given
> time with reduced refresh rate.
> v2: dealy of one frame added to simulate extended vblank.
>      remove vrr related debug checks.
> v3: fix typo and add define. (Suraj)
> v4: fix structure and add skip if no vrr monitor found. (Bhanu)
> v5: remove redundant code and correct delay logic. (Bhanu)
> 
> Signed-off-by: Jeevan B <jeevan.b@intel.com>
> ---
>   tests/intel/kms_pm_dc.c | 72 +++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 72 insertions(+)
> 
> diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
> index 7766d34d7..7ce1b7051 100644
> --- a/tests/intel/kms_pm_dc.c
> +++ b/tests/intel/kms_pm_dc.c
> @@ -76,6 +76,10 @@
>    *
>    * SUBTEST: dc9-dpms
>    * Description: This test validates display engine entry to DC9 state
> + *
> + * SUBTEST: deep-pkgc
> + * Description: This test validates display engine entry to PKGC10 state for extended vblank
> + * Functionality: pm_dc
>    */
>   
>   /* DC State Flags */
> @@ -89,6 +93,7 @@
>   #define PACKAGE_CSTATE_PATH  "pmc_core/package_cstate_show"
>   #define KMS_POLL_DISABLE 0
>   #define DC9_RESETS_DC_COUNTERS(devid) (!(IS_DG1(devid) || IS_DG2(devid) || AT_LEAST_DISPLAY(devid, 14)))
> +#define MSECS (1000000ul)
>   
>   IGT_TEST_DESCRIPTION("Tests to validate display power DC states.");
>   
> @@ -584,6 +589,64 @@ static unsigned int read_pkgc_counter(int debugfs_root_fd)
>   	return get_dc_counter(str);
>   }
>   
> +static void test_deep_pkgc_state(data_t *data)
> +{
> +	unsigned int pre_val = 0, cur_val = 0;
> +	time_t start = time(NULL), duration = 2, delay;
> +	enum pipe pipe;
> +	bool pkgc_flag = false;
> +	bool vrr_supported = false, flip = true;
> +
> +	igt_display_t *display = &data->display;
> +	igt_plane_t *primary;
> +	igt_output_t *output = NULL;
> +
> +	for_each_pipe_with_valid_output(display, pipe, output) {
> +		/* Check VRR capabilities before setting up */
> +		if (igt_output_has_prop(output, IGT_CONNECTOR_VRR_CAPABLE) &&
> +		    igt_output_get_prop(output, IGT_CONNECTOR_VRR_CAPABLE)) {
> +			vrr_supported = true;
> +			break;
> +		}
> +	}
> +
> +	/* Skip the test if no VRR capable output is found */
> +	if (!vrr_supported)
> +		igt_skip("No VRR capable output found, skipping the test.\n");
> +
> +	igt_display_reset(display);
> +
> +	if (output) {

Do we really need this check? if vrr_supported check is pass means there 
is a valid output available.

Apart from that, overall patch looks good to me. You can use my R-b 
after addressing above comment.

Reviewed-by: Bhanuprakash Modem <bhanuprakash.modem@intel.com>

- Bhanu

> +		igt_output_set_pipe(output, pipe);
> +
> +		data->output = output;
> +		data->mode = igt_output_get_mode(output);
> +		setup_videoplayback(data);
> +
> +		primary = igt_output_get_plane_type(data->output, DRM_PLANE_TYPE_PRIMARY);
> +		pre_val = read_pkgc_counter(data->debugfs_root_fd);
> +		delay = 1 * (MSECS / (data->mode->vrefresh - 10));
> +
> +		igt_plane_set_fb(primary, &data->fb_rgb);
> +		igt_display_commit(&data->display);
> +
> +		while (time(NULL) - start < duration) {
> +			flip = !flip;
> +			igt_plane_set_fb(primary, flip ? &data->fb_rgb : &data->fb_rgr);
> +			igt_display_commit(&data->display);
> +
> +			cur_val = read_pkgc_counter(data->debugfs_root_fd);
> +			if (cur_val > pre_val) {
> +				pkgc_flag = true;
> +				break;
> +			}
> +			usleep(delay);
> +		}
> +	}
> +	cleanup_dc3co_fbs(data);
> +	igt_assert_f(pkgc_flag, "PKGC10 is not achieved.\n");
> +}
> +
>   static void test_pkgc_state_dpms(data_t *data)
>   {
>   	unsigned int timeout_sec = 6;
> @@ -687,6 +750,15 @@ igt_main
>   			test_dc_state_psr(&data, CHECK_DC6);
>   	}
>   
> +	igt_describe("This test validates display engine entry to PKGC10 state "
> +		     "during extended vblank");
> +	igt_subtest("deep-pkgc") {
> +		igt_require_f(igt_pm_pc8_plus_residencies_enabled(data.msr_fd),
> +			      "PC8+ residencies not supported\n");
> +		igt_require(intel_display_ver(data.devid) >= 20);
> +		test_deep_pkgc_state(&data);
> +	}
> +
>   	igt_describe("This test validates display engine entry to DC5 state "
>   		     "while all connectors's DPMS property set to OFF");
>   	igt_subtest("dc5-dpms") {