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d="scan'208";a="219919890" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.244.101]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2026 23:28:47 -0800 Date: Tue, 24 Feb 2026 09:28:44 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: igt-dev@lists.freedesktop.org Subject: Re: [PATCH i-g-t v2 01/23] tests/intel/kms_psr: Don't pass uninitialized 'pipe' to intel_fbc_supported_on_chipset() Message-ID: References: <20260221032003.30936-1-ville.syrjala@linux.intel.com> <20260221032003.30936-2-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Mon, Feb 23, 2026 at 01:22:08PM +0200, Jani Nikula wrote: > On Sat, 21 Feb 2026, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Instead passing stack garbage in 'pipe' to > > intel_fbc_supported_on_chipset() iterate over all the CRTCs > > and properly check if any of them supports FBC. > > > > Signed-off-by: Ville Syrjälä > > --- > > tests/intel/kms_psr.c | 11 ++++++++--- > > 1 file changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c > > index c411981c0104..c730a6f23944 100644 > > --- a/tests/intel/kms_psr.c > > +++ b/tests/intel/kms_psr.c > > @@ -774,7 +774,6 @@ int igt_main() > > { > > int z, y; > > enum operations op; > > - enum pipe pipe; > > const char *append_subtest_name[3] = { > > "psr-", > > "psr2-", > > @@ -787,10 +786,12 @@ int igt_main() > > int modes[] = {PSR_MODE_1, PSR_MODE_2, PR_MODE}; > > int fbc_status[] = {FBC_DISABLED, FBC_ENABLED}; > > igt_output_t *output; > > - bool fbc_chipset_support; > > + bool fbc_chipset_support = true; > > int disp_ver; > > > > igt_fixture() { > > + igt_crtc_t *crtc; > > + > > data.drm_fd = drm_open_driver_master(DRIVER_INTEL | DRIVER_XE); > > data.debugfs_fd = igt_debugfs_dir(data.drm_fd); > > kmstest_set_vt_graphics_mode(); > > @@ -799,7 +800,11 @@ int igt_main() > > igt_display_require(&data.display, data.drm_fd); > > igt_require_f(output_supports_psr(&data), "Sink does not support PSR/PSR2/PR\n"); > > disp_ver = intel_display_ver(data.devid); > > - fbc_chipset_support = intel_fbc_supported_on_chipset(data.drm_fd, pipe); > > + > > + for_each_crtc(&data.display, crtc) { > > + if (!intel_fbc_supported_on_chipset(data.drm_fd, crtc->pipe)) > > + fbc_chipset_support = false; > > The commit message says "if any of them", but this requires all of them > to support FBC, which is unlikely. Hmm, yeah that is definitely a problem for hsw+. I guess I'll just reverse the logic here. intel_fbc_supported_on_chipset() should probably itself iterate all the CRTCs, but with the current low level API that'd be a bit inconvenient to implement. We should probably look into changing the intel_fbc*() API to take igt_display_t/igt_crtc_t/etc. as well... -- Ville Syrjälä Intel