[PATCH 1/1] lib/gpgpu_shader: set r1.4 to dim.x

Jan Maslak
2026-02-10T10:24:34Z

Sets up the r1.4 to contain the value of dim.x, making it accessible from
the shader.

Signed-off-by: Jan Maslak <jan.maslak@intel.com>
---
lib/gpgpu_fill.c.gen.iga64_codes.c | 2 +-
lib/gpgpu_shader.c | 6 ++++--
lib/gpgpu_shader.c.gen.iga64_codes.c | 2 +-
lib/iga64_macros.h | 1 +
tests/intel/xe_eudebug_online.c.gen.iga64_codes.c | 2 +-
5 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/lib/gpgpu_fill.c.gen.iga64_codes.c b/lib/gpgpu_fill.c.gen.iga64_codes.c
index b223425d0..15ffb6f2d 100644
--- a/lib/gpgpu_fill.c.gen.iga64_codes.c
+++ b/lib/gpgpu_fill.c.gen.iga64_codes.c
@@ -3,7 +3,7 @@

#include "gpgpu_shader.h"

-#define MD5_SUM_IGA64_ASMS 8304c8bb11385470bfd6ac32e1c36840
+#define MD5_SUM_IGA64_ASMS b785dce133b8fcf480cd65b219b3e008

struct iga64_template const iga64_code_gpgpu_fill[] = {
{ .gen_ver = 2000, .size = 44, .code = (const uint32_t []) {
diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 767bddb7b..abccb4808 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -151,13 +151,15 @@ __xelp_gpgpu_execfunc(struct intel_bb *ibb,
}

static void
-fill_inline_data(uint32_t *inline_data, uint64_t target_offset, struct intel_buf *target)
+fill_inline_data(uint32_t *inline_data, uint64_t target_offset, struct intel_buf *target,
+ uint32_t x_dim)
{
igt_assert(target->surface[0].stride == intel_buf_width(target) * target->bpp/8);
*inline_data++ = lower_32_bits(target_offset);
*inline_data++ = upper_32_bits(target_offset);
*inline_data++ = target->surface[0].stride;
*inline_data++ = intel_buf_height(target);
+ *inline_data++ = x_dim;
}

static void
@@ -206,7 +208,7 @@ __xehp_gpgpu_execfunc(struct intel_bb *ibb,
/* Inline data is at 31th/32th dword of COMPUTE_WALKER, BSpec: 67028 */
inline_data = intel_bb_ptr(ibb) + 4 * (shdr->gen_ver < 2000 ? 31 : 32);
xehp_emit_compute_walk(ibb, 0, 0, x_dim * 16, y_dim, &idd, 0x0);
- fill_inline_data(inline_data, CANONICAL(target->addr.offset), target);
+ fill_inline_data(inline_data, CANONICAL(target->addr.offset), target, x_dim);

intel_bb_out(ibb, MI_BATCH_BUFFER_END);
intel_bb_ptr_align(ibb, 32);
diff --git a/lib/gpgpu_shader.c.gen.iga64_codes.c b/lib/gpgpu_shader.c.gen.iga64_codes.c
index fffe242fe..ee45f8263 100644
--- a/lib/gpgpu_shader.c.gen.iga64_codes.c
+++ b/lib/gpgpu_shader.c.gen.iga64_codes.c
@@ -3,7 +3,7 @@

#include "gpgpu_shader.h"

-#define MD5_SUM_IGA64_ASMS f5d2183439f5e7b18097c3c2c2957dbb
+#define MD5_SUM_IGA64_ASMS b3ca58d01d637034cf62ec574656a2f0

struct iga64_template const iga64_code_read_a64_d32[] = {
{ .gen_ver = 2000, .size = 40, .code = (const uint32_t []) {
diff --git a/lib/iga64_macros.h b/lib/iga64_macros.h
index 8e452cf63..76a330ab5 100644
--- a/lib/iga64_macros.h
+++ b/lib/iga64_macros.h
@@ -27,6 +27,7 @@
#define R1_TGT_ADDRESS r1.0<0;1,0>:uq
#define R1_TGT_WIDTH r1.2<0;1,0>:ud
#define R1_TGT_HEIGHT r1.3<0;1,0>:ud
+#define R1_DIM_X r1.4<0;1,0>:ud

#define SET_SHARED_MEDIA_BLOCK_MSG_HDR(dst, y, width) \
(W) mov (8) dst.0<1>:ud 0x0:ud ;\
diff --git a/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c b/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c
index 3bd5b0c5f..32009e40f 100644
--- a/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c
+++ b/tests/intel/xe_eudebug_online.c.gen.iga64_codes.c
@@ -3,7 +3,7 @@

#include "gpgpu_shader.h"

-#define MD5_SUM_IGA64_ASMS f0897ea23eff7ea77569eca6ddd16161
+#define MD5_SUM_IGA64_ASMS d8acd22fb8afb78633ac79a0ca42d8da

struct iga64_template const iga64_code_store_sr0_0[] = {
{ .gen_ver = 2000, .size = 40, .code = (const uint32_t []) {
--
2.34.1