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24 Feb 2026 00:53:43 -0800 From: Jani Nikula To: Ville Syrjala , igt-dev@lists.freedesktop.org Subject: Re: [PATCH i-g-t v3 01/23] tests/intel/kms_psr: Don't pass uninitialized 'pipe' to intel_fbc_supported_on_chipset() In-Reply-To: <20260224084947.12493-1-ville.syrjala@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland References: <20260221032003.30936-2-ville.syrjala@linux.intel.com> <20260224084947.12493-1-ville.syrjala@linux.intel.com> Date: Tue, 24 Feb 2026 10:53:40 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" On Tue, 24 Feb 2026, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Instead passing stack garbage in 'pipe' to > intel_fbc_supported_on_chipset() iterate over all the CRTCs > and properly check if any of them supports FBC. > > v2: Reverse the logic to not require every CRTC to support FBC, > which is indeed not the case on gen2/gen3/hsw+ (Jani) > > Cc: Jani Nikula > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > tests/intel/kms_psr.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/tests/intel/kms_psr.c b/tests/intel/kms_psr.c > index c411981c0104..0ffe4c92b25b 100644 > --- a/tests/intel/kms_psr.c > +++ b/tests/intel/kms_psr.c > @@ -774,7 +774,6 @@ int igt_main() > { > int z, y; > enum operations op; > - enum pipe pipe; > const char *append_subtest_name[3] =3D { > "psr-", > "psr2-", > @@ -787,10 +786,12 @@ int igt_main() > int modes[] =3D {PSR_MODE_1, PSR_MODE_2, PR_MODE}; > int fbc_status[] =3D {FBC_DISABLED, FBC_ENABLED}; > igt_output_t *output; > - bool fbc_chipset_support; > + bool fbc_chipset_support =3D false; > int disp_ver; >=20=20 > igt_fixture() { > + igt_crtc_t *crtc; > + > data.drm_fd =3D drm_open_driver_master(DRIVER_INTEL | DRIVER_XE); > data.debugfs_fd =3D igt_debugfs_dir(data.drm_fd); > kmstest_set_vt_graphics_mode(); > @@ -799,7 +800,11 @@ int igt_main() > igt_display_require(&data.display, data.drm_fd); > igt_require_f(output_supports_psr(&data), "Sink does not support PSR/P= SR2/PR\n"); > disp_ver =3D intel_display_ver(data.devid); > - fbc_chipset_support =3D intel_fbc_supported_on_chipset(data.drm_fd, pi= pe); > + > + for_each_crtc(&data.display, crtc) { > + if (intel_fbc_supported_on_chipset(data.drm_fd, crtc->pipe)) > + fbc_chipset_support =3D true; > + } > } >=20=20 > for (y =3D 0; y < ARRAY_SIZE(fbc_status); y++) { --=20 Jani Nikula, Intel